Featured Device - Altera Cyclone III Reference Manual

Table 2–1. Cyclone III FPGA Starter Board (Part 2 of 2)
Component/
Type
Interface
Clock Circuitry
Oscillator Clock
Power Supply
Input DC power
jack
Input Power switch
Probe point Current sense
resistor
Probe point Current sense
resistor
Featured
Device
Table 2–2. Cyclone III Device Features
Architectural
Feature
Altera's ●
third-generation of ●
low-cost FPGAs ●
●
Lowest power
●
consumption ●
FPGA available ●
●
●
Increased system ●
integration
●
●
●
●
Altera Corporation
April 2012
Board Reference
Y1
J2
SW1
JP6
JP3
The Cyclone III FPGA Starter Kit features the EP3C25F324 device (U1) in
a 324-pin FineLine BGA (FBGA)
device features.
Lowest overall FPGA system cost available
Staggered I/O ring to decrease die area
Wide range of low-cost packages
Support for low-cost serial and parallel flash for configuration options
Based on the TSMC's low-power 65nm process
Supports hot-socketing
Unused I/O banks can be powered down
Extends battery life for portable or hand-held applications
Eliminates or reduces cooling system costs
Densities up to 119,088 logic elements
High memory-to-logic ratio
Highest multiplier-to-logic ratio in the industry
Up to four dynamically reconfigurable, cascadable phase-locked-loops (PLLs), each
with up to five outputs
Multi-value on-chip termination (OCT) support with calibration feature.
Board Components and Interfaces
Description
50-MHz clock oscillator used for the system
clock.
12-V DC unregulated power source.
Switches the board's power on and off.
Measure FPGA core power with current
sense resistor.
Measure 2.5-V I/O power (shared between
devices) with current sense resistor.
package. Table 2–2
Results
Cyclone III FPGA Starter Board Reference Manual
Page
2–6
2–19
2–19
N/A
N/A
lists Cyclone III
2–5