Altera Max10 FPGA Manual

Altera Max10 FPGA Manual

Board update portal based on nios ii processor

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Board Update Portal based on NIOS II
Processor Using the MAX 10 FPGA
Development Kit
©2015 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and
STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in ot her
countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in accordance
with Altera' s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera
assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as
expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest version of device specifications before relying on
any published information and before placing orders for products or services.

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Summary of Contents for Altera Max10 FPGA

  • Page 1 Altera warrants performance of its semiconductor products to current specifications in accordance with Altera' s standard warranty, but reserves the right to make changes to any products and services at any time without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to in writing by Altera.
  • Page 2: Revision History

    Revision history Version Author Date Changes Reason Martin Chen 6/1/2015 Initial release...
  • Page 3: Table Of Contents

    Table of Contents Revision history ..........................2 Table of Contents.......................... 3 Overview ............................4 Theory of Operation ........................5 Simple Demo Setup ........................6 How to recompile the hardware build ................... 8 Convert SOF file to POF file ......................9 How to recompile the software build...................
  • Page 4: Overview

    Quartus v15.0.0/145 or later is required for this design example. Please refer to the Altera Download Center for information on updates IMPORTANT: only use the 12V, 2A AC adapter that came with this kit. Do not use  other power supplies from other Altera kits   Figure 1: Max10 FPGA Development Kit...
  • Page 5: Theory Of Operation

    Theory of Operation On-Chip Memory QSPI Flash DDR3 SDRAM (Optional) Nios® II Core UART Ethernet Core SGDMA TX SGDMA RX On-Chip Description Memory Figure 2: BUP design example block diagram The Nios® II processor is used to implement a web server in MAX 10 FPGA device. Please see application note AN429: Remote Configuration Over Ethernet with the Nios®...
  • Page 6: Simple Demo Setup

    Simple Demo Setup 1. Connect the power cord to the power plug of the kit 2. Connect a mini USB from your PC/laptop to the J12 USB connector (labeled as USB 1 on the silkscreen) on the top left of the kit 3.
  • Page 7 Figure 4: Link establishment and IP address acquirement...
  • Page 8: How To Recompile The Hardware Build

    The following steps describe how to setup a project in Quartus II software in order to configure the MAX10 FPGA device with the m10_rgmii (BUP) demo design. 1. Launch Quartus II software and open the project top.qpf using File->Open Project 2.
  • Page 9: Convert Sof File To Pof File

    Convert SOF file to POF file Please follow the steps on how to convert SOF file to POF file for MAX 10 FPGA internal configuration solution. For dual configuration feature, please turn to the "Selecting the Internal Configuration Scheme" section of the User Guide for more details. 1.
  • Page 10: How To Recompile The Software Build

    How to recompile the software build Please follow the steps on how to recompile the software build under different conditions. 1. Compile the software build without any modifications a) Open NIOS command shell (v15.0.0/145 or later) and change to the directory: <BUP Root Directory>...
  • Page 11: Convert Nios Executable File To .Flash File

    Convert NIOS executable file to .flash file You should convert executable file to .flash file so that you can program it into QSPI flash with BUP build, you should use the elf2flash utility to create the flash image: 1. Open NIOS command shell (v15.0.0/145 or later) 2.
  • Page 12: Program Images Into On-Chip Cfm Flash And External Qspi Flash

    3. Make sure Ethernet cable is connected to port A (the bottom one) 4. Power cycle the board or push S5 button to boot up from BUP build (BUP A) 5. Open NIOS command shell at *\altera\15.0\nios2eds\, e.g. double click "Nios II Command Shell.bat"...
  • Page 13 Figure 9: Factory build restoration page 11. Load "*\software_examples\factory_images\m10_fpga_html.zip" in "Webpages File Name" column and "*\software_examples\factory_images\ext_flash.flash" in "Software File Name" column and then upload them Figure 10: Raw page for factory recovery 12. Check whether it uploads successfully or not 13.

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