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Stratix III Device Handbook, Volume 1

101 Innovation Drive

San Jose, CA 95134

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SIII5V1-1.4

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Page 1 Stratix III Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V1-1.4...
Page 2 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S.
Page 3: Table Of Contents
Software ............................1–14 Ordering Information ........................1–15 Referenced Documents ........................1–16 Document Revision History ....................... 1–16 Chapter 2. Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Introduction ............................2–1 Logic Array Blocks ..........................2–1 LAB Interconnects ..........................2–3...
Page 4 DSP Block Interface ..........................3–10 I/O Block Connections to Interconnect .................... 3–13 Conclusion ............................3–14 Document Revision History ....................... 3–15 Chapter 4. TriMatrix Embedded Memory Blocks in Stratix III Devices Introduction ............................4–1 Overview ..............................4–1 TriMatrix Memory Block Types ..................... 4–3 Parity Bit Support ..........................
Page 5 Conclusion ............................5–49 Referenced Documents ........................5–49 Document Revision History ....................... 5–50 Chapter 6. Clock Networks and PLLs in Stratix III Devices Introduction ............................6–1 Clock Networks in Stratix III Devices ....................6–1 Clock Input Connections to PLLs ....................6–12 Clock Output Connections ......................
Page 6 Contents Stratix III Device Handbook, Volume 2 Stratix III PLL Hardware Overview .................... 6–24 Stratix III PLL Software Overview ....................6–28 Clock Feedback Modes ........................6–32 Clock Multiplication and Division ....................6–38 Post-Scale Counter Cascading ...................... 6–39 Programmable Duty Cycle ......................6–40 PLL Control Signals ........................
Page 7 PLL ..............................8–45 Conclusion ............................8–45 Referenced Documents ........................8–46 Document Revision History ....................... 8–46 Chapter 9. High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Introduction ............................9–1 I/O Banks ..............................9–2 LVDS Channels ............................9–3 Differential Transmitter ........................9–4 Receiver Data Realignment Circuit (Bit Slip) ................
Page 8 Devices Can Be Driven Before Power-Up .................. 10–2 I/O Pins Remain Tri-Stated During Power-Up ................. 10–2 Insertion or Removal of a Stratix III Device from a Powered-Up System ......10–2 Hot Socketing Feature Implementation in Stratix III Devices ............10–3 Power-On Reset Circuitry ........................
Page 9 Conclusion ............................12–16 Referenced Documents ........................12–16 Document Revision History ......................12–16 Chapter 13. IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Introduction ............................13–1 IEEE Std. 1149.1 BST Architecture ....................13–2 IEEE Std. 1149.1 Boundary-Scan Register ..................13–4 Boundary-Scan Cells of a Stratix III Device I/O Pin ..............
Page 10 Referenced Documents ........................15–14 Document Revision History ......................15–14 Section V. Power and Thermal Management Chapter 16. Programmable Power and Temperature Sensing Diode in Stratix III Devices Introduction ............................16–1 Stratix III Power Technology ......................16–2 Selectable Core Voltage ......................... 16–2 Programmable Power Technology ....................
Page 11 External Pin Connections ......................16–7 Conclusion ............................16–7 Referenced Documents ........................16–7 Document Revision History ....................... 16–8 Section VI. Packaging Information Chapter 17. Stratix III Device Packaging Information Introduction ............................17–1 Thermal Resistance ..........................17–2 Package Outlines ..........................17–2 Referenced Documents ........................17–2 Document Revision History .......................
Page 12 Contents Stratix III Device Handbook, Volume 2 Altera Corporation...
Page 13: Chapter Revision Dates
Chapter Revision Dates The chapters in this book, Stratix III Device Handbook, Volume 1, were revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Stratix III Device Family Overview...
Page 14 Chapter Revision Dates Stratix III Device Handbook, Volume 1 Chapter 10. Hot Socketing and Power-On Reset in Stratix III Devices Revised: October 2007 Part number: SIII51010-1.2 Chapter 11. Configuring Stratix III Devices Revised: November 2007 Part number: SIII51011-1.3 Chapter 12. Remote System Upgrades With Stratix III Devices...
Page 15: About This Handbook
® Stratix III family of devices. How to Contact For the most up-to-date information about Altera products, go to the Altera world-wide web site at www.altera.com. For technical support on Altera this product, go to www.altera.com/mysupport. For additional information about Altera products, consult the sources shown below.
Page 16 Typographic Conventions Stratix III Device Handbook, Volume 1 Visual Cue Meaning Italic type Internal timing parameters and variables are shown in italic type. Examples: t , n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type.
Page 17: Section I. Device Core
Stratix III Devices ■ Chapter 3, MultiTrack Interconnect in Stratix III Devices ■ Chapter 4, TriMatrix Embedded Memory Blocks in Stratix III Devices ■ Chapter 5, DSP Blocks in Stratix III Devices ■ Chapter 6, Clock Networks and PLLs in Stratix III Devices Revision History Refer to each chapter for its own specific revision history.
Page 18 Device Core Stratix III Device Handbook, Volume 1 Section I–2 Altera Corporation...
Page 19: Chapter 1. Stratix Iii Device Family Overview
The Stratix III L family provides balanced logic, memory, and multiplier ratios for mainstream applications. ■ The Stratix III E family is memory and multiplier rich for data-centric applications. Modular I/O banks with a common bank structure for vertical migration lend efficiency and flexibility to the high speed I/O.
Page 20: Features
Introduction Features Stratix III devices offer the following features: ■ 48,000 to 338,000 equivalent logic elements (LEs), see Table 1–1 ■ 2,430 to 20,497 Kbits of enhanced TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers ■...
Page 21 The EP3SE260 device is rich in LE, memory, and multiplier resources. Hence, it aligns with both logic (L) and enhanced (E) variants. The Stratix III logic family (L) offers balanced logic, memory, and multipliers to address a wide range of applications, while the enhanced family (E) offers more memory and multipliers per logic and is ideal for wireless, medical imaging, and military applications.
Page 22 Introduction Table 1–2 lists the Stratix III FPGA package options and I/O pin counts. Table 1–2. Package Options and I/O Pin Counts Note (1) 484-Pin 780-Pin 1152-Pin 1,517-Pin 1,760-Pin Device FineLine FineLine FineLine FineLine FineLine EP3SL50 — — — EP3SL70 —...
Page 23: Architecture Features
Length/Width (mm/mm) 33/33 40/40 Stratix III devices are available in up to three speed grades, -2, -3, and -4, with -2 being the fastest. Stratix III devices are offered in both commercial and industrial temperature range ratings with leaded and lead-free packages.
Page 24: Multitrack Interconnect
TriMatrix Embedded Memory Blocks in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. MultiTrack Interconnect In the Stratix III architecture, connections between ALMs, TriMatrix memory, DSP blocks, and device I/O pins are provided by the MultiTrack interconnect structure with DirectDrive technology.
Page 25: Trimatrix Embedded Memory Blocks
(FIR) filters, complex FIR filters, infinite impulse response (IIR) filters, fast Fourier transform (FFT) functions, and discrete cosine transform (DCT) functions. Stratix III devices have up to 112 DSP blocks. The architectural highlights of the Stratix III DSP block are the following: ■...
Page 26: Clock Networks And Plls
(PCLKs). These clocks are organized into a hierarchical clock structure that provides up to 104 unique clock domains (16 GCLK + 88 RCLK) within the Stratix III device and allows for up to 38 (16 GCLK + 22 RCLK) unique GCLK/RCLK clock sources per device quadrant.
Page 27: I/O Banks And I/O Structure
1 of the Stratix III Device Handbook. I/O Banks and I/O Structure Stratix III devices contain up to 24 modular I/O banks, each of which contains 24, 32, 36, 40 or 48 I/Os. This modular bank structure improves pin efficiency and eases device migration.
Page 28: High Speed Differential I/O Interfaces With Dpa
I/O interconnect standards and applications: Utopia IV, SPI-4.2, SFI-4, 10 Gigabit Ethernet XSLI, Rapid I/O, and NPSI. Stratix III devices support 2×, 4×, 6×, 7×, 8× and 10× SERDES modes for high speed differential I/O interfaces and 4×, 6×, 7×, 8×...
Page 29: Configuration
The hot-socketing feature also makes it easier to use Stratix III devices on printed circuit boards (PCBs) that also contain a mixture of 3.3-V, 3.0-V, 2.5-V, 1.8-V, 1.5-V and 1.2-V devices.
Page 30: Remote System Upgrades
Boundary-scan cells in the Stratix III device can force signals onto pins or capture data from pin or logic array signals. Forced test data is serially shifted into the boundary-scan cells.
Page 31: Seu Mitigation
FPGA. The Quartus II software (starting from Version 6.1) automatically optimizes designs to meet the performance goals while simultaneously leveraging the programmable power saving options available in the Stratix III FPGA without the need for any changes to the design flow. Altera Corporation 1–13...
Page 32: Signal Integrity
Ordering Information Software Stratix III devices are supported by the Altera Quartus II design software, version 6.1, which provides a comprehensive environment for system-on-a-programmable-chip (SOPC) design. The Quartus II software includes HDL and schematic design entry, compilation and logic ®...
Page 33: Ordering Information
® the NativeLink interface. Ordering Information Figure 1–1 describes the ordering codes for Stratix III devices. For more information on a specific package, refer to the Stratix III Device Package Information chapter of the Stratix III Device Handbook. Figure 1–1. Stratix III Device Packaging Ordering Information...
Page 34: Referenced Documents
DSP Blocks in Stratix III Devices ■ External Memory Interfaces in Stratix III Devices ■ High Speed Differential I/O Interfaces with DPA in Stratix III Devices ■ Hot Socketing and Power-On Reset in Stratix III Devices ■ IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Devices ■...
Page 35: Introduction
II Compiler places associated logic in an LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. Figure 2–1 shows the Stratix III LAB structure and the LAB interconnects. Altera Corporation 2–1 October 2007...
Page 36 Variable Speed & Length from Either Side by Columns & LABs, & from Above by Rows The LAB of Stratix III has a new derivative called Memory LAB (MLAB), which adds look-up table (LUT)-based SRAM capability to the LAB as shown in Figure 2–2.
Page 37: Lab Interconnects
Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Figure 2–2. Stratix III LAB and MLAB Structure LUT-based-64 x 1 Simple dual port SRAM LUT-based-64 x 1 Simple dual port SRAM LUT-based-64 x 1 Simple dual port SRAM...
Page 38: Lab Control Signals
If the LAB uses both the rising and falling edges of a clock, it also uses two LAB-wide clock signals. De-asserting the clock enable signal turns off the corresponding LAB-wide clock. 2–4 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 39: Adaptive Logic Modules
Adaptive Logic The basic building block of logic in the Stratix III architecture, the adaptive logic module (ALM), provides advanced features with efficient Modules logic utilization. Each ALM contains a variety of look-up table (LUT)-based resources that can be divided between two combinational adaptive LUTs (ALUTs) and two registers.
Page 40 Stratix III ALM while Figure 2–6 shows a detailed view of all the connections in an ALM. Figure 2–5. High-Level Block Diagram of the Stratix III ALM shared_arith_in carry_in reg_chain_in labclk Combinational/Memory ALUT0...
Page 41 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Figure 2–6. Stratix III ALM Details Altera Corporation 2–7 October 2007 Stratix III Device Handbook, Volume 1...
Page 42: Alm Operating Modes
LUT. This provides another mechanism for improved fitting. The ALM can also drive out registered and unregistered versions of the LUT or adder output. ALM Operating Modes The Stratix III ALM can operate in one of the following modes: ■ Normal ■...
Page 43 In this mode, up to eight data inputs from the LAB local interconnect are inputs to the combinational logic. The normal mode allows two functions to be implemented in one Stratix III ALM, or an ALM to implement a single function of up to six inputs. The ALM can support certain combinations of completely independent functions and various combinations of functions that have common inputs.
Page 44 The common inputs are dataa and datab. The combination of a four-input function with a five-input function requires one common input (either dataa or datab). 2–10 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 45 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices In the case of implementing 2 six-input functions in one ALM, four inputs must be shared and the combinational function must be the same. For example, a 4 2 crossbar switch (two 4-to-1 multiplexers with common ×...
Page 46 Functions that fit into the template shown in Figure 2–10 occur naturally in designs. These functions often appear in designs as "if-else" statements in Verilog HDL or VHDL code. 2–12 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 47 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Figure 2–10. Template for Supported Seven-Input Functions in Extended LUT Mode datae0 datac dataa 5-Input datab To general or datad local routing dataf0 combout0 To general or local routing...
Page 48 50% for functions that can use this ability. An example of such functionality is a conditional operation, such as the one shown in Figure 2–12. 2–14 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 49 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Figure 2–12. Conditional Operation Example Adder output is not used. ALM 1 X[0] Comb & X[0] Adder R[0] To general or Y[0] Logic local routing reg0 syncdata syncload X[1] Comb &...
Page 50 The carry chain provides a fast carry function between the dedicated adders in arithmetic or shared arithmetic mode. The two-bit carry select feature in Stratix III devices halves the propagation delay of carry chains within the ALM. Carry chains can begin in either the first ALM or the fifth ALM in an LAB.
Page 51 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Shared Arithmetic Mode In shared arithmetic mode, the ALM can implement a three-input add within an ALM. In this mode, the ALM is configured with 4 four-input LUTs. Each LUT either computes the sum of three inputs or the carry of three inputs.
Page 52 The shared arithmetic chains can begin in either the first or sixth ALM in an LAB. The Quartus II Compiler creates shared arithmetic chains longer than 20 (10 ALMs in arithmetic or shared arithmetic mode) by linking 2–18 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 53 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices LABs together automatically. For enhanced fitting, a long shared arithmetic chain runs vertically allowing fast horizontal connections to TriMatrix memory and DSP blocks. A shared arithmetic chain can continue as far as a full column.
Page 54: Register Chain
ALMs while saving local interconnect resources (refer to Figure 2–17). The Quartus II Compiler automatically takes advantage of these resources to improve utilization and performance. 2–20 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 55 Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Figure 2–17. Register Chain within an LAB Note (1) From previous ALM within the LAB reg_chain_in labclk To general or local routing To general or adder0 local routing reg0...
Page 56: Alm Interconnects
ALM 9 ALM 10 Refer to the MultiTrack Interconnect in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook for information on routing between LABs. 2–22 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 57: Clear And Preset Logic Control
Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices Clear and Preset Logic Control LAB-wide signals control the logic for the register's clear signal. The ALM directly supports an asynchronous clear function. You can achieve the register preset through the Quartus II software’s NOT-gate push-back logic option.
Page 58: Conclusion
Conclusion Logic array block and adaptive logic modules are the basic building blocks of the Stratix III device. You can use these to configure logic functions, arithmetic functions, and register functions. The ALM provides advanced features with efficient logic utilization and is completely backward-compatible.
Page 59: Chapter 3. Multitrack Interconnect In Stratix Iii Devices
(DSP) blocks, and input/output elements (IOE). These blocks communicate with themselves and to one another through a fabric of routing wires. This chapter provides details on the Stratix III core routing structure. It also describes how Stratix III block types interface to this fabric.
Page 60 R4 Interconnect Driving Left MLAB Neighbor Neighbor Notes to Figure 3–1 C4 and C12 interconnects can drive R4 interconnects. This pattern is repeated for every LAB in the LAB row. 3–2 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 61: Column Interconnects
C12 column interconnects for high-speed vertical routing through the device Stratix III devices include an enhanced interconnect structure in LABs for routing-shared arithmetic chains and carry chains for efficient arithmetic functions. The register chain connection allows the register output of one ALM to connect directly to the register input of the next ALM in the LAB for fast shift registers.
Page 62 IOEs. For LAB interconnection, a primary LAB or its LAB neighbor can drive a given C4 interconnect. C4 interconnects can drive each other to extend their range as well as drive row interconnects for column-to-column connections. 3–4 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 63 MultiTrack Interconnect in Stratix III Devices Figure 3–3. C4 Interconnect Connections Note (1) C4 Interconnects Drives Local and R4 Interconnects up to Four Rows C4 Interconnects Driving Up Interconnects Adjacent LAB can drive onto neighboring LAB's C4 interconnect Local Interconnect...
Page 64 These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. Table 3–1 shows the Stratix III device's routing scheme. Table 3–1. Stratix III Device Routing Scheme (Part 1 of 2) Destination Source Shared...
Page 65 MultiTrack Interconnect in Stratix III Devices Table 3–1. Stratix III Device Routing Scheme (Part 2 of 2) Destination Source Shared Direct Regis- Local MLAB Col- Arith- Carry Link M144K Inter- Inter- Inter- Inter- Inter- metic Chain Inter- Block Blocks Chain...
Page 66: Memory Block Interface
Interface memory blocks interface to the routing structure. The RAM blocks in Stratix III devices have local interconnects to allow ALMs and interconnects to drive into RAM blocks. The MLAB RAM block local interconnect is driven by the R4, C4, and direct link interconnects from adjacent LABs.
Page 67 MultiTrack Interconnect in Stratix III Devices The M9K RAM block local interconnect is driven by the R4, C4, and direct link interconnects from adjacent LABs. The M9K RAM blocks can communicate with LABs on either the left or right side through these row resources or with LAB columns on either the right or left with the column resources.
Page 68: Dsp Block Interface
Block Interconnect Region Block Interconnect Region DSP Block Stratix III device DSP block input registers can generate a shift register that cascades down in the same DSP block column. Dedicated Interface connections between DSP blocks provide fast connections between the shift register inputs to cascade the shift register chains.
Page 69 MultiTrack Interconnect in Stratix III Devices These outputs work similarly to LAB outputs. Eighteen outputs from the DSP block can drive to the left LAB through direct link interconnects and eighteen can drive to the right LAB though direct link interconnects. All 36 outputs can drive to R4 and C4 routing interconnects.
Page 70 DSP Block Row Structure Control A[35..0] OA[17..0] B[35..0] OB[17..0] Row Interface Block DSP Block to 72 Inputs per Row 36 Outputs per Row LAB Row Interface Block Interconnect Region 3–12 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 71: I/O Block Connections To Interconnect
MultiTrack Interconnect in Stratix III Devices I/O Block The IOEs are located in I/O blocks around the periphery of the Stratix III device. There are up to four IOEs per row I/O block and four IOEs per Connections to column I/O block. The row I/O blocks drive row, column, or direct link interconnects.
Page 72: Conclusion
Interconnects C4 Interconnects Conclusion Stratix III devices consist of an array of logic blocks such as LABs, TriMatrix memory, DSP blocks, and IOEs. These blocks communicate with themselves and one another through the MultiTrack interconnect structures. The Quartus II compiler automatically routes critical design paths on faster interconnects to improve design performance and optimize the device resources.
Page 73: Document Revision History
MultiTrack Interconnect in Stratix III Devices Document Table 3–3 shows the revision history for this document. Revision History Table 3–3. Document Revision History Date and Document Changes Made Summary of Changes Version October 2007 ● Minor formatting changes. Minor formatting changes.
Page 74 Document Revision History 3–16 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 75: Introduction
4. TriMatrix Embedded Memory Blocks in Stratix III Devices SIII51004-1.3 Introduction TriMatrix embedded memory blocks provide three different sizes of ® embedded SRAM to efficiently address the needs of Stratix III FPGA designs. TriMatrix memory includes 640-bit memory logic array blocks (MLABs), 9-Kbit M9K blocks, and 144-Kbit M144K blocks.
Page 76 ECC Support Soft IP support Soft IP support Built-in support in via Quartus II via Quartus II ×64 wide SDP mode or soft IP support via Quartus II 4–2 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 77: Trimatrix Memory Block Types
TriMatrix Embedded Memory Blocks in Stratix III Devices Table 4–2 shows the capacity and distribution of the TriMatrix memory blocks in each Stratix III family member Table 4–2. TriMatrix Memory Capacity and Distribution in Stratix III Devices Total Dedicated RAM M144K Total RAM Bits...
Page 78 Quartus II software. When a byte-enable bit is asserted during a write cycle, the corresponding data byte output also depends on the setting chosen in the Quartus II software. 4–4 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 79: Packed Mode Support
(asynch) Packed Mode Support Stratix III M9K and M144K blocks support packed mode. The packed mode feature packs two independent single-port RAMs into one memory block. The Quartus II software automatically implements packed mode where appropriate by placing the physical RAM block into true dual-port mode and using the most significant bit (MSB) of the address to distinguish between the two logical RAMs.
Page 80 Figure 4–3 shows the address clock enable waveform during the read cycle. Figure 4–3. Stratix III Address Clock Enable during Read Cycle Waveform inclock rdaddress rden addressstall latched address (inside memory) q (synch) dout0...
Page 81: Mixed Width Support
TriMatrix Embedded Memory Blocks in Stratix III Devices Figure 4–4 shows the address clock enable waveform during write cycle. Figure 4–4. Stratix III Address Clock Enable during Write Cycle Waveform inclock wraddress data wren addressstall latched address (inside memory) contents at a0...
Page 82: Error Correction Code (Ecc) Support
For more information, refer to the RAM Megafunction User Guide. Error Correction Code (ECC) Support Stratix III M144K blocks have built-in support for error correction code (ECC) when in 64-wide simple dual-port mode. ECC allows you to × detect and correct data errors in the memory array. The M144K blocks have a single-error-correction double-error-detection (SECDED) implementation.
Page 83: Memory Modes
Block Data Output Memory Modes Stratix III TriMatrix memory blocks allow you to implement fully synchronous SRAM memory in multiple modes of operation. M9K and M144K blocks do not support asynchronous memory (unregistered inputs). MLABs support asynchronous (flow-through) read operations.
Page 84: Single Port Ram
® in the RAM MegaWizard in the Quartus II software. See “Read During Write” on page 4–21 for more details on this behavior. 4–10 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 85 TriMatrix Embedded Memory Blocks in Stratix III Devices Table 4–4 shows the possible port width configurations for TriMatrix memory blocks in single-port mode. Table 4–4. Stratix III Port Width Configurations for MLABs, M9K Blocks, and M144K Blocks (Single-Port Mode) MLABs M9K Blocks...
Page 86: Simple Dual-Port Mode
M9K blocks in simple dual-port mode. MLABs do not have native support for mixed width operation. The Quartus II software can implement mixed width memories in MLABs by using more than one MLAB. Table 4–5. Stratix III M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) Write Port Read Port ×...
Page 87 TriMatrix Embedded Memory Blocks in Stratix III Devices Table 4–6 shows the mixed width configurations for the M144K blocks in simple dual-port mode. Table 4–6. Stratix III M144K Block Mixed-Width Configurations (Simple Dual-Port Mode) Write Port Read Port × ×...
Page 88 Registering the RAM's outputs would simply delay the q output by one clock cycle. Figure 4–10. Stratix III Simple Dual-Port Timing Waveforms wrclock wren wraddress...
Page 89: True Dual-Port Mode
Table 4–7 lists the possible M9K block mixed-port width configurations in true dual-port mode. Table 4–7. Stratix III M9K Block Mixed-Width Configuration (True Dual-Port Mode) (Part 1 of 2) Write Port Read Port ×...
Page 90 Memory Modes Table 4–7. Stratix III M9K Block Mixed-Width Configuration (True Dual-Port Mode) (Part 2 of 2) Write Port Read Port × × × × × × × 512×16 — — 1K×9 — — — — — 512×18 — —...
Page 91: Shift-Register Mode
Shift-Register Mode All Stratix III memory blocks support shift register mode. Embedded memory block configurations can implement shift registers for digital signal processing (DSP) applications, such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross-correlation functions.
Page 92: Rom Mode
Shift Register ROM Mode All Stratix III TriMatrix memory blocks support ROM mode. A memory initialization file (.mif) initializes the ROM contents of these blocks. The address lines of the ROM are registered on M9K and M144K blocks, but can be unregistered on MLABs.
Page 93: Fifo Mode
Both single and dual-clock (asynchronous) FIFOs are supported. Refer to the Single- and Dual-Clock FIFO Megafunctions User Guide more information on implementing FIFO buffers. Clocking Modes Stratix III TriMatrix memory blocks support the following clocking modes: ■ Independent ■ Input/output ■...
Page 94: Input/Output Clock Mode
Single Clock Mode Stratix III TriMatrix memory blocks can implement single-clock mode for true dual-port, simple dual-port, and single-port memories. In this mode, a single clock, together with a clock enable, is used to control all registers of the memory block.
Page 95: Conflict Resolution
Read During Write You can customize the read-during-write behavior of the Stratix III TriMatrix memory blocks to suit your design needs. Two types of read-during-write operations are available: same port and mixed port.
Page 96 Figure 4–17. Same Port Read-During-Write: Old Data Mode clk_a wrena rdena address_a data_a q_a (asynch) a0(old data) a1(old data) 4–22 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 97 TriMatrix Embedded Memory Blocks in Stratix III Devices Mixed-Port Read-During-Write Mode This mode applies to a RAM in simple or true dual-port mode which has one port reading and the other port writing to the same address location with the same clock.
Page 98: Power-Up Conditions And Memory Initialization
Quartus II Handbook. Power Management Stratix III memory block clock-enables allow you to control clocking of each memory block to reduce AC power consumption. Use the read-enable signal to ensure that read operations only occur when you need them to. If your design does not require read-during-write, you can...
Page 99: Document Revision History
TriMatrix Embedded Memory Blocks in Stratix III Devices Referenced This chapter references the following documents: Documents ■ Logic Array Blocks and Adaptive Logic Modules in Stratix III Devices ■ Quartus II Handbook ■ RAM Megafunction User Guide ■ Single- and Dual-Clock FIFO Megafunctions User Guide Document Table 4–10...
Page 100 Document Revision History 4–26 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 101: Introduction
Overview and dynamic shift functions efficiently. The logical functionality of the Stratix III DSP block is a superset of the previous generation of the DSP block found in Stratix and Stratix II devices. Architectural highlights of the Stratix III DSP block include: ■...
Page 102 Rich and flexible arithmetic rounding and saturation units ■ Efficient barrel shifter support ■ Loopback capability to support adaptive filtering The number of DSP blocks for the Stratix III device family is shown in Table 5–1. Table 5–1. Number of DSP Blocks in Stratix III Devices Four...
Page 103: Simplified Dsp Operation
Figure 5–1. The Stratix III DSP block input data lines of 288 bits is double that of Stratix and Stratix II, but the number of output data lines remains at 144 bits. Figure 5–1. Overview of DSP Block Signals...
Page 104 36 × 36 multipliers, as described in later sections. Each Stratix III DSP block contains four Two-Multiplier Adder units (two Two-Multiplier Adder units per half-block). Therefore, there are eight 18 × 18 multiplier functionalities per DSP block.
Page 105 DSP Blocks in Stratix III Devices Following the Two-Multiplier Adder units are the pipeline registers, the second-stage adders, and an output register stage. You can configure the second-stage adders to provide the following alternative functions per Half-Block: Equation 5–2. Four-Multiplier Adder Equation Z[37..0] = P...
Page 106 Half-DSP Block To support commonly found FIR-like structures efficiently, a major addition to the DSP block in Stratix III is the ability to propagate the result of one Half-Block to the next Half-Block completely within the DSP block without additional soft logic overhead. This is achieved by the inclusion of a dedicated addition unit and routing that adds the 44-bit result of a previous Half-Block with the 44-bit result of the current block.
Page 107 DSP blocks to perform shift operations. The DSP block can dynamically switch between logical shift left/right, arithmetic shift left/right, and rotation operation in one clock cycle. A top-level view of the Stratix III DSP block is shown in Figure 5–5.
Page 108 Simplified DSP Operation Figure 5–5. Stratix III Full DSP Block Summary From Previous Half-Block DSP Input Result Data Top Half-DSP Block Input Result Data Bottom Half-DSP Block To Next Half-Block DSP 5–8 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 109: Operational Modes Overview
DSP Blocks in Stratix III Devices Operational Each Stratix III DSP block can be used in one of five basic operational modes. Table 5–2 shows the five basic operational modes and the number Modes Overview of multipliers that can be implemented within a single DSP block, depending on the mode.
Page 110: Dsp Block Resource Descriptions
Half-Block. This increases DSP block resource efficiency and allows you to implement more multipliers within a Stratix III device. The Quartus II software automatically places multipliers that can share the same DSP block resources within the same block.
Page 111: Input Registers
DSP Blocks in Stratix III Devices Figure 5–6. Half-DSP Block Architecture signa signb zero_loopback accum_sload output_round clock[3..0] zero_chainout output_saturate overflow ena[3..0] rotate chainout_round chainin[ ] alcr[3..0] chainout_saturate shift_right chainout_sat_overflow scanina[ ] dataa_0[ ] loopback datab_0[ ] dataa_1[ ] datab_1[ ]...
Page 112 A feature of the input register bank is to support a tap delay line. Therefore, the top leg of the multiplier input (A) can be driven from general routing or from the cascade chain, as shown in Figure 5–7. 5–12 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 113 DSP Blocks in Stratix III Devices Figure 5–7. Input Register of Half-DSP Block clock[3..0] ena[3..0] signa aclr[3..0] signb scanina[17..0] dataa_0[17..0] loopback datab_0[17..0] +/− dataa_1[17..0] datab_1[17..0] dataa_2[17..0] datab_2[17..0] +/− dataa_3[17..0] datab_3[17..0] Delay Register Altera Corporation 5–13 October 2007 Stratix III Device Handbook, Volume 1...
Page 114 The first multiplier in every half DSP block (top- and bottom-half) in Stratix III devices has a mux for the first multiplier B-input (lower-leg input) register to select between general routing and loopback, as shown Figure 5–6.
Page 115: Multiplier And First-Stage Adder
DSP Blocks in Stratix III Devices Multiplier and First-Stage Adder The multiplier stage natively supports 9 × 9, 12 × 12, 18 × 18, or 36 × 36 multipliers. Other wordlengths are padded up to the nearest appropriate native wordlength; for example, 16 × 16 would be padded up to use 18 ×...
Page 116: Pipeline Register Stage
The output of the second-stage adder has the option to go into the round and saturation logic unit or the output register. You cannot use the second-stage adder independently from the multiplier and first-stage adder. 5–16 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 117: Round And Saturation Stage
44-bit registers that can also be combined to form larger 72-bit banks to support 36 × 36 output results. The outputs of the different stages in the Stratix III devices are routed to the output registers through an output selection unit. Depending on the...
Page 118 This is done by the Quartus II software by zero-padding the LSBs. Figures 5–8, 5–9, and 5–10 show the DSP block in the independent multiplier operation mode. 5–18 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 119 DSP Blocks in Stratix III Devices Figure 5–8. 18-Bit Independent Multiplier Mode Shown for Half-DSP Block signa clock[3..0] signb ena[3..0] overflow output_round aclr[3..0] output_saturate dataa_0[17..0] result_0[ ] datab_0[17..0] dataa_1[17..0] result_1[ ] datab_1[17..0] Half-DSP Block Altera Corporation 5–19 October 2007 Stratix III Device Handbook, Volume 1...
Page 120 Figure 5–9. 12-Bit Independent Multiplier Mode Shown for Half-DSP Block clock[3..0] ena[3..0] signa signb aclr[3..0] dataa_0[11..0] result_0[ ] datab_0[11..0] dataa_1[11..0] result_1[ ] datab_1[11..0] dataa_2[11..0] result_2[ ] datab_2[11..0] Half-DSP Block 5–20 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 121 DSP Blocks in Stratix III Devices Figure 5–10. 9-Bit Independent Multiplier Mode Shown for Half-Block clock[3..0] ena[3..0] signa signb aclr[3..0] dataa_0[8..0] result_0[ ] datab_0[8..0] dataa_1[8..0] result_1[ ] datab_1[8..0] dataa_2[8..0] result_2[ ] datab_2[8..0] dataa_3[8..0] result_3[ ] datab_3[8..0] Half-DSP Block The multiplier operands can accept signed integers, unsigned integers, or a combination of both.
Page 122: 36-Bit Multiplier
This simplification fits conveniently into one half-DSP block, and is implemented in the DSP block automatically by selecting the 36 × 36 mode. Stratix III devices can have up to two 36-bit multipliers per DSP block (one 36-bit multiplier per half DSP block). The 36-bit multiplier...
Page 123: Double Multiplier
IEEE double precision floating point multiplication. A 54 × 54 bit multiplier can be built using basic 18 × 18 multipliers, shifters and adders. In order to efficiently utilize the Stratix III DSP block's built Altera Corporation 5–23...
Page 124 Figure 5–12 Figure 5–13. Figure 5–12. Double Mode Shown for Half-DSP Block clock[3..0] ena[3..0] signa signb aclr[3..0] dataa_0[35..18] datab_0[35..18] dataa_0[17..0] datab_0[35..18] result[ ] dataa_0[35..18] datab_0[17..0] dataa_0[17..0] datab_0[17..0] Half-DSP Block 5–24 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 125: Two-Multiplier Adder Sum Mode
DSP Blocks in Stratix III Devices Figure 5–13. Unsigned 54 × 54 Multiplier clock[3..0] signa ena[3..0] signb aclr[3..0] Two Multiplier "0" Adder Mode "0" dataa[53..36] datab[53..36] Double Mode dataa[35..18] datab[53..36] dataa[17..0] datab[53..36] result[ ] dataa[53..36] datab[35..18] dataa[53..36] datab[17..0] 36 x 36 Mode dataa[35..18]...
Page 126 The two-multiplier adder mode supports the round and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. 5–26 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 127 DSP Blocks in Stratix III Devices Figure 5–14. Two-Multiplier Adder Mode Shown for Half-DSP Block signa clock[3..0] signb ena[3..0] output_round aclr[3..0] output_saturate overflow dataa_0[17..0] datab_0[17..0] result[ ] dataa_1[17..0] datab_1[17..0] Half-DSP Block Altera Corporation 5–27 October 2007 Stratix III Device Handbook, Volume 1...
Page 128 Operational Mode Descriptions Figure 5–15. Loopback Mode for Half-DSP Block signa clock[3..0] signb ena[3..0] output_round output_saturate aclr[3..0] zero_loopback overflow dataa_0[17..0] loopback datab_0[17..0] result[ ] dataa_1[17..0] datab_1[17..0] Half-DSP Block 5–28 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 129: 18 × 18 Complex Multiply
DSP Blocks in Stratix III Devices 18 × 18 Complex Multiply You can configure the DSP block when used in Two-Multiplier Adder mode to implement complex multipliers using the two-multiplier adder mode. A single half DSP block can implement one 18-bit complex multiplier.
Page 130 Operational Mode Descriptions Figure 5–16. Complex Multiplier Using Two-Multiplier Adder Mode clock[3..0] ena[3..0] signa signb aclr[3..0] C) − (B − (Real Part) D) − (B (Imaginary Part) Half-DSP Block 5–30 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 131: Four-Multiplier Adder
DSP Blocks in Stratix III Devices Four-Multiplier Adder In the four-multiplier adder configuration shown in Figure 5–17, the DSP block can implement two four-multiplier adders (one four-multiplier adder per half DSP block). These modes are useful for implementing one-dimensional and two-dimensional filtering applications. The four-multiplier adder is performed in two addition stages.
Page 132 The four-multiplier adder mode supports the round and saturation logic unit. You can use the pipeline registers and output registers within the DSP block to pipeline the multiplier-adder result, increasing the performance of the DSP block. 5–32 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 133: Multiply Accumulate Mode
DSP Blocks in Stratix III Devices Multiply Accumulate Mode In multiply accumulate mode, the second-stage adder is configured as a 44-bit accumulator or subtractor. The output of the DSP block is looped back to the second-stage adder and added or subtracted with the two...
Page 134: Shift Modes
32-bit rotator or Barrel shifter, ROT[N] You can switch the shift mode between these modes using the dynamic rotate and shift control signals. The shift mode in a Stratix III device can be easily used by the soft ® embedded processor such as Nios II to perform the dynamic shift and rotate operation.
Page 135 DSP Blocks in Stratix III Devices Two control signals rotate and shift_right together with the signa and signb signals, determining the shifting operation. Examples of shift operations are shown in Table 5–5. Figure 5–19. Shift Operation Mode Shown for Half-DSP Block signa clock[3..0]...
Page 136: Rounding And Saturation Mode
Round and saturation functions are often required in DSP arithmetic. Rounding is used to limit bit growth and its side effects and saturation is used to reduce overflow and underflow side effects. Two rounding modes are supported in Stratix III devices: ■ Round-to-nearest-integer mode ■...
Page 137 110110 1110 ⇒ ⇒ 110010 1101 110010 1100 Two saturation modes are supported in Stratix III: ■ Asymmetric saturation mode ■ Symmetric saturation mode You must select one of the two options at compile time. Altera Corporation 5–37 October 2007...
Page 138 ADA38D2210h 800000001h 800000000h Stratix III devices have up to 16 configurable bit positions out of the 44-bit bus ([43:0]) for the round and saturate logic unit providing higher flexibility. You must select the 16 configurable bit positions at compile time. These 16-bit positions are located at bits [21:6] for rounding and...
Page 139: Dsp Block Control Signals
(A × B)]] DSP Block Control Signals The Stratix III DSP block is configured using a set of static and dynamic signals. The DSP block dynamic signals are user configurable and can be set to toggled or not at run time. This list of dynamic signals is shown in Table 5–9...
Page 140 Input and Pipeline Register enable signals ena0 ena1 ena2 ena3 DSP block-wide asynchronous clear signals (active low). aclr0 aclr1 aclr2 aclr3 Total Count per Full Block 5–40 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 141: Application Examples
Down Converters (DDC). FIR filters can be implemented in many forms, the most simple being the tap-delay line approach. Stratix III DSP block can implement various types of FIR filters very efficiently. To form the tap-delay line, the input register stage of the DSP block has the ability to cascade the input in a chained fashion in 18-bit wide format.
Page 142 For a complete FIR, the results per individual Four-Multiplier Adder can be combined in either a tree or chained cascade manner. Using external logic and adders, you can very easily implement a tree summation, as shown in Figure 5–21. 5–42 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 143 DSP Blocks in Stratix III Devices Figure 5–21. FIR Filter Using Tap-Delay Line Input and Tree Summation of Final Result signa clock[3..0] signb ena[3..0] output_round aclr[3..0] output_saturate overflow dataa_0[ ] datab_0[17..0] datab_1[17..0] Final Summation Final Adder in Result Soft Logic datab_2[17..0]...
Page 144 FPGA routing. The chainout result can be zeroed out by applying logic 1 on the dynamic zerochainout signal. The zerochainout signal can also be registered. 5–44 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 145 DSP Blocks in Stratix III Devices Figure 5–22. FIR Filter using Tap-Delay Line Input and Chained Cascade Summation of Final Result signa clock[3..0] signb ena[3..0] chainout_round aclr[3..0] chainout_saturate zero_chainout chainout_sat_overflow dataa_0[ ] datab_0[17..0] Zero datab_1[17..0] datab_2[17..0] datab_3[17..0] Half-DSP Block Delay Register datab_4[17..0]...
Page 146 Four-Multiplier Mode with independent inputs. Figure 5–23 shows an example for chained cascaded summation. In most cases, only the final stage FIR tap with the rounding and saturation unit is deployed. 5–46 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 147 DSP Blocks in Stratix III Devices Figure 5–23. Semi-Parallel FIR Structure Using Chained Cascaded Summation signa clock[3..0] signb ena[3..0] chainout_round aclr[3..0] chainout_saturate zero_chainout chainout_sat_overflow dataa_0[ ] datab_0[ ] Zero dataa_1[ ] datab_1[ ] dataa_2[ ] datab_2[ ] dataa_3[ ] datab_3[ ]...
Page 148: Fft Example
A fundamental building block of the FFT is the FFT butterfly. FFTs are most efficient when operating on complex samples. You can use the Stratix III DSP block to form the core of a complex FFT butterfly very efficiently. Figure 5–24, a radix-4 butterfly is shown.
Page 149: Software Support
1 of the Quartus II Development Software Handbook. Conclusion The Stratix III device DSP blocks are optimized to support DSP applications requiring high data throughput, such as FIR filters, IIR filters, FFT functions, and encoders. These DSP blocks are flexible and can be configured to implement one of several operational modes to suit a particular application.
Page 150: Document Revision History
Table 5–5 Table 5–9. ● Deleted Table 5-10. ● Added sections “Double Multiplier” “Referenced Documents”. ● Clarification added for “Shift Modes” on page 5–34. November 2006 v1.0 Initial Release. — 5–50 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 151: Chapter 6. Clock Networks And Plls In Stratix Iii Devices
220 unique in Stratix III clock domains (16 GCLK + 88 RCLK + 116 PCLK) within the Stratix III device and allows up to 67 unique GCLK, RCLK, and PCLK clock sources Devices (16 GCLK + 22 RCLK + 29 PCLK) per device quadrant.
Page 152: Clock Networks In Stratix Iii Devices
Stratix III devices have up to 32 dedicated single-ended clock pins or 16 dedicated differential clock pins (CLK[0:15]p and CLK[0:15]n) that can drive either the GCLK or RCLK networks. These clock pins are arranged on the four sides of the Stratix III device, as shown in Figures 6–1 to 6–4.
Page 153 The regional clock (RCLK) networks only pertain to the quadrant they drive into. The RCLK networks provide the lowest clock delay and skew for logic contained within a single device quadrant. Stratix III device I/O elements and internal logic within a given quadrant can also drive RCLKs to create internally generated regional clocks and other high fan-out control signals;...
Page 154 Clock Networks in Stratix III Devices Figure 6–2. Regional Clock Networks (EP3SL50, EP3SL70, and EP3SE50 Devices) CLK[12..15] RCLK[54..63] RCLK[44..53] RCLK[38..43] RCLK[0..5] CLK[0..3] CLK[8..11] RCLK[6..11] RCLK[32..37] RCLK[12..21] RCLK[22..31] CLK[4..7] Figure 6–3. Regional Clock Networks (EP3SL110, EP3SL150, EP3SE80, and EP3SE110 Devices) CLK[12..15] RCLK[54..63] RCLK[44..53]...
Page 155 Stratix III device. Clocking Regions Stratix III devices provide up to 104 distinct clock domains (16 GCLKs + 88 RCLKs) in the entire device. You can utilize these clock resources to form the following four different types of clock region: ■...
Page 156 Corner PLL outputs only span one quadrant and hence cannot generate a dual-regional clock network. Figure 6–5 shows the dual-regional clock region. Figure 6–5. Stratix III Dual-Regional Clock Region Clock pins or PLL outputs can drive half of the device to create side-wide clocking regions for improved interface timing.
Page 157 Clock Networks and PLLs in Stratix III Devices The sub-regional clock scheme allows the formation of independent sub-regional clock regions for optimal and efficient use of global and regional clock resources. You can partition the device into a maximum of 16 sub-regional clock regions.
Page 158 Clock Networks in Stratix III Devices Figure 6–8. Twelve Independent Sub-Regional + One Regional Clock Region Clock Network Sources In Stratix III devices, clock input pins, PLL outputs, and internal logic can drive the global and regional clock networks. See Tables 6–2 6–6...
Page 159 Clock Networks and PLLs in Stratix III Devices Table 6–2 shows the connection between the dedicated clock input pins and GCLKs. Table 6–2. Clock Input Pin Connectivity to Global Clock Networks CLK (p/n Pins) Clock Resources — — — —...
Page 160 Clock Networks in Stratix III Devices Table 6–3. Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 1) (Part 2 of 2) CLK (p/n Pins) Clock Resource — — — — — — — — — — — — —...
Page 161 Clock Networks and PLLs in Stratix III Devices Table 6–4. Clock Input Pin Connectivity to Regional Clock Networks (Quadrant 2) (Part 2 of 2) CLK (p/n Pins) Clock Resource — — — — — — — — — — —...
Page 162: Clock Input Connections To Plls
Clock Input Connections to PLLs Dedicated clock input pin connectivity to Stratix III device PLLs is shown Table 6–7. Table 6–7. Stratix III Device PLLs and PLL Clock Pin Drivers (Part 1 of 2) Dedicated Clock PLL Number Input Pin (CLKp/n pins) —...
Page 163: Clock Output Connections
Clock Networks and PLLs in Stratix III Devices Table 6–7. Stratix III Device PLLs and PLL Clock Pin Drivers (Part 2 of 2) Dedicated Clock PLL Number Input Pin (CLKp/n pins) — — — — — — — — CLK3 —...
Page 164: Clock Source Control For Plls
Clock Networks in Stratix III Devices Table 6–8. Stratix III PLL Connectivity to GCLKs (Part 2 of 2) PLL Number Clock Network — — — — — — — — — — GCLK7 — — — — — — —...
Page 165 Clock Networks and PLLs in Stratix III Devices The multiplexer select lines are set in the configuration file (SRAM object file [.SOF] or programmer object file [.POF]) only. Once programmed, this block cannot be changed without loading a new configuration file (.SOF or .POF).
Page 166: Clock Control Block
Clock Networks in Stratix III Devices Figure 6–10. Clock Input Multiplexer Logic for L1, L4, R1, and R4 PLLs PLL_<L1/L4/R1/R4>_CLK (1) inclk0 GCLK/RCLK (2) CLK[0..3] or CLK[8..11] (3) inclk1 Notes to Figure 6–10: Dedicated clock input pins to PLLs - L1, L4, R1 and R4, respectively. For example, PLL_L1_CLK is the dedicated clock input for PLL_L1.
Page 167 Clock Networks and PLLs in Stratix III Devices Figure 6–11. Stratix III Global Clock Control Block CLKp Pins PLL Counter CLKn Outputs Internal CLKSELECT[1..0] Logic Static Clock This multiplexer Select (2) supports user-controllable dynamic switching Enable/ Disable Internal Logic GCLK...
Page 168 (.sof or .pof) generated by the Quartus II software. The Stratix III clock networks can be powered down by both static and dynamic approaches. When a clock net is powered down, all the logic fed by the clock net is in an off-state, thereby reducing the overall power consumption of the device.
Page 169 PLL outputs feed the inclock[2..3] ports. You can choose from among these inputs using the CLKSELECT[1..0] signal. Figure 6–13. Stratix III External PLL Output Clock Control Block PLL Counter Outputs 7 or 10...
Page 170: Clock Enable Signals
The select line is statically controlled by a bit setting in the configuration file (.SOF or .POF). In Stratix III devices, the clkena signals are supported at the clock network level instead of at the PLL output counter level. This allows you to gate off the clock even when a PLL is not being used.
Page 171 Clock Networks and PLLs in Stratix III Devices Figure 6–15. clkena Signals output of clock select mux clkena output of AND gate with R2 bypassed output of AND gate with R2 not bypassed Note to Figure 6–15: You can use the clkena signals to enable or disable the global and regional networks or the PLL_<#>_CLKOUT pins.
Page 172 PLLs T2, B2, L3, and R3 are not available in the F780 package. PLLs L1, L4, R1, and R4 are not available in the F1152 package. All Stratix III PLLs have the same core analog structure with only minor differences in features that are supported.
Page 173 The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Stratix III device can shift all output frequencies in increments of at least 45 degrees. Smaller degree increments are possible depending on the frequency and divide parameters.
Page 174: Stratix Iii Pll Hardware Overview
There are a number of components that comprise a PLL to achieve this phase alignment. Stratix III PLLs align the rising edge of the input reference clock to a feedback clock using the phase-frequency detector (PFD). The falling edges are determined by the duty-cycle specifications. The PFD produces an up or down signal that determines whether the voltage-controlled oscillator (VCO) needs to operate at a higher or lower frequency.
Page 175 Clock Networks and PLLs in Stratix III Devices charge pump. If the charge pump receives an up signal, current is driven into the loop filter. Conversely, if the charge pump receives a down signal, current is drawn from the loop filter.
Page 176 The number of post scale counters is 7 for Left/Right PLLs and 10 for Top/Bottom PLLs. This is the VCO post-scale counter The FBOUT port is fed by the M counter in Stratix III PLLs. The global (GCLK) or regional (RCLK) clock input can be driven by an output from another PLL, a pin-driven global or regional clock, or through a clock control block provided the clock control block is fed by an output from another PLL or a pin driven dedicated global or regional clock.
Page 177 Clock Networks and PLLs in Stratix III Devices Figure 6–18. External Clock Outputs for Top/Bottom PLLs Internal Logic Top/Bottom PLLs m(fbout) clkena4 (3) clkena0 (3) clkena2 (3) clkena3 (3) clkena5 (3) clkena1 (3) PLL_<#>_CLKOUT3 PLL_<#>_FBp/CLKOUT1 (1), (2) PLL_<#>_CLKOUT0p (1), (2) (1), (2) PLL_<#>_CLKOUT4...
Page 178: Stratix Iii Pll Software Overview
Stratix III Device Handbook to determine which I/O standards are supported by the PLL clock input and output pins. Stratix III PLLs can also drive out to any regular I/O pin through the global or regional clock network. You can also use the external clock output pins as user I/O pins if external PLL clocking is not needed.
Page 179 You can drive to global or regional clock networks or dedicated external clock output pins. n = 6 for Left/Right PLLs and n = 9 for Top/Bottom PLLs. Table 6–12 shows the PLL input signals for Stratix III devices. Table 6–12. PLL Input Signals (Part 1 of 2) Port...
Page 180 Logic array or I/O pin PLL reconfiguration circuit phaseupdown direction; 1 = UP; 0 = DOWN Logic high enables dynamic phase Logic array or I/O pin PLL reconfiguration circuit phasestep shifting 6–30 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 181 Clock Networks and PLLs in Stratix III Devices Table 6–13 shows the PLL output signals for Stratix III devices. Table 6–13. PLL Output Signals Port Description Source Destination PLL output counters driving PLL counter Internal or external for Top/Bottom clk[9..0]...
Page 182: Clock Feedback Modes
PLLs in Stratix III Devices Clock Feedback Modes Stratix III PLLs support up to six different clock feedback modes. Each mode allows clock multiplication and division, phase shifting, and programmable duty cycle. Table 6–14 shows the clock feedback modes supported by Stratix III device PLLs.
Page 183 Clock Networks and PLLs in Stratix III Devices Figure 6–21. Phase Relationship Between Clock and Data in Source- Synchronous and LVDS Modes Data pin reference clock at input pin Data at register Clock at register The source-synchronous mode compensates for the delay of the clock network used plus any difference in the delay between these two paths: ■...
Page 184 In normal mode, the delay introduced by the GCLK or RCLK network is fully compensated. Figure 6–23 shows an example waveform of the PLL clocks' phase relationship in this mode. 6–34 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 185 When using this mode, you must use the same I/O standard on the input clocks and output clocks in order to guarantee clock alignment at the input and output pins. This mode is supported on all Stratix III PLLs. When using Stratix III PLLs in ZDB mode, along with single-ended I/O...
Page 186 Figure 6–27. Aligning these clocks allows you to remove clock delay and skew between devices. This mode is supported on all Stratix III PLLs. 6–36 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 187 Left/Right PLLs support EFB mode when using single-ended I/O standards only. Figure 6–26 shows EFB mode implementation in Stratix III devices. Figure 6–26. External Feedback Mode in Stratix III Devices inclk ÷n PLL_<#>_CLKOUT# ÷C0 CP/LF PLL_<#>_CLKOUT#...
Page 188: Clock Multiplication And Division
The PLL clock outputs can lead or lag the fbin clock input. Clock Multiplication and Division Each Stratix III PLL provides clock synthesis for PLL output ports using m/(n* post-scale counter) scaling factors. The input clock is divided by a pre-scale factor, n, and is then multiplied by the m feedback factor.
Page 189: Post-Scale Counter Cascading
Post-Scale Counter Cascading The Stratix III PLLs support post-scale counter cascading to create counters larger than 512. This is automatically implemented in the Quartus II software by feeding the output of one C counter into the input...
Page 190: Programmable Duty Cycle
PLL out-of-lock. The VCO is then set back to its nominal setting. When areset is driven low again, the PLL will resynchronize to its input as it re-locks. 6–40 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 191: Clock Switchover
The following clock switchover modes are supported in Stratix III PLLs: ■ Automatic switchover: The clock sense circuit monitors the current reference clock and if it stops toggling, automatically switches to the other clock inclk0 or inclk1.
Page 192 Automatic switchover with manual override: This mode combines Modes 1 and 2. When the clkswitch signal goes high, it overrides automatic clock switchover mode. Stratix III device PLLs support a fully configurable clock switchover capability. Figure 6–29 shows the block diagram of the switchover circuit built into the PLL.
Page 193 Clock Networks and PLLs in Stratix III Devices generates a signal (clksw) that controls the multiplexer select input as shown in Figure 6–29. In this case, inclk1 becomes the reference clock for the PLL. When using the automatic switchover mode, you can switch back and forth between inclk0 and inclk1 clocks any number of times, when one of the two clocks fails and the other clock is available.
Page 194 On the falling edge of inclk0, the counter's reference clock, muxout, is gated off to prevent any clock glitching. On the falling edge of inclk1, the reference clock 6–44 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 195 Clock Networks and PLLs in Stratix III Devices multiplexer switches from inclk0 to inclk1 as the PLL reference, and the activeclock signal changes to indicate which clock is currently feeding the PLL. Figure 6–31. Clock Switchover Using the clkswitch (Manual) Control...
Page 196 PLLs in Stratix III Devices Figure 6–32. Manual Clock Switchover Circuitry in Stratix III PLLs clkswitch Clock Switch Control Logic inclk0 n Counter inclk1 muxout refclk fbclk For more information on PLL software support in the Quartus II software, refer to the altpll Megafunction User Guide.
Page 197: Programmable Bandwidth
Once the lock indication is stable, the system can re-enable the output clock(s). Programmable Bandwidth Stratix III PLLs provide advanced control of the PLL bandwidth using the PLL loop's programmable characteristics, including loop filter and charge pump. Background PLL bandwidth is the measure of the PLL's ability to track the input clock and its associated jitter.
Page 198 PLL output. A low-bandwidth PLL filters out reference clock jitter but increases lock time. Stratix III PLLs allow you to control the bandwidth over a finite range to customize the PLL characteristics for a particular application.
Page 199 PLL's bandwidth. Most loop filters consist of passive components such as resistors and capacitors that take up unnecessary board space and increase cost. With Stratix III PLLs, all the components are contained within the device to increase performance and decrease cost.
Page 200: Phase-Shift Implementation
You can phase-shift the output clocks from the Stratix III PLLs in either of these two resolutions: ■...
Page 201 You can use the coarse- and fine-phase shifts to implement clock delays in Stratix III devices. Stratix III devices support dynamic phase-shifting of VCO phase taps only. The phase shift is reconfigurable any number of times, and each phase shift takes about one SCANCLK cycle, allowing you to implement large phase shifts quickly.
Page 202: Pll Reconfiguration
Phase-locked loops (PLLs) use several divide counters and different voltage-controlled oscillator (VCO) phase taps to perform frequency synthesis and phase shifts. In Stratix III PLLs, you can reconfigure both the counter settings and phase-shift the PLL output clock in real time.
Page 203 Clock Networks and PLLs in Stratix III Devices Figure 6–37. PLL Reconfiguration Scan Chain from m counter LF/K/CP (3) from n counter scandata scanclkena configupdate /Ci (2) inclk /Ci-1 scandataout scandone scanclk Notes to Figure 6–37: The Stratix III Left/Right PLLs support C0 - C6 counters.
Page 204 Reset the PLL using the areset signal if you make any changes to the M or N counters or the Icp, R, or C settings. Steps 1-5 can be repeated to reconfigure the PLL any number of times. 6–54 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 205 Clock Networks and PLLs in Stratix III Devices Figure 6–38 shows a functional simulation of the PLL reconfiguration feature. Figure 6–38. PLL Reconfiguration Waveform SCANDATA SCANCLK SCANCLKENA Dn_old D0_old SCANDATAOUT CONFIGUPDATE SCANDONE ARESET When you reconfigure the counter clock frequency, you cannot reconfigure the corresponding counter phase shift settings using the same interface.
Page 206 Scan Chain Description The length of the scan chain varies for different Stratix III PLLs. The Top/Bottom PLLs have 10 post-scale counters and a 234-bit scan chain, while the Left/Right PLLs have 7 post-scale counters and a 180-bit scan chain.
Page 207 Clock Networks and PLLs in Stratix III Devices Table 6–16. Top/Bottom PLL Reprogramming Bits (Part 2 of 2) Number of Bits Block Name Total Counter Other Charge Pump Current VCO Post-Scale divider (K) Loop Filter Capacitor Loop Filter Resistor Unused CP/LF Total number of —...
Page 208 Left/Right PLLs have the same scan-chain order. The post-scale counters end at C6. Figure 6–40 shows the scan-chain bit-order sequence for post-scale counters in all Stratix III PLLs. Figure 6–40. Scan-Chain Bit-Order Sequence for Post-Scale Counters in Stratix III PLLs DATAIN rbypass rselodd DATAOUT 6–58...
Page 209 Clock Networks and PLLs in Stratix III Devices Charge Pump and Loop Filter You can reconfigure the charge-pump and loop-filter settings to update the PLL bandwidth in real time. Tables 6–17, 6–18, and 6–19 show the possible settings for charge pump current (I ), loop-filter resistor (R), and capacitor (C) values for Stratix III PLLs.
Page 210 Bypassing a PLL counter results in a multiply (m counter) or a divide (n and C0 to C9 counters) factor of one. Table 6–20 shows the settings for bypassing the counters in Stratix III PLLs. Table 6–20. PLL Counter Settings PLL Scan Chain Bits [0..10] Settings...
Page 211 Clock Networks and PLLs in Stratix III Devices the output clock phase-shift in real time. This adjustment is achieved by incrementing or decrementing the VCO phase-tap selection to a given C counter or to the M counter. The phase is shifted by 1/8 of the VCO frequency at a time.
Page 212 Repeat steps 1-5 as many times as required to perform multiple phase-shifts. All signals are synchronous to scanclk. They are latched on scanclk edges and must meet t requirements with respect to scanclk edges. 6–62 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 213 Clock Networks and PLLs in Stratix III Devices Figure 6–41. Dynamic Phase Shifting Waveform SCANCLK PHASESTEP PHASEUPDOWN PHASECOUNTERSELECT PHASEDONE PHASEDONE goes low synchronous with SCANCLK Dynamic phase-shifting can be repeated indefinitely. All signals are synchronous to scanclk and must meet t requirements with respect to scanclk edges.
Page 214: Spread-Spectrum Tracking
However, the device cannot automatically detect that the input is a spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the input of PLL. Stratix III PLLs can track a spread-spectrum input clock as long as it is within the input-jitter tolerance specifications.
Page 215: Document Revision History
Clock Networks and PLLs in Stratix III Devices Document Table 6–23 shows the revision history for this document. Revision History Table 6–23. Document Revision History Date and Document Changes Made Summary of Changes Version November 2007 — ● Updated “pfdena” on page 6–40.
Page 216 Document Revision History 6–66 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 217: Section Ii. I/O Interfaces
DPA. This section includes the following chapters: ■ Chapter 7, Stratix III Device I/O Features ■ Chapter 8, External Memory Interfaces in Stratix III Devices ■ Chapter 9, High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Revision History Refer to each chapter for its own specific revision history.
Page 218 I/O Interfaces Stratix III Device Handbook, Volume 1 Section II–2 Altera Corporation Preliminary...
Page 219: Chapter 7. Stratix Iii Device I/O Features
Programmable pre-emphasis ■ Programmable differential output voltage (VOD) Stratix III Stratix III devices support a wide range of industry I/O standards. Table 7–1 shows the I/O standards Stratix III devices support as well as I/O Standards the typical applications. Stratix III devices support a V...
Page 220: Stratix Iii I/O Standards Support
Stratix III I/O Standards Support Table 7–1. Stratix III I/O Standard Applications (Part 1 of 2) I/O Standard Application 3.3-V LVTTL/LVCMOS General purpose 3.0-V LVTTL/LVCMOS General purpose 2.5-V LVTTL/LVCMOS General purpose 1.8-V LVTTL/LVCMOS General purpose 1.5-V LVTTL/LVCMOS General purpose 1.2-V LVTTL/LVCMOS General purpose 3.0-V PCI...
Page 221: I/O Standards And Voltage Levels
Stratix III Device I/O Features Table 7–1. Stratix III I/O Standard Applications (Part 2 of 2) I/O Standard Application LVDS High-speed communications RSDS Flat panel display mini-LVDS Flat panel display LVPECL Video graphics and clock distribution I/O Standards and Voltage Levels...
Page 222 Stratix III I/O Standards Support Table 7–2. Stratix III I/O Standards and Voltage Levels Notes (1), (Part 2 of 3) CCIO CCPD Input Operation Output Operation I/O Standard Standard (Pre- (Input (Board Support Driver Termination Top and Left and Top and...
Page 223: Stratix Iii I/O Banks
Refer to the DC and Switching Characteristics of Stratix III Devices chapter in volume 2 of the Stratix III Device Handbook for detailed electrical characteristics of each I/O standard. Stratix III I/O Stratix III devices contain up to 24 I/O banks, as shown in Figure 7–1.
Page 224 Refer to the High-Speed Differential I/O Interface with DPA in Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook for the number of channels available for the LVDS I/O standard. 7–6 Altera Corporation...
Page 225 Stratix III Device I/O Features Figure 7–1. Stratix III I/O banks Notes (1), (2), (3), (4), (5), (6), (7), (8), Bank 8A Bank 8B Bank 7B Bank 8C Bank 7C Bank 7A I/O banks 8A, 8B, and 8C support all...
Page 226: Modular I/O Banks
I/O pins available in each I/O bank. In Stratix III devices, the maximum number of I/O banks per side is four or six, depending on the device density. When migrating between devices with a different number of I/O banks per side, it is the middle or “B”...
Page 227 CLK10p, and CLK10n) that can be used for data inputs. Figure 7–3 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical representation only. Altera Corporation 7–9 November 2007 Stratix III Device Handbook, Volume 1...
Page 228 CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) that can be used for data inputs. Figure 7–4 is a top view of the silicon die that corresponds to a reverse view for flip- chip packages. It is a graphical representation only. 7–10 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 229 CLK10p, and CLK10n) that can be used for data inputs. Figure 7–5 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical representation only. Altera Corporation 7–11 November 2007 Stratix III Device Handbook, Volume 1...
Page 230 Figure 7–6 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical representation only. 7–12 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 231 Figure 7–7 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical representation only. Altera Corporation 7–13 November 2007 Stratix III Device Handbook, Volume 1...
Page 232: Stratix Iii I/O Structure
DDR transfer. The IOEs are located in I/O blocks around the periphery of the Stratix III device. There are up to four IOEs per row I/O block and four IOEs per column I/O block. The row IOEs drive row, column, or direct link interconnects.
Page 233: 3.3-V I/O Interface
1 of the Stratix III Device Handbook. 3.3-V I/O Interface Stratix III I/O buffers are fully compatible with 3.3-V I/O standards and you can use them as transmitters or receivers in your system. The output high voltage (V...
Page 234 (OCT) for all LVTTL/LVCMOS I/O standards in all I/O banks. When using the Stratix III device as a receiver, a technique you can use to limit the overshoot, though not required, is using a clamping diode (on-chip or off-chip). Stratix III devices provide an optional on-chip PCI-clamp diode for column I/O pins.
Page 235: External Memory Interfaces
Stratix III Device I/O Features External Memory Interfaces In addition to the I/O registers in each IOE, Stratix III devices also have dedicated registers and phase-shift circuitry on all I/O banks for interfacing with external memory interfaces. Table 7–3 lists the memory interfaces and the corresponding I/O standards supported by Stratix III devices.
Page 236: Programmable Current Strength
1 of the Stratix III Device Handbook. Programmable Current Strength The output buffer for each Stratix III device I/O pin has a programmable current-strength control for certain I/O standards. You can use programmable current strength to mitigate the effects of high signal attenuation due to a long transmission line or a legacy backplane.
Page 237: Programmable Slew Rate Control
Programmable Slew Rate Control The output buffer for each Stratix III device regular- and dual-function I/O pin has a programmable output slew-rate control that you can configure for low-noise or high-speed performance. A faster slew rate provides high-speed transitions for high-performance systems.
Page 238: Programmable Delay
Refer to the DC and Switching Characteristics of Stratix III Devices chapter in volume 2 of the Stratix III Device Handbook for the programmable IOE delay specifications. Programmable Output Buffer Delay Stratix III devices support delay chains built inside the single-ended...
Page 239: Bus Hold
Stratix III Device I/O Features Bus Hold Each Stratix III device I/O pin provides an optional bus-hold feature. The bus-hold circuitry can weakly hold the signal on an I/O pin at its last-driven state. Because the bus-hold feature holds the last-driven state...
Page 240: Programmable Pre-Emphasis
The Stratix III architecture supports the MultiVolt I/O interface feature that allows Stratix III devices in all packages to interface with systems of different supply voltages. The VCCIO pins can be connected to a 1.2-, 1.5-, 1.8-, 2.5-, 3.0-V, or 3.3-V power supply, depending on the output requirements.
Page 241: Oct Support
V minimum voltage specifications. Altera recommends that you use an external clamp diode on the column I/O pins when the input signal is 3.0 V or 3.3 V. OCT Support Stratix III devices feature dynamic series and parallel on-chip termination to provide I/O impedance matching and termination capabilities.
Page 242 GND through an external 50-Ω ±1% resistor. On-Chip Series (R ) Termination without Calibration Stratix III devices support driver-impedance matching to provide the I/O driver with controlled output impedance that closely matches the impedance of the transmission line. As a result, you can significantly reduce reflections.
Page 243 50-Ω pull-up to V On-Chip Series Termination with Calibration Stratix III devices support on-chip series termination with calibration in all banks. The on-chip series termination calibration circuit compares the total impedance of the I/O buffer to the external 25-Ω ±1% or 50-Ω ±1%...
Page 244 SSTL-15 Class I Ω SSTL-15 Class II Ω HSTL-18 Class I Ω HSTL-18 Class II Ω HSTL-15 Class I Ω HSTL-15 Class II Ω HSTL-12 Class I Ω HSTL-12 Class II 7–26 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 245 Stratix III Device I/O Features On-Chip Parallel Termination with Calibration Stratix III devices support on-chip parallel termination with calibration in all banks. On-chip parallel termination with calibration is only supported for input or bi-directional pin configurations. Output pin configurations do not support on-chip parallel termination with calibration.
Page 246 Ω Differential HSTL-12 Class I, II Dynamic On-Chip Termination Stratix III devices support on-off dynamic series and parallel termination for a bi-directional I/O in all I/O banks. Figure 7–12 shows the termination schemes supported in the Stratix III device. Dynamic parallel termination is enabled only when the bi-directional I/O acts as a receiver and is disabled when it acts as a driver.
Page 247: Lvds Input On-Chip Termination (R D )
I/O banks; column I/O banks do not support OCT R The dedicated clock input pairs CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n on the row I/O banks of the Stratix III devices do not support R termination. Altera Corporation 7–29...
Page 248: Oct Calibration
(R ) on all I/O pins. You can calibrate the Stratix III I/O bank with any of eight OCT calibration blocks in EP3SL50, EP3SL70, EP3SL110, EP3SL150, EP3SE50, EP3SE80, and EP3SE110 devices and ten OCT calibration blocks in EP3SL200, EP3SE260 and EP3SL340 devices.
Page 249 Note to Figure 7–15: Figure 7–15 is a top view of the silicon die that corresponds to a reverse view for flip-chip packages. It is a graphical representation only. Altera Corporation 7–31 November 2007 Stratix III Device Handbook, Volume 1...
Page 250 Since 3B, 4C, 6C, and 7B have the same as bank 7A, you can calibrate all four I/O banks (3B, 4C, 6C, CCIO and 7B) with the OCT calibration block located in bank 7A. You can 7–32 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 251: Oct Calibration Block Modes Of Operation
It is a graphical representation only. OCT Calibration Block Modes of Operation Stratix III devices support calibration R and R OCT in all I/O banks. The calibration can occur in either power-up mode or user mode.
Page 252 The OCTUSRCLK clock frequency must be 20 MHz or less. You must generate all user signals on the rising edge of OCTUSRCLK. 7–34 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 253 ENASER[N] must be asserted for exactly 28 OCTUSRCLK cycles. Between two consecutive asserted ENASER signals there must be at least 1 OCTUSRCLK cycle gap. Refer to Figure 7–19 for these requirements. Altera Corporation 7–35 November 2007 Stratix III Device Handbook, Volume 1...
Page 254 7–20, when nCLRUSR is set to 0 for the second time to initialize OCT calibration block 0, this does not affect OCT calibration block 1, whose calibration is already in progress. 7–36 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 255: Termination Schemes For I/O Standards
You still have to assert the ENASER signal for 28 OCTUSRCLK cycles for serial transfer. Termination The following section describes the different termination schemes for the I/O standards used in Stratix III devices. Schemes for I/O Standards Single-Ended I/O Standards Termination...
Page 256 Stratix III Stratix III Note to Figure 7–21: In Stratix III devices, series and parallel OCT cannot be used simultaneously. For more information, refer to “Dynamic On-Chip Termination” on page 7–28. 7–38 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 257: Differential I/O Standards Termination
25 Ω Note to Figure 7–22: In Stratix III devices, series and parallel OCT cannot be used simultaneously. For more information, refer to “Dynamic On-Chip Termination” on page 7–28. Differential I/O Standards Termination Stratix III devices support differential SSTL-2 and SSTL-18, differential HSTL-18, HSTL-15, HSTL-12, LVDS, LVPECL, RSDS, and mini-LVDS Figures 7–23...
Page 258 Termination Schemes for I/O Standards Figure 7–23. Stratix III Differential SSTL I/O Standard Termination Termination Differential SSTL Class II Differential SSTL Class I V TT V TT V TT V TT V TT V TT 50 Ω 50 Ω 50 Ω...
Page 259 LVDS requires a 100-Ω termination resistor between the two signals at the input buffer. Stratix III devices provide an optional 100-Ω differential termination resistor in the device using on-chip differential termination. Figure 7–25 shows the details of LVDS termination.
Page 260 Termination Schemes for I/O Standards Figure 7–25. Stratix III LVDS I/O Standard Termination Note (1) LVDS Termination Differential Outputs Differential Inputs External On-Board 50 Ω 100 Ω Termination 50 Ω Differential Outputs Differential Inputs 50 Ω OCT Receive 100 Ω...
Page 261 Stratix III Device I/O Features Differential LVPECL In Stratix III devices, the LVPECL I/O standard is supported on input clock pins on column and row I/O banks. LVPECL output operation is not supported by Stratix III devices. LVDS input buffers are used to support LVPECL input operation.
Page 262 Termination Schemes for I/O Standards RSDS Stratix III devices support the RSDS output standard with a data rate up to 230 Mbps using LVDS output buffer types. For transmitters, use the two single-ended output buffers with the external one- or three-resistor...
Page 263 Specification from the National Semiconductor web site at www.national.com. mini-LVDS Stratix III devices support the mini-LVDS output standard with a data rate up to 340 Mbps using LVDS output buffer types. For transmitters, use the two single-ended output buffers with the external one- or...
Page 264: Design Considerations
Differential I/O standards typically require a termination resistor between the two signals at the receiver. The termination resistor must match the differential load impedance of the signal line. Stratix III devices provide an optional differential on-chip resistor when using LVDS.
Page 265: I/O Banks Restrictions
I/O standards in Stratix III devices. Non-Voltage-Referenced Standards Each Stratix III device I/O bank has its own VCCIO pins and supports only one V , either 1.2, 1.5, 1.8, 2.5, 3.0, or 3.3 V. An I/O bank can...
Page 266: I/O Placement Guidelines
CCIO I/O Placement Guidelines This section provides I/O placement guidelines for the programmable I/O standards supported by Stratix III devices and includes essential information for designing systems using a Stratix III device’s selectable I/O capabilities. I/O Pin Placement with Respect to LVDS I/O Pins The placement of single-ended I/O pins with respect to LVDS I/O pins is restricted.
Page 267 HSTL/SSTL inputs. Single-ended outputs with a driving strength less than 8 mA and single-ended inputs without OCT R have no restriction. The single-ended I/O placement rules for column I/O are shown in Figure 7–31. Altera Corporation 7–49 November 2007 Stratix III Device Handbook, Volume 1...
Page 268: Conclusion
8 mA Conclusion Stratix III devices provide I/O capabilities that allow you to work in compliance with current and emerging I/O standards and requirements. With the Stratix III device features, you can reduce board design interface costs and increase development flexibility.
Page 269 Calibration”, and “Referenced Documents.” ● Added live links for references. May 2007 Added the feature programmable input delay to “Stratix III I/O — v1.1 Structure” on page 7–13. Updated Table 7–4 and Table 7–7. Updated “LVDS Input On-Chip Termination (RD)” on page 7–29.
Page 270 Referenced Documents 7–52 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 271: Introduction
Packed with features such as dynamic on-chip termination (OCT), trace mismatch compensation, read/write leveling, half data rate (HDR) blocks, and 4- to 36-bit programmable DQ group widths, Stratix III I/O elements provide easy-to-use built-in functionality required for a rapid and robust implementation.
Page 272 Memory interfaces above 333 MHz require the use of the deskew circuitry pending characterization. Support will be evaluated after characterization. Stratix III FPGAs support QDRII+ SRAM devices with 2.5 cycle read latency. Stratix III FPGAs do not support QDRII+ SRAM devices with 2.0 cycle read latency.
Page 273 External Memory Interfaces in Stratix III Devices Table 8–2. Stratix III Maximum Clock Rate Support for External Memory Interfaces with Full-Rate Controller Note (1), –2 Speed Grade –3 Speed Grade –4 Speed Grade -4L Speed Grade (MHz) (MHz) (MHz) (MHz)
Page 274 Introduction Figure 8–1. Stratix III Package Bottom View Note (1), DLL4 DLL1 PLL_T1 PLL_T2 PLL_L1 PLL_R1 PLL_R2 PLL_L2 Stratix III Device PLL_R3 PLL_L3 PLL_R4 PLL_L4 PLL_B1 PLL_B2 DLL3 DLL2 Notes to Figure 8–1: The number of I/O banks and PLLs available depends on the device density.
Page 275 Each register block can be bypassed. The blocks for each memory interface may differ slightly. This chapter describes the hardware features in Stratix III devices that facilitate high-speed memory interfacing for each DDR memory standard. Stratix III devices feature DLLs, PLLs, dynamic OCT, read/write leveling, and deskew ciruitry.
Page 276: Memory Interfaces Pin Support
Stratix III devices support all these different pins. Data and Data Clock/Strobe Pins Stratix III DDR memory interface data pins are called DQ pins. The read data-strobes or clocks are called DQS pins. Depending on the memory specifications, the DQS pins can be bi-directional single-ended signals (in...
Page 277 PVT variations. The DQS and DQ pin locations are fixed in the pin table. The memory interface circuitry is available in every Stratix III I/O bank. All the memory interface pins support the I/O standards required to support DDR3, DDR2, DDR SDRAM, QDRII+, QDRII SRAM, and RLDRAM II devices.
Page 278 Memory Interfaces Pin Support Every I/O bank in the Stratix III device can support DQS and DQ signals with DQ bus modes of ×4, ×8/×9, ×16/×18, or ×32/×36 although not all devices support ×16/×18 or ×32/×36 (see Table 8–5). In ×4 mode, each DQS and DQSn pin-pair drives up to four DQ pins within that group.
Page 279 DQS/DQ groups available per bank in each Stratix III device, see Figures 8–3 through Figure 8–7. These figures represent the package-bottom view of the Stratix III device. Table 8–5. Number of DQS/DQ Groups in Stratix III Devices per Side (Part 1 of 2) Note (1), Device Package Side ×4...
Page 280 Memory Interfaces Pin Support Table 8–5. Number of DQS/DQ Groups in Stratix III Devices per Side (Part 2 of 2) Note (1), Device Package Side ×4 ×8/×9 ×16/×18 ×32/×36 EP3SE260 780-pin Hybrid Left FineLine BGA Bottom Right 1152-pin Left FineLine BGA...
Page 281 External Memory Interfaces in Stratix III Devices Figure 8–3. Number of DQS/DQ Groups per Bank in EP3SE50, EP3SL50, and EP3SL70 Devices in 484-pin FineLine BGA Package Notes (1), I/O Bank 8C I/O Bank 7C 24 User I/Os 24 User I/Os...
Page 282 Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are not going to be used by your configuration scheme. All I/O pin counts include eight dedicated clock inputs (CLK1p, CLK1n, CLK3p, CLK3n, CLK8p, CLK8n, CLK10p, and CLK10n) 8–12 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 283 External Memory Interfaces in Stratix III Devices Figure 8–5. Number of DQS/DQ Groups in EP3SE80, EP3SE110, EP3SL110, EP3SL150, EP3SL200, EP3SE260, and EP3SL340 Devices in 1152-pin FineLine BGA Package Notes (1), I/O Bank 7A (3) I/O Bank 8A (3) I/O Bank 8B...
Page 284 Some of the DQS/DQ pins in this bank can also be used as configuration pins. Choose the DQS/DQ pins that are not going to be used by your configuration scheme. 8–14 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 285 External Memory Interfaces in Stratix III Devices Figure 8–7. DQS/DQ Bus Mode Support per Bank in EP3SL340 Devices in 1760-pin FineLine BGA Package Note (1) I/O Bank 8A (2) I/O Bank 8B I/O Bank 8C (2) I/O Bank 7C I/O Bank 7B...
Page 286 Memory Interfaces Pin Support The DQS and DQSn pins are listed in the Stratix III pin tables as DQSXY and DQSnXY, respectively, where X denotes the DQS/DQ grouping number, and Y denotes whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the device.
Page 287 External Memory Interfaces in Stratix III Devices Figure 8–8. DQS Pins in Stratix III I/O Banks DQS23T DQS22T DQS1T DQS44T DLL1 DLL4 PLL_T1 PLL_T2 PLL_L1 PLL_R1 DQS1L DQS40R DQS20L DQS21R PLL_R2 PLL_L2 Stratix III Device PLL_R3 PLL_L3 DQS21L DQS20R DQS40L...
Page 288: Optional Parity, Dm, Bwsn, Ecc And Qvld Pins
You can use any of the DQ pins from the same DQS/DQ group for data as parity pins in Stratix III devices. The Stratix III device family supports parity in the ×8/×9, ×16/×18, and ×32/×36 modes. There is one parity bit available per eight bits of data pins.
Page 289: Address And Control/Command Pins
8 data bits, which are referred to as the NWSn pins. Generate the DM or BWSn signals using DQ pins and configure the signals similarly to the DQ (or D) output signals. Stratix III devices do not support the DM signal in ×4 DDR3 SDRAM or in ×4 DDR2 SDRAM interfaces with differential DQS signaling.
Page 290: Memory Clock Pins
SRAM devices use the same clock (K/K#) to capture data, address, and control/command signals. The memory clock pins in Stratix III devices are generated using a DDIO register going to differential output pins, marked in the pin table with DIFFOUT, DIFFIO_TX, and DIFFIO_RX prefixes. For more information on which pins to use for memory clock pins, refer to Table 8–3...
Page 291 (PHY) best suited for your system. Memory This section describes each Stratix III device feature that is used in Interface external memory interfaces from the DQS phase-shift circuitry, DQS logic...
Page 292: Stratix Iii External Memory Interface Features
Stratix III External Memory Interface Features Figure 8–10. DQS and CQn Pins and DQS Phase-Shift Circuitry Note (1) Reference Reference DQS Logic Clock (2) Clock (2) Blocks Δt Δt Δt Δt Phase-Shift Phase-Shift Circuitry Circuitry to IOE to IOE to IOE...
Page 293 There are four DLLs in a Stratix III device, located in each corner of the device. These four DLLs can support a maximum of four unique frequencies, with each DLL running at one frequency.
Page 294 Stratix III External Memory Interface Features Figure 8–11. Stratix III DLL and I/O Bank Locations (Package-Bottom View) PLL_R1 PLL_L1 PLL_T2 PLL_T1 DLL1 DLL4 PLL_L2 PLL_R2 Stratix III FPGA PLL_L3 PLL_R3 DLL3 DLL2 PLL_L4 PLL_B1 PLL_B2 PLL_R4 The DLL can access the two adjacent sides from its location within the device.
Page 295 Table 8–7 lists the DLL location and supported I/O banks for Stratix III devices. Note, however, that you can only have one memory interface in I/O banks with the same I/O bank number (such as I/O banks 1A, 1B, and 1C) when the leveling delay chains are used.
Page 296 Stratix III External Memory Interface Features When you have a dedicated PLL that only generate the DLL input reference clock, set the PLL mode to No Compensation, or the Quartus II software will change it automatically. Because the PLL does not use any other outputs, it does not need to compensate for any clock paths.
Page 297 External Memory Interfaces in Stratix III Devices Table 8–9. DLL Reference Clock Input for EP3SE80, EP3SE110, and EP3SL150 Devices in the 780-pin Package CLKIN CLKIN (Top/Bottom) (Left/Right) (Top/Bottom) (Left/Right) DLL3 CLK4P, CLK8P, CLK5P, CLK9P, CLK6P, CLK10P, CLK7P CLK11P DLL4 CLK12P,...
Page 298 Stratix III External Memory Interface Features Table 8–11. DLL Reference Clock Input for EP3SL200, EP3SE260 and EP3SL340 Devices CLKIN CLKIN (Top/Bottom) (Left/Right) (Top/Bottom) (Left/Right) DLL1 CLK12P, CLK0P, PLL_T1 PLL_L1 CLK13P, CLK1P, PLL_L2 CLK14P, CLK2P, CLK15P CLK3P DLL2 CLK4P, CLK0P, PLL_B1...
Page 299 External Memory Interfaces in Stratix III Devices Figure 8–12. Simplified Diagram of the DQS Phase Shift Circuitry Note (1) addnsub_a Phase offset settings from the logic array Phase Phase offset Offset settings to DQS pins Control on top or bottom edge (3)
Page 300 22.5° (up to 90°), a multiple of 30° (up to 120°), a multiple of 36° (up to 144°), or a multiple of 45° (up to 180°). There are six different frequency modes for the Stratix III DLL, as shown Table 8–12.
Page 301 5-bit DLL delay settings. Refer to the DC and Switching Characteristics of Stratix III Devices chapter in volume 2 of the Stratix III Device Handbook for information on the value for each step. Altera Corporation 8–31 November 2007...
Page 302: Dqs Phase-Shift Circuitry
The input reference clock for the DQS phase-shift circuitry can come from a PLL output clock or an input clock pin. Refer to Tables 8–8 through 8–11 for the exact PLL and input clock pin. The dqsenable signal can also come from the Stratix III FPGA fabric. 8–32 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 303 External Memory Interfaces in Stratix III Devices DQS Delay Chain The DQS delay chains consist of a set of variable delay elements to allow the input DQS and CQn signals to be shifted by the amount specified by the DQS phase-shift circuitry or the logic array. There are four delay elements in the DQS delay chain;...
Page 304 DQS line at the end of a read postamble time. Stratix III devices have a dedicated postamble register that can be controlled to ground the shifted DQS signal used to clock the DQ input registers at the end of a read operation.
Page 305 The postamble clock can come from any of the delayed resynchronization clock taps although it is not necessarily of the same phase as the resynchronization clock. The dqsenable signal can also come from the Stratix III FPGA fabric. In addition to the dedicated postamble register, Stratix III devices also have an HDR block inside the postamble enable circuitry.
Page 306: Leveling Circuitry
Stratix III External Memory Interface Features Figure 8–16. Avoiding Glitch on a Non-Consecutive Read Burst Waveform Postamble glitch Postamble Preamble Postamble Enable dqsenable Delayed by 1/2T logic Leveling Circuitry DDR3 SDRAM unbuffered modules use a fly-by clock distribution topology for better signal integrity. This means that the CK/CK# signals arrive at each DDR3 SDRAM device in the module at different times.
Page 307 DQSS device on the modules. Furthermore, read data coming back into the FPGA from the memory will also be staggered in a similar way. Stratix III FPGAs have leveling circuitry to take care of these two needs. There is one group of leveling circuitry per I/O bank, with the same I/O number (for example, there is one leveling circuitry shared between I/O bank 1A, 1B, and 1C) located in the middle of the I/O bank.
Page 308: Dynamic On-Chip Termination Control
For more information refer to section “OCT” on page 8–43, or to the Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device Handbook. Figure 8–19. Stratix III Dynamic OCT Control Block OCT Control OCT Enable...
Page 309: I/O Element (Ioe) Registers
IOEs having extra features to support LVDS data transfer. Figure 8–20 shows the registers available in the Stratix III input path. The input path consists of the DDR input registers, resynchronization registers, and HDR block. Each block of the input path can be bypassed.
Page 310 Stratix III External Memory Interface Features Figure 8–20. Stratix III IOE Input Registers Note (1) Half Data Rate Registers to core Double Data Rate Input Registers dataoutbypass (8) to core Alignment & Synchronization Input Reg A Registers (2) to core...
Page 311 “Leveling Circuitry” on page 8–36. Figure 8–21 shows the registers available in the Stratix III output and output-enable paths. The path is divided into the HDR block, resynchronization registers, and output/output-enable registers. The device can bypass each block of the output and output-enable path.
Page 312 Stratix III External Memory Interface Features Figure 8–21. Stratix III IOE Output and Output-Enable Path Registers Note (1) Half Data Rate to Single Data Rate Output-Enable Registers From Core (2) Double Data Rate Output-Enable Registers Alignment Registers (4) From Core (2)
Page 313: Ioe Features
Stratix III Device I/O Features chapter in volume 1 of the Stratix III Device Handbook. Stratix III devices feature dynamic calibrated OCT, in which the series termination (OCT R ) is turned on when driving signals and turned off when receiving signals, while the parallel termination (OCT R ) is turned off when driving signals and turned on when receiving signals.
Page 314 Programmable Slew Rate Control Stratix III devices provide four levels of static output slew rate control: 0, 1, 2, and 3, where 0 is the slowest slew rate setting and 3 is the fastest slew rate setting.
Page 315: Pll
Altera’s IP controller. In Stratix III devices, most of the critical data transfers are taken care of for you in the IOE, alleviating the burden of having to close timing in the FPGA fabric.
Page 316: Referenced Documents
Stratix III to support DDR3 modules, thus offering customers the choice of highest performance memory technologies. Stratix III devices also offer memory interface support in any of 24 modular I/O banks with up to four different frequencies of operations.
Page 317: Introduction
III device family offers up to 1.25-Gbps differential I/O capabilities to support source-synchronous communication protocols such as Utopia, Rapid I/O™, XSBI, SGMII, SFI, and SPI. Stratix III devices have the following dedicated circuitry for high-speed differential I/O support: ■ Differential I/O buffer ■...
Page 318: I/O Banks
I/O Banks I/O Banks The Stratix III I/Os are divided into 16 to 24 I/O banks. The dedicated circuitry that supports high-speed differential I/Os is located in banks in the right side and left side of the device. Figure 9–1 shows the different banks and the I/O standards supported by the banks.
Page 319: Lvds Channels
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices LVDS Channels The Stratix III device supports LVDS at both side I/O banks and column I/O banks. There are true LVDS input and output buffers at side I/O banks. On column I/O banks, there are true LVDS input buffers but no true LVDS output buffers.
Page 320: Differential Transmitter
Differential Transmitter Table 9–2. LVDS Channels (Emulated) Supported in Stratix III Device Column I/O Banks Note (1) 484 - Pin 780 - Pin 1152 - Pin 1517 - Pin 1780 - Pin Device FineLine BGA FineLine BGA FineLine BGA FineLine BGA...
Page 321 PLL_Lx / PLL_Rx load_en Any Stratix III transmitter data channel can be configured to generate a source synchronous transmitter clock output. This flexibility allows placing the output clock near the data outputs to simplify board layout and reduce clock-to-data skew. Different applications often require specific clock-to-data alignments or specific data rate to clock rate factors.
Page 322 PLL_Lx / PLL_Rx load_en The Stratix III serializer can be bypassed to support DDR (×2) and SDR (×1) operations to achieve a serialization factor of 2 and 1, respectively. The I/O element (IOE) contains two data output registers that can each operate in either DDR or SDR mode.
Page 323 10 bits to the internal logic. The data path in the Stratix III receiver is clocked by either a dffioclk signal or the DPA recovered clock. The deserialization factor can be statically set to 4, 6, 7, 8, or 10 by using the Quartus II software.
Page 324 Differential Transmitter The Stratix III deserializer can be bypassed in the Quartus II MegaWizard to support DDR(×2) or SDR(×1) operations. The DPA and the data realignment circuit cannot be used when the deserializer is bypassed. The IOE contains two data input registers that can operate in DDR or SDR mode.
Page 325: Receiver Data Realignment Circuit (Bit Slip)
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Receiver Data Realignment Circuit (Bit Slip) Skew in the transmitted data along with skew added by the link causes channel-to-channel skew on the received serial data streams. If the DPA is enabled, the received data is captured with different clock phases on each channel.
Page 326: Dynamic Phase Aligner (Dpa)
The RX_DPA_LOCKED signal is synchronized to the DPA clock domain and should be considered as the initial indicator for the lock condition. Use data checkers to validate the data integrity. 9–10 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 327: Soft-Cdr Mode
The DPA circuitry must be retrained after reset. Soft-CDR Mode The Stratix III LVDS channel offers the soft-CDR mode to support the Gigabit Ethernet/SGMII protocols. Clock-data recovery (CDR) is required to extract the clock out of the clock-embedded data to support SGMII.
Page 328: Synchronizer
An optional port, RX_FIFO_RESET, is available to the internal logic to reset the synchronizer. The synchronizer is automatically reset when the DPA first locks to the incoming data. Altera recommends using RX_FIFO_RESET to reset the synchronizer when the DPA signals a loss-of-lock condition beyond the initial locking condition.
Page 329: Differential I/O Termination
Stratix III pre-emphasis is programmable to create the right amount of overshoot at different transmission conditions. There are four settings for pre-emphasis: zero, low, medium, and high. The default setting is low.
Page 330: Left/Right Plls (Pll_Lx/ Pll_Rx)
Left/Right PLLs (PLL_Lx/ PLL_Rx) Left/Right PLLs Stratix III devices contain up to eight left/right PLLs with up to four PLLs located on the left side and four on the right side of the device. The left (PLL_Lx/ PLLs can support high-speed differential I/O banks on the left side and the right PLLs can support banks on the right side of the device.
Page 331: Clocking
Figure 9–13 Figure 9–14 show center and corner PLL clocking in Stratix III devices. More information on PLL clocking restrictions can be found in “Differential Pin Placement Guidelines” on page 9–21. Figure 9–13. LVDS/DPA Clocks in Stratix III Devices with Center PLLs...
Page 332: Source-Synchronous Timing Budget
Clocking Figure 9–14. LVDS/DPA Clocks in Stratix III Devices with Center and Corner PLLs Corner Corner PLL_R1 PLL_L1 LVDS LVDS Clock Clock Clock Clock Quadrant Quadrant Center Center PLL_L2 PLL_R2 Center Center PLL_L3 PLL_R3 Quadrant Quadrant LVDS LVDS Clock Clock...
Page 333: Differential Data Orientation
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Differential Data Orientation There is a set relationship between an external clock and the incoming data. For operation at 1 Gbps and SERDES factor of 10, the external clock is multiplied by 10, and phase-alignment can be set in the PLL to coincide with the sampling window of each data bit.
Page 334 The MSB and LSB positions increase with the number of channels used in a system. Table 9–3. Differential Bit Naming (Part 1 of 2) Internal 8-bit parallel data Receiver Channel Data Number MSB position LSB position 9–18 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 335: Receiver Skew Margin For Non-Dpa
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Table 9–3. Differential Bit Naming (Part 2 of 2) Internal 8-bit parallel data Receiver Channel Data Number MSB position LSB position Receiver Skew Margin for Non-DPA Changes in system environment, such as temperature, media (cable, connector, or PCB) loading effect, the receiver’s setup and hold times, and...
Page 336 (max) Bit n Clock Bit n Falling Edge Timing Budget External Clock Clock Placement Internal Clock Synchronization Transmitter Output Data RSKM RSKM TCCS TCCS Receiver Input Data Sampling Window 9–20 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 337: Differential Pin Placement Guidelines
DPA usage. Guidelines for DPA-Enabled Differential Channels The Stratix III device has differential receivers and transmitters in I/O banks on the left and right sides of the device. Each receiver has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel.
Page 338 (26 contiguous rows on the upper banks and 26 contiguous rows on the lower banks simultaneously, as shown in Figure 9–19). ■ The 26 contiguous rows do not need to be adjacent to the driving PLL. 9–22 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 339 High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Figure 9–19. Left/Right PLL Driving Distance for DPA-Enabled Channels Corner Left / Right Corner Left / Right Reference Reference DPA-enabled DPA-enabled Diff I/O Diff I/O Maximum 26 channels driven by the corner...
Page 340 Figure 9–20). The two groups can operate at independent frequencies. ■ No separation is necessary if a single left/right PLL is driving DPA-enabled channels as well as DPA-disabled channels. 9–24 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 341 High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Figure 9–20. Corner and Center Left/Right PLLs Driving DPA-Enabled Differential I/Os in the Same Bank Corner Left Right PLL Reference DPA -enabled Diff I/O Channels driven by DPA - enabled...
Page 342 PLL_L3/PLL_R3 cannot drive DPA-enabled channels in the upper differential banks and vice versa. In other words, the center left/right PLLs cannot drive cross- banks simultaneously, as shown in Figure 9–22. 9–26 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 343 High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Figure 9–21. Center Left/Right PLLs Driving DPA-Enabled Differential I/Os DPA-enabled DPA-enabled Diff I/O Diff I/O DPA-enabled DPA-enabled Diff I/O Diff I/O DPA-enabled DPA-enabled Diff I/O Diff I/O DPA-enabled DPA-enabled Diff I/O...
Page 344 DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O Reference Center Left /Right Center Left /Right Reference DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O DPA-enabled Diff I/O 9–28 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 345: Guidelines For Dpa-Disabled Differential Channels
High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Guidelines for DPA-Disabled Differential Channels When DPA-disabled channels are used in the left and right banks of a Stratix III device, you must adhere to the guidelines in the following sections. DPA-Disabled Channels and Single-Ended I/Os The placement rules for DPA-disabled channels and single-ended I/Os are the same as those for DPA-enabled channels and single-ended I/Os.
Page 346 Diff RX Diff TX Diff I/O driven by DPA-disabled Center Diff RX Diff TX Diff I/O Left/Right DPA-disabled Diff RX Diff TX Diff I/O Reference Reference Center Left/Right Center Left/Right 9–30 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 347 High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Figure 9–24. Invalid Placement of DPA-Disabled Differential I/Os Due to Interleaving of Channels Driven by the Corner and Center Left/Right PLLs Corner Left/Right Reference CLK DPA-disabled Diff I/O DPA-disabled Diff I/O...
Page 348 For example, the upper center left/right PLL can drive the lower differential bank at the same time the lower center left/right PLL is driving the upper differential bank and vice versa, as shown in Figure 9–25. 9–32 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 349 High-Speed Differential I/O Interfaces and DPA in Stratix III Devices Figure 9–25. Both Center Left/Right PLLs Driving Cross-Bank DPA-Disabled Channels Simultaneously DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O DPA-disabled Diff I/O Reference Center Left/Right PLL Center Left/Right PLL...
Page 350: Referenced Documents
Referenced Documents Referenced This chapter references the following document: Documents ■ Clock Network and PLLs in Stratix III Devices Document Table 9–4 shows the revision history for this document. Revision History Table 9–4. Document Revision History Date and Document Changes Made...
Page 351: Section Iii. Hot Socketing, Configuration, Remote Upgrades, And Testing
Stratix III devices, remote system upgrades, and IEEE 1149.1 (JTAG) Boundary-Scan Testing in the following sections: ■ Chapter 10, Hot Socketing and Power-On Reset in Stratix III Devices ■ Chapter 11, Configuring Stratix III Devices ■ Chapter 12, Remote System Upgrades With Stratix III Devices ■...
Page 352 Hot Socketing, Configuration, Remote Upgrades, and Testing Stratix III Device Handbook, Volume 1 Section III–2 Altera Corporation...
Page 353: Introduction
The hot socketing feature also removes some of the difficulty when you use Stratix III devices on printed circuit boards (PCBs) that contain a mixture of 3.3, 3.0, 2.5, 1.8, 1.5 and 1.2 V devices. With the Stratix III hot socketing feature, you no longer need to ensure a proper power-up sequence for each device on the board.
Page 354: Stratix Iii Hot-Socketing Specifications
This irregular power-up can damage both the driving and driven devices and can disrupt card power-up. A Stratix III device may be inserted into (or removed from) a powered-up system board without damaging or interfering with system-board operation.
Page 355 Each I/O pin has the following circuitry shown in Figure 10–1. Figure 10–1. Hot Socketing Circuit Block Diagram for Stratix III Devices Power On Reset Monitor CCIO Weak...
Page 356: Power-On Reset Circuitry
CCPGM CCPT device is in user mode. The weak pull-up resistor (R) in the Stratix III input/output element (IOE) keeps the I/O pins from floating. The 3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3 V before...
Page 357 Hot Socketing and Power-On Reset in Stratix III Devices The POR block consists of a regulator POR, satellite POR, and main POR to check the power supply levels for proper device configuration. The satellite POR monitors V and V power supplies that are used in...
Page 358: Power-On Reset Specifications
65 ms to 100 ms internal POR delay to be powered-up and ready to receive the nSTATUS signal from Stratix III. When the PORSEL is set to high, the POR signal pulse width is set to 12 ms. A POR pulse width of 12 ms allows time for power supplies to ramp-up to full rail.
Page 359: Conclusion
Hot Socketing and Power-On Reset in Stratix III Devices Conclusion Stratix III devices are hot-socketing compliant and allow successful device power-up without the need for any power sequencing. The POR circuitry keeps the devices in the reset state until the power supply voltage levels are within operating range.
Page 360 Document Revision History 10–8 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 361: Introduction
Configuration Devices The Altera serial configuration devices (EPCS128, EPCS64, and EPCS16) support a single-device and multi-device configuration solution for Stratix III devices and are used in the fast AS configuration scheme. Serial configuration devices offer a low-cost, low-pin count configuration solution.
Page 362 JTAG-based configuration Notes to Table 11–1: Stratix III only supports Fast AS configuration. You would need to use either EPCS16, EPCS64, or EPCS128 devices. ® These modes are only supported when using a MAX II device or a microprocessor with flash memory for configuration.
Page 363: Configuration Features
Stratix III devices offer design security, decompression, and remote system upgrade features. Design security using configuration bitstream Features encryption is available in Stratix III devices, which protects your designs. Stratix III devices can receive a compressed configuration bitstream and decompress this data in real-time, reducing storage requirements and configuration time.
Page 364: Configuration Data Decompression
Fast AS configuration scheme. Local update mode is not supported. If your system already contains a common flash interface (CFI) flash memory, you can use it for the Stratix III device configuration storage as well. The MAX II parallel flash loader (PFL) feature in MAX II devices...
Page 365 Stratix III device. The time required by a Stratix III device to decompress a configuration file is less than the time needed to transmit the configuration data to the device.
Page 366 Configuration Features Figure 11–1. Enabling Compression for Stratix III Bitstreams in Compiler Settings You can also enable compression when creating programming files from the Convert Programming Files window. Click Convert Programming Files (File menu). Select the programming file type (.pof, .sram, .hex, .rbf, or .ttf).
Page 367 Select the name of the file you added to the SOF Data area and click Properties. Check the Compression check box. When multiple Stratix III devices are cascaded, you can selectively enable the compression feature for each device in the chain if you are using a serial configuration scheme.
Page 368: Design Security Using Configuration Bitstream Encryption
Non-volatile key programming does not require any external devices, such as a battery backup, for storage. However, for different applications, you can store the security keys in volatile memory in the Stratix III device. An external battery is needed for this volatile key storage.
Page 369: Vccpgm Pins
, for all the dedicated CCPGM configuration pins and dual function pins. Configuration voltage supported is 1.8 V, 2.5 V, 3.0 V, and 3.3 V. Stratix III devices do not support 1.5 V configuration. Use this pin to power all dedicated configuration inputs, dedicated configuration outputs, dedicated configuration bidirectional pins, and some of the dual functional pins that you use for configuration.
Page 370: Fpp Configuration Using A Max Ii Device As An External Host
The ×4 DCLK signal does not require an additional pin and is sent on the DCLK pin. The maximum DCLK frequency is 100 MHz, which results in a maximum data rate of 200 Mbps. If you are not using the Stratix III decompression or design security features, the data rate is ×8 the DCLK frequency.
Page 371 I/O on the device and the external host. Upon power-up, the Stratix III device goes through a POR. The POR delay is dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is approximately 100 ms. When PORSEL is driven high, the POR time is approximately 12 ms.
Page 372 CONF_DONE pin must have an external 10-kΩ pull-up resistor in order for the device to initialize. In Stratix III devices, the initialization clock source is either the internal oscillator (typically 10 MHz) or the optional CLKUSR pin. By default, the internal oscillator is the clock source for initialization.
Page 373 DCLK for an indefinite amount of time. If you are using the Stratix III decompression and/or design security feature and need to stop DCLK, it can only be stopped three clock cycles after the last data byte was latched into the Stratix III device.
Page 374 MAX II device. This circuit is similar to the FPP configuration circuit for a single device, except the Stratix III devices are cascaded for multi-device configuration. Figure 11–4. Multi-Device FPP Configuration Using an External Host Memory ADDR DATA[7..0]...
Page 375 (with a low pulse of at least 2 ms) on nCONFIG to restart the configuration process. In a multi-device FPP configuration chain, all Stratix III devices in the chain must either enable or disable the decompression and/or design security feature.
Page 376 V specification of the I/O on the device and the external host. The nCEO pins of both Stratix III devices are left unconnected when configuring the same configuration data into multiple devices. You can use a single configuration chain to configure Stratix III devices with other Altera devices that support FPP configuration, such as other types of Stratix devices.
Page 377 The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. Upon power-up, the Stratix III device holds nSTATUS low for the time of the delay.
Page 378 Fast Passive Parallel Configuration Table 11–5. FPP Timing Parameters for Stratix III Devices Notes (1), (Part 2 of 2) Symbol Parameter Minimum Maximum Units — Data setup time before rising edge on DCLK — Data hold time after rising edge on...
Page 379 CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay. Upon power-up, before and during configuration, CONF_DONE is low.
Page 380 Table 11–6 defines the timing parameters for Stratix III devices for FPP configuration when the decompression and/or the design security feature are enabled. Table 11–6. FPP Timing Parameters for Stratix III Devices With Decompression or Design Security Feature Enabled Notes (1),...
Page 381: Fpp Configuration Using A Microprocessor
Refer to this section for all configuration and timing information. Fast Active In the fast AS configuration scheme, Stratix III devices are configured using a serial configuration device. These configuration devices are Serial low-cost devices with non-volatile memory that feature a simple four-pin interface and a small form factor.
Page 382: Fast Active Serial Configuration (Serial Configuration Devices)
Connect the pull-up resistors to a 3.3-V supply. Stratix III devices use the ASDO-to-ASDI path to control the configuration device. Upon power-up, the Stratix III devices go through a POR. The POR delay is dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is approximately 100 ms.
Page 383 DCLK. The serial configuration device responds to the instructions by driving out configuration data on the falling edge of DCLK. Then the data is latched into the Stratix III device on the following falling edge of DCLK.
Page 384 If the Auto-restart configuration after error option (available in the Quartus II software from the General tab of the Device and Pin Options dialog box) is turned on, the Stratix III device resets the configuration device by pulsing nCSO, releases nSTATUS after a reset time-out period (maximum of 100 ms), and retries configuration.
Page 385 Configuring Stratix III Devices PS configuration scheme. Any other Altera device that supports PS configuration can also be part of the chain as a configuration slave. Figure 11–9 shows the pin connections for this setup. Figure 11–9. Multi-Device Fast AS Configuration 10 kΩ...
Page 386 To configure four identical Stratix III devices with the same SOF, you could set up the chain similar to the example shown in Figure 11–10.
Page 387: Estimating Active Serial Configuration Time
Stratix III device. This serial interface is clocked by the Stratix III DCLK output (generated from an internal oscillator). As the Stratix III device only supports fast AS configuration, the DCLK frequency needs to be set to 40 MHz (25 ns).
Page 388: Programming Serial Configuration Devices
During in-system programming, the download cable disables device access to the AS interface by driving the nCE pin high. Stratix III devices are also held in reset by a low level on nCONFIG. After programming is...
Page 389 Power up the ByteBlaster II cable's V with a 3.3-V supply. You can program serial configuration devices with the Quartus II software using the Altera programming hardware and the appropriate configuration device programming adapter. In production environments, you can program serial configuration devices using multiple methods.
Page 390 1 bit 0 CD2UM INIT_DONE User I/O User Mode Note to Figure 11–12: The initialization clock can come from the Stratix III device's internal oscillator or the CLKUSR pin. 11–30 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 391: Passive Serial Configuration
In this configuration scheme, you can use a MAX II device as an intelligent host that controls the transfer of configuration data from a storage device, such as flash memory, to the target Stratix III device. You can store configuration data in .rbf, .hex, or .ttf format.
Page 392 I/O on the device and the external host. Upon power-up, Stratix III devices go through a POR. The POR delay is dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is approximately 100 ms. When PORSEL is driven high, the POR time is approximately 12 ms.
Page 393 EE 01 FA, the serial bitstream you should transmit to the device is 0100-0000 1101-1000 0111-0111 1000-0000 0101-1111. The Stratix III device receives configuration data on the DATA0 pin and the clock is received on the DCLK pin. Data is latched into the device on the rising edge of DCLK.
Page 394 (available in the Quartus II software from the General tab of the Device and Pin Options dialog box) is turned on, the Stratix III device releases nSTATUS after a reset time-out period (maximum of 100 ms). After nSTATUS is released and pulled high by a pull-up resistor, the MAX II device can try to reconfigure the target device without needing to pulse nCONFIG low.
Page 395 MAX II device. This circuit is similar to the PS configuration circuit for a single device, except Stratix III devices are cascaded for multi-device configuration. Figure 11–14. Multi-Device PS Configuration Using an External Host...
Page 396 Devices must be the same density and package. All devices will start and complete configuration at the same time. Figure 11–15 shows multi-device PS configuration when both Stratix III devices are receiving the same configuration data. Figure 11–15. Multiple-Device PS Configuration When Both devices Receive the Same Data...
Page 397 CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins. Upon power-up, the Stratix III device holds nSTATUS low for the time of the POR delay. Upon power-up, before and during configuration, CONF_DONE is low.
Page 398 Passive Serial Configuration Table 11–10 defines the timing parameters for Stratix III devices for PS configuration. Table 11–10. PS Timing Parameters for Stratix III Devices Note (1) Symbol Parameter Minimum Maximum Units low to — nCONFIG CONF_DONE CF2CD — nCONFIG...
Page 399: Ps Configuration Using A Microprocessor
PC) transfers data from a storage device to the device via the USB Blaster, MasterBlaster, ByteBlaster II, EthernetBlaster, or ByteBlasterMV cable. Upon power-up, the Stratix III devices go through a POR. The POR delay is dependent on the PORSEL pin setting. When PORSEL is driven low, the POR time is approximately 100 ms.
Page 400 Quartus II programmer and a download cable. Figure 11–17 shows PS configuration for Stratix III devices using a USB Blaster, MasterBlaster, ByteBlaster II, or ByteBlasterMV cable. Figure 11–17. PS Configuration Using a USB Blaster, MasterBlaster, ByteBlaster II, or ByteBlasterMV Cable 10 kΩ...
Page 401 Configuring Stratix III Devices You can use a download cable to configure multiple Stratix III devices by connecting each device's nCEO pin to the subsequent device's nCE pin. The first device's nCE pin is connected to GND while its nCEO pin is connected to the nCE of the next device in the chain.
Page 402 USB Blaster USB Port Download Cable Data Sheet ■ MasterBlaster Serial/USB Communications Cable Data Sheet ■ ByteBlaster II Parallel Port Download Cable Data Sheet ■ ByteBlasterMV Parallel Port Download Cable Data Sheet 11–42 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 403: Jtag Configuration
Quartus II software programmer. For more information on JTAG boundary-scan testing and commands available using Stratix III devices, refer to the following documents: ■ IEEE 1149.1 (JTAG) Boundary Scan Testing in Stratix III Device...
Page 404 TRST pin to V . This ensures that the TAP controller is not reset. Figure 11–19 shows JTAG configuration of a single Stratix III device. 11–44 Altera Corporation Stratix III Device Handbook, Volume 1...
Page 405 (.jam) for a multi-device chain, it contains instructions so that all the devices in the chain will be initialized at the same time. If CONF_DONE is not high, the Quartus II software indicates that configuration has failed. Altera Corporation 11–45 November 2007 Stratix III Device Handbook, Volume 1...
Page 406 Stratix III devices have dedicated JTAG pins that always function as JTAG pins. Not only can you perform JTAG testing on Stratix III devices before and after, but also during configuration. While other device families do not support JTAG testing during configuration, Stratix III devices support the bypass, id code, and sample instructions during configuration without interrupting configuration.
Page 407 The number of devices in the JTAG chain is limited only by the drive capability of the download cable. When four or more devices are connected in a JTAG chain, Altera recommends buffering the TCK, TDI, and TMS pins with an on-board buffer.
Page 408 When the CONF_DONE and nSTATUS signals are shared among all the devices, you must configure every device when JTAG configuration is performed. If you only use JTAG configuration, Altera recommends that you connect the circuitry as shown in Figure 11–20, where each of the CONF_DONE and...
Page 409 JTAG chain for device programming and configuration. JTAG configuration support has been enhanced and allows more than 17 Stratix III devices to be cascaded in a JTAG chain. For more information on configuring multiple Altera devices in the same configuration chain, refer to the Configuring Mixed Altera Device Chains chapter in the Configuration Handbook.
Page 410: Jam Stapl
AN 122: Using Jam STAPL for ISP and ICR via an Embedded Processor. To download the jam player, visit the Altera web site at www.altera.com. Device The following tables describe the connections and functionality of all the configuration-related pins on the Stratix III devices.
Page 411 Configuring Stratix III Devices Table 11–13. Stratix III Configuration Pin Summary Note (1) (Part 2 of 2) Description Input/Output Dedicated Powered By Configuration Mode Output ASDO CCPGM Output nCSO CCPGM Input PS, FPP DCLK CCPGM — Output — CCPGM Input...
Page 412 Device Configuration Pins Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 1 of 6) Configuration Pin Name User Mode Pin Type Description Scheme Power Dedicated power pin. Use this pin to power all VCCPGM dedicated configuration inputs, dedicated...
Page 413 Configuring Stratix III Devices Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 2 of 6) Configuration Pin Name User Mode Pin Type Description Scheme Input Dedicated input which selects between a POR PORSEL time of 12 ms or 100 ms. A logic high (1.8 V, 2.5 V, 3.0 V, 3.3 V) selects a POR time of...
Page 414 Device Configuration Pins Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 3 of 6) Configuration Pin Name User Mode Pin Type Description Scheme Bi-directional The device drives low immediately nSTATUS nSTATUS open-drain after power-up and releases it after the POR time.
Page 415 Configuring Stratix III Devices Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 4 of 6) Configuration Pin Name User Mode Pin Type Description Scheme — — — If V and V are not fully powered up, nSTATUS...
Page 416 Device Configuration Pins Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 5 of 6) Configuration Pin Name User Mode Pin Type Description Scheme Input Active-low chip enable. The pin activates the device with a low signal to allow configuration.
Page 417 Configuring Stratix III Devices Table 11–14. Dedicated Configuration Pins on the Stratix III Device (Part 6 of 6) Configuration Pin Name User Mode Pin Type Description Scheme Synchronous Input (PS, In PS and FPP configuration, is the DCLK DCLK configuration...
Page 418 JTAG instructions. The TDI, TMS, and TRST have weak internal pull-up resistors while TCK has a weak internal pull-down resistor (typically 11–58 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 419 25 kΩ). If you plan to use the SignalTap embedded logic array analyzer, you need to connect the JTAG pins of the Stratix III device to a JTAG header on your board. Table 11–16. Dedicated JTAG Pins (Part 1 of 2)
Page 420: Conclusion
GND. TRST Conclusion You can configure Stratix III devices in a number of different schemes to fit your system's needs. In addition, configuration bitstream encryption, configuration data decompression, and remote system upgrade support supplement the Stratix III configuration solution.
Page 421 Removed Figure 11–19. ● Added live links for references. ● Added section “Referenced Documents” May 2007 Removed Bank Column from Table 11–13. — v1.1 November 2006 Initial Release — v1.0 Altera Corporation 11–61 November 2007 Stratix III Device Handbook, Volume 1...
Page 422: Document Revision History
Document Revision History 11–62 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 423: Introduction
(either the Nios II embedded processor or user logic) implemented in a Stratix III device can download a new configuration image from a remote location, store it in configuration memory, and direct the dedicated remote system upgrade circuitry to initiate a reconfiguration cycle.
Page 424 Stratix III devices have remote system upgrade processes that involves the following steps: A Nios II processor (or user logic) implemented in the Stratix III device logic array receives new configuration data from a remote location. The connection to the remote source uses a communication...
Page 425 Fast AS configuration scheme. Figure 12–2 shows the block diagrams for implementing a remote system upgrade with the Stratix III Fast AS configuration scheme. Figure 12–2. Remote System Upgrade Block Diagram for Stratix III Fast AS Configuration Scheme Stratix III Device...
Page 426: Enabling Remote Update
Enabling Remote Update You can enable remote update for Stratix III devices in the Quartus II software before design compilation (in the Compiler Settings menu). To enable remote update in the project’s compiler settings, perform the following steps in the Quartus II software: On the Assignment menu, click Device.
Page 427: Configuration Image Types
Stratix III device that performs certain user-defined functions. Each Stratix III device in your system requires one factory image or the addition of one or more application images. The factory image is a user-defined fall-back, or safe configuration, and is responsible for administering remote updates in conjunction with the dedicated circuitry.
Page 428: Remote System Upgrade Mode
Remote Update Mode When a Stratix III device is first powered-up in remote update mode, it loads the factory configuration located at page zero (page registers PGM[23:0] = 24'b0). You should always store the factory configuration image for your system at page address zero.
Page 429 Remote System Upgrades With Stratix III Devices ■ Communicate with the remote host and receive new application configurations and store this new configuration data in the local non-volatile memory device ■ Determine which application configuration is to be loaded into the Stratix III device ■...
Page 430: Dedicated Remote System Upgrade Circuitry
In user mode, the soft logic (Nios II processor or state machine and the remote communication interface) assists the Stratix III device in determining when a remote system update is arriving. When a remote system update arrives, the soft logic receives the incoming data, writes it to the configuration memory device, and triggers the device to load the factory configuration.
Page 431 Remote System Upgrades With Stratix III Devices Figure 12–5. Remote System Upgrade Circuit Data Path Note (1) Internal Oscillator Status Register (SR) Control Register [4..0] [37..0] Logic Array Update Register [37..0] update Shift Register User timeout dout dout Watchdog State Bit [4..0]...
Page 432: Remote System Upgrade Registers
12–3. In the figure, the numbers show the bit position of a setting within a register. For example, bit number 8 is the enable bit for the watchdog timer. 12–10 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 433 PGM[23..0] The application-not-factory (AnF) bit indicates whether the current configuration loaded in the Stratix III device is the factory configuration or an application configuration. This bit is set low by the remote system upgrade circuitry when an error condition causes a fall-back to the factory configuration.
Page 434 Note to Table 12–4: Logic array reconfiguration forces the system to load the application configuration data into the Stratix III device. This occurs after the factory configuration specifies the appropriate application configuration page address by updating the update register. 12–12...
Page 435: Remote System Upgrade State Machine
Remote System Upgrades With Stratix III Devices Remote System Upgrade State Machine The remote system upgrade control and update registers have identical bit definitions, but serve different roles (refer to Table 12–2). While both registers can only be updated when the device is loaded with a factory configuration image, the update register writes are controlled by the user logic;...
Page 436: User Watchdog Timer
The user watchdog timer is disabled in factory configurations and during the configuration cycle of the application configuration. It is enabled after the application configuration enters user mode. 12–14 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 437: Altremote_Update Megafunction
Remote System Upgrades With Stratix III Devices Quartus II Quartus II software provides the flexibility to include the remote system upgrade interface between the Stratix III device logic array and the Software dedicated circuitry, generate configuration files for productions, and remote programming of the system configuration memory.
Page 438: Conclusion
Conclusion Conclusion Stratix III devices offer remote system upgrade capability, where you can upgrade a system in real-time through any network. Remote system upgrade helps to deliver feature enhancements and bug fixes without costly recalls, reduces time to market, and extends product life cycles. The...
Page 439: Introduction
13. IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices SIII51013-1.3 Introduction As printed circuit boards (PCBs) become more complex, the need for thorough testing becomes increasingly important. Advances in surface-mount packaging and PCB manufacturing have resulted in smaller boards, making traditional test methods (such as, external test probes and “bed-of-nails”...
Page 440: Ieee Std. 1149.1 Bst Architecture
1 of the Stratix III Device Handbook. IEEE Std. 1149.1 A Stratix III device operating in IEEE Std. 1149.1 BST mode uses four required pins, TDI, TDO, TMS, and TCK, and one optional pin, TRST. The BST Architecture TCK pin has an internal weak pull-down resistor, while the TDI, TMS, and TRST pins have weak internal pull-ups.
Page 441 IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Table 13–1. IEEE Std. 1149.1 Pin Descriptions (Part 2 of 2) Description Function Test mode select Input pin that provides the control signal to determine the transitions of the test access port (TAP) controller state machine. Transitions within the state machine occur at the rising edge of .
Page 442: Ieee Std. 1149.1 Boundary-Scan Register
Note to Figure 13–2: For register lengths, see the device data sheet in the Configuring Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook. IEEE Std. 1149.1 boundary-scan testing is controlled by a test access port (TAP) controller.
Page 443 IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Refer to the Configuring Stratix III Devices chapter in volume 1 of the Stratix III Device Handbook for the Stratix III family device boundary-scan register lengths. Figure 13–3 shows how test data is serially shifted around the periphery of the IEEE Std.
Page 444: Boundary-Scan Cells Of A Stratix Iii Device I/O Pin
2970 Boundary-Scan Cells of a Stratix III Device I/O Pin The Stratix III device three-bit boundary-scan cell (BSC) consists of a set of capture registers and a set of update registers. The capture registers can connect to internal device data via the OUTJ, OEJ, and PIN_IN signals, while the update registers connect to external data through the PIN_OUT, and PIN_OE signals.
Page 445 IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Figure 13–4 shows the Stratix III device's user I/O boundary-scan cell. Figure 13–4. Stratix III Device's User I/O BSC with IEEE Std. 1149.1 BST Circuitry Capture Update Registers Registers PIN_IN INPUT...
Page 446 IEEE Std. 1149.1 Boundary-Scan Register Table 13–3 describes the capture and update register capabilities of all boundary-scan cells within Stratix III devices. Table 13–3. Stratix III Device Boundary Scan Cell Descriptions Note (1) Captures Drives Output Input Output Input Pin Type...
Page 447 I/O pins to a state defined by the data in the boundary-scan register. — Used when configuring a Stratix III device via the JTAG port with a ICR instructions USB Blaster™, ByteBlaster™ II, MasterBlaster™ or ByteBlasterMV™...
Page 448: Ieee Std. 1149.1 Bst Operation Control
IDCODE as the initial instruction. At device power-up, the TAP controller starts in this TEST_LOGIC/RESET state. In addition, forcing the TAP controller to the TEST_LOGIC/RESET state is 13–10 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 449 IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices done by holding TMS high for five TCK clock cycles, or by holding the TRST pin low. Once in the TEST_LOGIC/RESET state, the TAP controller remains in this state as long as TMS is held high (while TCK is clocked) or TRST is held low.
Page 450: Sample/Preload Instruction Mode
EXTEST instruction. Figure 13–8 shows the capture, shift, and update phases of the SAMPLE/PRELOAD mode. 13–12 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 451 IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Figure 13–8. IEEE Std. 1149.1 BST SAMPLE/PRELOAD Mode PIN_IN Capture Phase In the capture phase, the signals at the pin, OEJ and OUTJ, are loaded into the capture registers. The CLOCK signals are supplied by the TAP controller's CLOCKDR output.
Page 452: Extest Instruction Mode
EXTEST allows test data to be forced onto the pin signals. By forcing known logic high and low levels on output pins, you can detect opens and shorts at pins of any device in the scan chain. 13–14 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 453 IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Figure 13–10 shows the capture, shift, and update phases of the EXTEST mode. Figure 13–10. IEEE Std. 1149.1 BST EXTEST Mode PIN_IN Capture Phase In the capture phase, the signals at the pin, OEJ and OUTJ, are loaded into the capture registers.
Page 454: Bypass Instruction Mode
TAP controller is in the SHIFT_DR state. In this state, data signals are clocked into the bypass register from TDI on the rising edge of TCK and out of TDO on the falling edge of the same clock pulse. 13–16 Altera Corporation Stratix III Device Handbook, Volume 1 November 2007...
Page 455: Idcode Instruction Mode
IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices Figure 13–12. BYPASS Shift Data Register Waveforms Bit 1 Bit 2 Bit 3 Bit 1 Bit 2 Bit 4 SHIFT_IR SHIFT_DR TAP_STATE EXIT1_DR EXIT1_IR SELECT_DR_SCAN Data shifted into TDI on the rising edge of TCK is...
Page 456: Usercode Instruction Mode
TDO pin must meet the specifications of the Chain TDI pin it drives. The TDI of one Stratix III device connected in a chain to the TDO pins of another Stratix III device are powered by the V CCPD (2.5 V / 3.0 V) supply of I/O Bank 1A.
Page 457 IEEE 1149.1 (JTAG) Boundary-Scan Testing in Stratix III Devices I/O standards, you should connect V to 3.0 V; for 2.5 V and below CCPD I/O standards, you should connect V to 2.5 V. Table 13–6 shows CCPD board design recommendations to ensure proper JTAG chain operation.
Page 458: Ieee Std. 1149.1 Bst Circuitry
IEEE Std. 1149.1 Stratix III devices have dedicated JTAG pins and the IEEE Std. 1149.1 BST circuitry is enabled upon device power-up. Not only can you perform BST Circuitry BST on Stratix III FPGAs before and after, but also during configuration.
Page 459: Ieee Std. 1149.1 Bst For Configured Devices
Language (BSDL) Support” on page 13–23. IEEE Std. 1149.1 The IEEE Std. 1149.1 BST circuitry for Stratix III devices is enabled upon device power-up. Because the IEEE Std. 1149.1 BST circuitry is used for BST Circuitry BST or in-circuit reconfiguration, you must enable the circuitry only at specific times as mentioned in, “IEEE Std.
Page 460: Ieee Std. 1149.1 Bst Guidelines
Leave open TRST Note to Table 13–7: There is no software option to disable JTAG in Stratix III devices. The JTAG pins are dedicated. IEEE Std. 1149.1 Use the following guidelines when performing boundary-scan testing with IEEE Std. 1149.1 devices: BST Guidelines ■...
Page 461: Boundary-Scan Description Language (Bsdl) Support
Stratix III devices and the BSDLCustomizer script, visit the Altera web site at www.altera.com. Conclusion The IEEE Std. 1149.1 BST circuitry available in Stratix III devices provides a cost-effective and efficient way to test systems that contain devices with tight lead spacing. Circuit boards with Altera and other IEEE Std.
Page 462 Maunder, C. M., and R. E. Tulloss. The Test Access Port and Boundary- Scan Architecture. Los Alamitos: IEEE Computer Society Press, 1990. ■ Remote System Upgrades with Stratix III Devices chapter of volume 1 of the Stratix III Device Handbook Document Table 13–8...
Page 463 ® Upset (SEU) Mitigation in Stratix III devices. ■ Chapter 14, Design Security in Stratix III Devices ■ Chapter 15, SEU Mitigation in Stratix III Devices Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
Page 464: Section Iv. Design Security & Single Event Upset (Seu) Mitigation
Design Security & Single Event Upset (SEU) Mitigation Stratix III Device Handbook, Volume 1 Section IV–2 Altera Corporation...
Page 465: Chapter 14. Design Security In Stratix Iii Devices
(AES) as well as the security modes available in Stratix III devices for designers to utilize this new feature in their designs. As Stratix III devices start to play a role in larger and more critical designs in competitive commercial and military environments, it is increasingly important to protect the designs from copying, reverse engineering, and tampering.
Page 466: Stratix Iii Security Protection
Security Protection Security Against Copying The security key is securely stored in the Stratix III device and cannot be read out through any interfaces. In addition, as configuration file read-back is not supported in Stratix III devices, the design information cannot be copied.
Page 467: Aes Decryption Block
Table 14–1: Key programming is carried out via JTAG interface. The non-volatile key can be programmed to the Stratix III device without an external battery. Also, there are no additional requirements to any of the Stratix III power supply inputs.
Page 468: Stratix Iii Design Security Solution
Figure 14–1: Program the security key into the Stratix III device. Program the user-defined 256-bit AES keys to the Stratix III device through the JTAG interface. Encrypt the configuration file and store it in the external memory. Encrypt the configuration file with the same 256-bit keys used to program the Stratix III device.
Page 469: Security Modes Available
Step 1, Step 2, and Step 3 correspond to the procedure detailed in the “Stratix III Design Security Solution” section. Security Modes There are several security modes available on the Stratix III device, which are as follows: Available Volatile Key Secure Operation with volatile key programmed and required external battery: this mode accepts both encrypted and unencrypted configuration bitstreams.
Page 470: Supported Configuration Schemes
In the No key operation, only unencrypted configuration file is supported. The tamper protection bit setting does not prevent the device from being reconfigured. Supported The Stratix III device supports only selected configuration schemes, depending on the security mode you select when you encrypt the Configuration Stratix III device.
Page 471 Design Security in Stratix III Devices Figure 14–2. Stratix III Security Modes - Sequence and Restrictions No Key Volatile Key Unencrypted Non-Volatile Key Configuration File Unencrypted or Unencrypted or Encrypted Encrypted Configuration File Configuration File Non-Volatile Key with Tamper-Protection Bit Set...
Page 472 You can use the design security feature with other configuration features, such as compression and remote system upgrade features. When you use compression with the design security feature, the configuration file is first 14–8 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 473: Conclusion
Design Security in Stratix III Devices compressed and then encrypted using the Quartus II software. During configuration, the Stratix III device first decrypts and then decompresses the configuration file. Conclusion The need for design security is increasing as devices move from glue logic to implementing critical system functions.
Page 474 Document Revision History 14–10 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 475: Chapter 15. Seu Mitigation In Stratix Iii Devices
SEUs continuously and automatically. This section describes how to activate and use the error detection CRC feature when your Stratix III device is in user mode and describes how to recover from configuration errors caused by CRC errors. For Stratix III devices, use of the error detection CRC feature is ®...
Page 476: Configuration Error Detection
If the two checksum values are equal, the received data frame is correct and no data corruption occurred during transmission or storage. The error detection CRC feature uses the same concept. When Stratix III devices have been configured successfully and are in user mode, the error detection CRC feature ensures the integrity of the configuration data.
Page 477 This causes the CRC engine to start searching the error bit location. The error detection in Stratix III devices calculates CRC check bits for each frame and will pull the CRC_ERROR pin high when it detects bit errors in the chip.
Page 478 EDERROR_INJECT is provided. This instruction is able to change the content of the 21-bit JTAG fault injection register, used for error injection in Stratix III devices, hence enabling the testing of the error detection block. You can only execute the EDERROR_INJECT JTAG instruction when the device is in user mode.
Page 479 Use the JTAG fault injection register with EDERROR_INJECT instruction to flip the readback bits. The Stratix III device is then forced into error test mode. The content of the JTAG fault injection register is not loaded into the fault injection register during the processing of the last and the first frame.
Page 480: Automated Single Event Upset Detection
SEU. You can implement the error detection CRC feature with existing circuitry in Stratix III devices, eliminating the need for external logic. The CRC_ERROR pin reports a soft error when configuration CRAM data is corrupted, and you would have to decide whether to reconfigure the device or to ignore the error.
Page 481: Error Detection Pin Description
SEU Mitigation in Stratix III Devices Figure 15–1. Critical Error Detection Implementation Block Diagram Stratix III FPGA CRC Checker CRC_ERROR (Hard Logic) CRITICAL ERROR Memory Access Sensitivity Serial / Parallel Logic Processor Flash (Soft IP) (User Designed) This reference design will be supported in future versions of the Quartus II software.
Page 482: Critical Error Pin
Device Pin-Outs on the Literature page of the Altera website (www.altera.com) in the later revision. Error Detection You can enable the Stratix III device error detection block in the Quartus II software (refer to “Software Support” on page 15–12).
Page 483: Error Detection Registers
During configuration, after a frame of data is loaded into the ● Stratix III device, the precomputed CRC is shifted into the CRC circuitry. At the same time, the CRC value for the data frame shifted-in is ●...
Page 484 SHIFT_EDERROR_REG User Shift Register This register is accessible by the core logic and allows the contents of the User Update Register to be sampled and read by user logic. 15–10 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 485: Error Detection Timing
SEU Mitigation in Stratix III Devices Table 15–5. Error Detection Registers (Part 2 of 2) Register Description JTAG Fault Injection This 21-bit register is fully controlled by the JTAG Register instruction . This register holds EDERROR_INJECT the information of the error injection that you want in the bitstream.
Page 486: Software Support
Options dialog box in the Quartus II software. Enable the error detection feature using CRC by performing the following steps: Open the Quartus II software and load a project using a Stratix III device. On the Assignments menu, click Settings. The Settings dialog box is shown.
Page 487 SEU Mitigation in Stratix III Devices In the Device and Pin Options dialog box, click the Error Detection CRC tab. Turn on Enable error detection CRC (Figure 15–3). Figure 15–3. Enabling the Error Detection CRC Feature in the Quartus II...
Page 488: Recovering From Crc Errors
The purpose of the error detection CRC feature is to detect a flip in any of the configuration CRAM bits in Stratix III devices due to a soft error. By using the error detection circuitry, you can continuously verify the integrity of the configuration CRAM bits.
Page 489: Section V. Power And Thermal Management
III devices. ■ Chapter 16, Programmable Power and Temperature Sensing Diode in Stratix III Devices Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
Page 490 Power and Thermal Management Stratix III Device Handbook, Volume 1 Section V–2 Altera Corporation Preliminary...
Page 491: Introduction
Power consumption also affects thermal management. Stratix III offers a temperature sensing diode (TSD), which can self-monitor the device junction temperature and be used with external circuitry for activities such as controlling air flow to the FPGA.
Page 492: Stratix Iii Power Technology
V to the voltage level that you set in the Quartus II software. The Stratix III device cannot distinguish which core voltage level is used on the board. Connecting to the wrong voltage level will give you different timing delays and power consumption than what is reported by the Quartus II software.
Page 493: Programmable Power Technology
Programmable Power and Temperature Sensing Diode in Stratix III Devices Programmable Power Technology In addition to the ability to change the core voltage, Stratix III also offers the ability to configure portions of the core, called tiles, for high-speed or low-power mode of operation performed by the Quartus II software without user intervention.
Page 494: Relationship Between Selectable Core Voltage And Programmable Power Technology
Relationship Between Selectable Core Voltage and Programmable Power Technology Table 16–1 shows available Stratix III programmable power capabilities. Speed grade considerations can add to the permutations to give you flexibility in designing your system. Table 16–1. Stratix III Programmable Power Capabilities...
Page 495 Table 16–2 lists the external power supply pins External for Stratix III devices. Some of the power supply pins can be supplied with the same external power supply, provided they need the same Power Supply voltage level, as noted in the recommended board connection column.
Page 496: Temperature Sensing Diode
When V = 0.9 V, a separate voltage regulator is needed. Temperature The Stratix III TSD uses the characteristics of a PN junction diode to determine die temperature. Knowing the junction temperature is crucial Sensing Diode for thermal management. Historically, junction temperature is calculated using ambient or case temperature, junction-to-ambient (θ...
Page 497: External Pin Connections
Programmable Power and Temperature Sensing Diode in Stratix III Devices External Pin Connections The Stratix III TSD, located in the top right corner of the die, requires two pins for voltage reference. When both TSD and analog to digital converter are used, connect the TEMPDIODEP pin to an external resistor and connect the TEMPDIODEN pin to ground.
Page 498: Document Revision History
Added new section “Referenced Documents”. ● Added live links for references. May 2007 v1.1 ● Replaced all instances of VCCR with VCCPT Minor update. November 2006 Initial Release. — v1.0 16–8 Altera Corporation Stratix III Device Handbook, Volume 1 October 2007...
Page 499: Section Vi. Packaging Information
This section provides packaging information for the Stratix III device. ■ Chapter 17, Stratix III Device Packaging Information Revision History Refer to each chapter for its own specific revision history. For information on when each chapter was updated, refer to the Chapter Revision Dates section, which appears in the full handbook.
Page 500 Packaging Information Stratix III Device Handbook, Volume 1 Section VI–2 Altera Corporation Preliminary...
Page 501: Chapter 17. Stratix Iii Device Packaging Information
Package outlines Tables 17–1 shows which Stratix III devices, respectively, are available in ® FineLine BGA (FBGA) packages. Table 17–1. Stratix III Devices in FBGA Packages (Part 1 of 2) Device Package Pins EP3SL50 FineLine BGA - Flip Chip FineLine BGA - Flip Chip...
Page 502: Thermal Resistance
Thermal Resistance Table 17–1. Stratix III Devices in FBGA Packages (Part 2 of 2) Device Package Pins EP3SE260 Hybrid FineLine BGA - Flip Chip FineLine BGA - Flip Chip 1152 FineLine BGA - Flip Chip 1517 Thermal For thermal resistance specifications for Stratix III devices, refer to the Stratix Series Device Thermal Resistance Data Sheet.
Page 503 Stratix III Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIII5V2-1.5...
Page 504 Altera Corporation in the U.S. and other countries. All other product or service names are the property of their respective holders. Al- tera products are protected under numerous U.S.
Page 505 About this Handbook ................vii How to Contact Altera ........................... vii Typographic Conventions ........................vii Section I. DC & Switching Characteristics of Stratix III Devices Chapter 1. Stratix III Device Datasheet: DC and Switching Characteristics Electrical Characteristics ........................1–1 Operating Conditions ........................1–1 Power Consumption ........................
Page 506 Contents Stratix III Device Handbook, Volume 2 Altera Corporation...
Page 507: Chapter Revision Dates
Chapter Revision Dates The chapter in this book, Stratix III Device Handbook, Volume 2, was revised on the following dates. Where chapters or groups of chapters are available separately, part numbers are listed. Chapter 1. Stratix III Device Datasheet: DC and Switching Characteristics...
Page 508 Chapter Revision Dates Stratix III Device Handbook, Volume 2 Altera Corporation...
Page 509: About This Handbook
Email nacomp@altera.com Email authorization@altera.com (Software Licensing) Note to Table You can also contact your local Altera sales office or sales representative. Typographic This document uses the typographic conventions shown below. Conventions Visual Cue Meaning Bold Type with Initial Command names, dialog box titles, checkbox options, and dialog box options are Capital Letters shown in bold, initial capital letters.
Page 510 Typographic Conventions Stratix III Device Handbook, Volume 2 Visual Cue Meaning Italic type Internal timing parameters and variables are shown in italic type. Examples: t , n + 1. Variable names are enclosed in angle brackets (< >) and shown in italic type.
Page 511: Section I. Dc & Switching Characteristics Of Stratix Iii Devices
When Stratix® III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Stratix III devices, system designers must consider the operating requirements discussed in the following chapter: ■...
Page 512 DC & Switching Characteristics of Stratix III Devices Stratix III Device Handbook, Volume 2 Section I–2 Altera Corporation...
Page 513: Chapter 1. Stratix Iii Device Datasheet: Dc And Switching Characteristics
Absolute Maximum Ratings Absolute maximum ratings define the maximum operating conditions for Stratix III devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functional operation of the device is not implied at these conditions.
Page 514 Electrical Characteristics Table 1–1. Stratix III Device Absolute Maximum Ratings Note (1) (Part 2 of 2) Symbol Parameter Minimum Maximum Unit DC output current, per pin Storage temperature (No bias) °C Note to Table 1–1: Supply voltage specifications apply to voltage readings taken at the device pins, not the power supply.
Page 515 In the example shown in Figure 1–1, the overshoot voltage is shown in red and is present at the Stratix III pin, up to 4.1 V. From Table 1–2, for an overshoot of up to 4.1 V, the percentage of high time for overshoot >...
Page 516 . Maximum allowed ripple on power supplies is bounded by the RAMP minimum and maximum specifications listed in Table 1–3. Table 1–3. Stratix III Device Recommended Operating Conditions (Part 1 of 2) Symbol Parameter Conditions Minimum Typical...
Page 517 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–3. Stratix III Device Recommended Operating Conditions (Part 2 of 2) Symbol Parameter Conditions Minimum Typical Maximum Unit Operating junction temperature For commercial — °C For industrial use — °C Power Supply Ramptime Normal POR 100 µs...
Page 518 If OCT calibration is enabled, calibration is automatically performed at power-up for I/Os connected to the calibration block. Table 1–6 lists the Stratix III OCT calibration block accuracy specifications. Table 1–6. Stratix III On-Chip Termination Calibration Accuracy Specifications (Part 1 of 2) Note (1) - Preliminary Unit Calibration Accuracy...
Page 519 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–6. Stratix III On-Chip Termination Calibration Accuracy Specifications (Part 2 of 2) Note (1) - Preliminary Unit Calibration Accuracy Symbol Description Conditions Commercial Industrial 50-Ω R Internal parallel termination with = 1.2 V ±10...
Page 520 +/- 5% and temperature range of 0 to 85 CCIO Pin Capacitance Table 1–9 shows the Stratix III device family pin capacitance. Table 1–9. Stratix III Device Capacitance (Part 1 of 2) Note (1) Preliminary Symbol Parameter Typical...
Page 521 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–9. Stratix III Device Capacitance (Part 2 of 2) Note (1) Preliminary Symbol Parameter Typical Unit Input capacitance on left/right dedicated CLKLR clock input pins Input capacitance on dual-purpose OUTFB clock output/feedback pins...
Page 522 0.5 * V 0.53 * V 0.47 * V 0.53 * V CCIO CCIO CCIO CCIO CCIO CLASS I, II HSTL-18 1.71 1.89 0.85 0.95 — — CCIO CLASS I, II 1–10 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 523 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–12. Single-Ended SSTL and HSTL I/O Reference Voltage Specifications (Part 2 of 2) CCIO Standard HSTL-15 1.425 1.575 0.68 0.75 — — CCIO CLASS I, II HSTL-12 1.14 1.26 0.47 * V 0.5 * V...
Page 524 — 0.05 0.247 — 1.125 1.25 1.375 (Row I/O) Mbps 2.375 2.5 2.625 100 = 1.25 V — 1.05 > 700 — — — — — — 1.55 Mbps 1–12 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 525: Power Consumption
700 Mbps, the minimum input voltage is 0.45 V, the maximum input voltage is 1.95 V. Power supply for column I/O LVPECL differential clock input buffer is V CC_CLKIN. Power Consumption Altera offers two ways to estimate power for a design: the Excel-based ® Early Power Estimator and the Quartus II PowerPlay Power Analyzer feature.
Page 526: Switching Characteristics
Configuration and JTAG Specifications. Clock Tree Specifications Table 1–17 lists the clock tree performance specifications for the logic array, DSP blocks, and TriMatrix Memory blocks for Stratix III devices. Table 1–17. Stratix III Clock Tree Performance (Part 1 of 2) Preliminary -2 Speed...
Page 527 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–17. Stratix III Clock Tree Performance (Part 2 of 2) Preliminary -2 Speed -3 Speed -4 Speed -4L Speed Unit Grade Grade Grade Grade Device = 1.1V = 1.1V = 1.1V = 1.1V...
Page 528 PLL. Pending silicon characterization. DSP Block Specifications Table 1–19 describes the Stratix III DSP block performance specifications. Table 1–19. Stratix III DSP Block Performance Specifications (Part 1 of 2)Note (1) (Part 1 of 2) Preliminary -2 Speed -3 Speed...
Page 529 Maximum for non-pipelined block with loopback input registers disabled and Round and Saturation disabled. TriMatrix Memory Block Specifications Table 1–20 describes the Stratix III TriMatrix Memory Block specifications. Table 1–20. Stratix III TriMatrix Memory Block Performance Specifications (Part 1 of 2) Preliminary -2 Speed -3 Speed -4 Speed...
Page 530 Switching Characteristics Table 1–20. Stratix III TriMatrix Memory Block Performance Specifications (Part 2 of 2) Preliminary -2 Speed -3 Speed -4 Speed -4L Speed Memory TriMatrix Grade Grade Grade Grade Mode ALUTs Unit Block Type Memory = 1.1V V = 1.1V = 1.1V...
Page 531 JTAG timing parameters and values for Stratix III devices. Refer to figure for “HIGH-SPEED I/O Block” in Table 1–206 JTAG timing requirements. Table 1–22. Stratix III JTAG Timing Parameters and Values - Preliminary Symbol Parameter Unit TCK clock period —...
Page 532: Periphery Performance
Refer to the Table 1–206 for definitions of high-speed timing specifications. Table 1–24 shows the high-speed I/O timing for Stratix III devices. Table 1–24. High Speed I/O Specifications for -2 Speed Grade Notes (1), (2), - Preliminary -2 Speed Grade...
Page 533 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–24. High Speed I/O Specifications for -2 Speed Grade Notes (1), (2), - Preliminary -2 Speed Grade Symbol Conditions Unit DPA jitter tolerance Data channel peak-to-peak jitter tolerance — — Notes to Table 1–24:...
Page 534 DDR3/DDR2 SDRAM interfaces above 333 MHz requires the use of the deskew circuitry pending characterization. Support will be evaluated after characterization. Stratix III FPGAs support QDRII+ devices with 2.5 cycle read latency. Stratix III FPGAs do not support QDRII+ devices with 2.0 cycle read latency.
Page 535 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–27. Stratix III Maximum Clock Rate Support for External Memory Interfaces with Full-Rate Controller Note (1), –2 Speed Grade –3 Speed Grade –4 Speed Grade -4L Speed Grade (MHz) (MHz) (MHz)
Page 536 (Part 1 of 2) - Preliminary Commercial TCCS (ps) Speed Location Memory Type Lead Grade DDR2 DDR2 DDR2 DDR3 DDR3 DDR3 DDR1 QDRII / II + QDRII / II + 1–24 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 537 RLDRAM II RLDRAM II DLL and DQS Logic Block Specifications Table 1–30 describes the DLL Frequency Range specifications for Stratix III devices. Table 1–30. Stratix III DLL Frequency Range Specifications - Preliminary Frequency Mode Frequency Range (MHz) Resolution (Degrees) 100-125 22.5...
Page 538 Switching Characteristics Table 1–31 describes the DQS Phase Offset Delay per stage for Stratix III devices. Table 1–31. DQS Phase Offset Delay per Stage Notes (1), (2), Preliminary Speed Grade Unit Notes to Table 1–31: The delay settings are linear.
Page 539: I/O Timing
— — RS_RT DCD Specifications Table 1–33 lists the worst case duty cycle distortion for Stratix III devices. Detailed information on duty cycle distortion will be published after characterization. Table 1–33. Duty Cycle Distortion on Stratix III I/O Pins Notes...
Page 540: Preliminary And Final Timing
When the timing models are final, all or most of the Stratix III family devices have been completely characterized and no further changes to the timing model are expected.
Page 541 (PVT) for default loading conditions shown in Table 1–35. The following equation describes clock pin to output pin timing for Stratix III devices. The t from clock pin to I/O pin = ■ + delay from clock pad to I/O output register ■...
Page 542 The Quartus II software reports the timing with the conditions shown in Table 1–35 using the above equation. Figure 1–4 shows the model of the circuit that is represented by the output timing of the Quartus II software. 1–30 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 543 Stratix III Device Datasheet: DC and Switching Characteristics Figure 1–4. Output Register Clock to Output Timing Diagram CCIO Output Output Output Buffer Output MEAS Notes to Figure 1–4: Output pin timing is reported at the output pin of the FPGA device. Additional delays for loading and board trace delay need to be accounted for with IBIS model simulations.
Page 544 — 1.1875 Notes: Hyper transport is not supported by Stratix III. LVPECL outputs are not supported by Stratix III. Quartus timing conditions can be changed using the Advanced I/O Timing feature. is nominally 1.1 v less 50 mV (1.05 v).
Page 545: I/O Default Capacitive Loading
Stratix III Device Datasheet: DC and Switching Characteristics I/O Default Capacitive Loading Table 1–36 for default capacitive loading of different I/O standards. Table 1–36. Default Loading of Different I/O Standards for Stratix III Capacitive I/O Standard Unit Load 3.3 V LVTTL 3.3 V LVCMOS...
Page 546: Maximum I/O Toggle Rate
0pF load for column I/O pins. Derating factors for maximum I/O toggle rates for non-0pF loads will be published after characterization. Table 1–37. Maximum Input Toggle Rate on Stratix III Devices for Column I/O Pins (Part 1 of 2) I/O Standard Units VCCL=1.1V...
Page 547 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–37. Maximum Input Toggle Rate on Stratix III Devices for Column I/O Pins (Part 2 of 2) I/O Standard Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V HSTL CLASS II DIFFERENTIAL 1.5-V...
Page 548 I/O Timing Table 1–38. Maximum Output Toggle Rate on Stratix III Devices for Column I/O Pins (Part 1 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting 3.3-V LVTTL 4 mA 8 mA 12 mA 16 mA 3.3-V LVCMOS...
Page 549 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–38. Maximum Output Toggle Rate on Stratix III Devices for Column I/O Pins (Part 2 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting 1.5 V...
Page 550 I/O Timing Table 1–38. Maximum Output Toggle Rate on Stratix III Devices for Column I/O Pins (Part 3 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting 1.8-V HSTL CLASS II 16 mA 1.5-V HSTL CLASS I...
Page 551 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–38. Maximum Output Toggle Rate on Stratix III Devices for Column I/O Pins (Part 4 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting DIFFERENTIAL 1.5-V...
Page 552 I/O Timing Table 1–38. Maximum Output Toggle Rate on Stratix III Devices for Column I/O Pins (Part 5 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting OCT 50 Ω 1.5 V 1111 OCT 50 Ω...
Page 553 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–38. Maximum Output Toggle Rate on Stratix III Devices for Column I/O Pins (Part 6 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting OCT 50 Ω...
Page 554 I/O Timing Table 1–39. Maximum Input Toggle Rate on Stratix III Devices for Row I/O Pins I/O Standard Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V HSTL CLASS II DIFFERENTIAL 1.5-V HSTL CLASS I DIFFERENTIAL 1.5-V HSTL CLASS II DIFFERENTIAL 1.8-V...
Page 555 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–40. Maximum Output Toggle Rate on Stratix III Devices for Row I/O Pins (Part 1 of 5) Current Strength I/O Standard Units or OCT VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V Setting 3.3-V LVTTL...
Page 556 I/O Timing Table 1–40. Maximum Output Toggle Rate on Stratix III Devices for Row I/O Pins (Part 2 of 5) Current Strength I/O Standard Units or OCT VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V Setting SSTL-18 CLASS I 4 mA 6 mA...
Page 557 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–40. Maximum Output Toggle Rate on Stratix III Devices for Row I/O Pins (Part 3 of 5) Current Strength I/O Standard Units or OCT VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V Setting DIFFERENTIAL 1.8-V...
Page 558 I/O Timing Table 1–40. Maximum Output Toggle Rate on Stratix III Devices for Row I/O Pins (Part 4 of 5) Current Strength I/O Standard Units or OCT VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V Setting OCT 50 Ω 3.3-V LVTTL OCT 50 Ω...
Page 559 Table 1–42 specifies the maximum output toggle rates at 0pF load for clock pins. Table 1–41. Maximum Input Toggle Rate on Stratix III Devices for Dedicated Clock Input Pins (Part 1 of 2) I/O Standard Units VCCL=1.1V VCCL=1.1V...
Page 560 I/O Timing Table 1–41. Maximum Input Toggle Rate on Stratix III Devices for Dedicated Clock Input Pins (Part 2 of 2) I/O Standard Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V 3.0-V PCI 3.0-V PCI-X DIFFERENTIAL LVPECL DIFFERENTIAL 1.2-V HSTL CLASS I DIFFERENTIAL 1.2-V...
Page 561 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–42. Maximum Output Toggle Rate on Stratix III Devices for Dedicated Clock Output Pins (Part 1 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting 3.3-V LVTTL...
Page 562 I/O Timing Table 1–42. Maximum Output Toggle Rate on Stratix III Devices for Dedicated Clock Output Pins (Part 2 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting 1.5 V 2 mA 4 mA...
Page 563 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–42. Maximum Output Toggle Rate on Stratix III Devices for Dedicated Clock Output Pins (Part 3 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting 1.8-V HSTL CLASS II...
Page 564 I/O Timing Table 1–42. Maximum Output Toggle Rate on Stratix III Devices for Dedicated Clock Output Pins (Part 4 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting DIFFERENTIAL 1.5-V 4 mA SSTL CLASS I...
Page 565 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–42. Maximum Output Toggle Rate on Stratix III Devices for Dedicated Clock Output Pins (Part 5 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting OCT 50 Ω...
Page 566: Programmable Ioe Delay
I/O Timing Table 1–42. Maximum Output Toggle Rate on Stratix III Devices for Dedicated Clock Output Pins (Part 6 of 6) Current I/O Standard Strength or Units VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=1.1V VCCL=0.9V OCT Setting OCT 50 Ω DIFFERENTIAL 2.5-V SSTL CLASS I OCT 25 Ω...
Page 567: User I/O Pin Timing
Stratix III Device Datasheet: DC and Switching Characteristics User I/O Pin Timing Table 1–45 through Table 1–144 show user I/O pin timing for Stratix III devices. I/O buffer t , and t are reported for the cases when I/O clock is driven by a non-PLL global clock (GCLK) and a PLL driven global clock (GCLK-PLL).
Page 568 -0.977 -1.153 -1.269 -1.213 -1.106 SSTL-18 CLASS II GCLK — -0.572 -0.736 -0.756 -0.819 -0.770 -1.080 GCLK — 0.593 1.124 1.320 1.451 1.386 1.274 — -0.482 -0.977 -1.153 -1.269 -1.213 -1.106 1–56 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 569 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–45. EP3SL50 Column Pins Input Timing Parameters (Part 3 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-15 CLASS I GCLK — -0.558 -0.709 -0.724 -0.786 -0.737 -1.048...
Page 570 — -0.682 -0.975 -1.040 -1.125 -1.007 -1.331 — 0.788 1.117 1.201 1.300 1.176 1.492 GCLK — 0.447 0.898 1.057 1.201 1.135 1.044 — -0.345 -0.755 -0.895 -1.022 -0.966 -0.882 1–58 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 571 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–46. EP3SL50 Row Pins Input Timing Parameters (Part 2 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 2.5 V GCLK — -0.687 -0.986 -1.052 -1.137 -1.019 -1.343 —...
Page 572 -0.630 -0.640 -0.718 -0.686 -0.930 CLASS II — 0.622 0.778 0.807 0.901 0.860 1.098 GCLK — 0.626 1.197 1.402 1.672 1.593 1.387 — -0.514 -1.049 -1.235 -1.484 -1.414 -1.219 1–60 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 573 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–46. EP3SL50 Row Pins Input Timing Parameters (Part 4 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2-V HSTL GCLK — -0.510 -0.630 -0.640 -0.718 -0.686 -0.930 CLASS I —...
Page 574 5.332 5.956 6.208 6.065 6.285 GCLK — 2.457 3.463 3.883 3.951 3.903 3.935 16mA GCLK — 3.698 5.452 6.101 6.353 6.210 6.430 GCLK — 2.529 3.583 4.028 4.096 4.048 4.080 1–62 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 575 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–47. EP3SL50 Column Pins Output Timing Parameters (Part 2 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.0-V LVTTL GCLK —...
Page 576 5.677 6.405 6.657 6.514 6.734 GCLK — 2.603 3.808 4.332 4.400 4.352 4.384 12mA GCLK — 3.664 5.484 6.172 6.424 6.281 6.501 GCLK — 2.495 3.615 4.099 4.167 4.119 4.151 1–64 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 577 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–47. EP3SL50 Column Pins Output Timing Parameters (Part 4 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.5 V GCLK —...
Page 578 4.408 4.922 5.171 5.032 5.252 GCLK — 1.815 2.539 2.849 2.914 2.870 2.902 16mA GCLK — 2.981 4.412 4.930 5.179 5.040 5.260 GCLK — 1.812 2.543 2.857 2.922 2.878 2.910 1–66 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 579 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–47. EP3SL50 Column Pins Output Timing Parameters (Part 6 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-15 CLASS I GCLK —...
Page 580 4.407 4.923 5.172 5.033 5.253 GCLK — 1.811 2.538 2.850 2.915 2.871 2.903 12mA GCLK — 2.978 4.412 4.931 5.180 5.041 5.261 GCLK — 1.809 2.543 2.858 2.923 2.879 2.911 1–68 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 581 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–47. EP3SL50 Column Pins Output Timing Parameters (Part 8 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.5-V HSTL 16mA GCLK —...
Page 582 5.362 5.995 6.272 6.115 6.293 LVCMOS GCLK — 2.490 3.531 3.958 4.021 3.983 3.978 GCLK — 3.617 5.318 5.949 6.226 6.069 6.247 GCLK — 2.476 3.487 3.912 3.975 3.937 3.932 1–70 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 583 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–48. EP3SL50 Row Pins Output Timing Parameters (Part 2 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 2.5 V GCLK —...
Page 584 4.378 4.887 5.151 5.044 5.177 GCLK — 1.820 2.551 2.855 2.885 2.862 2.876 12mA GCLK — 2.955 4.377 4.886 5.150 5.043 5.176 GCLK — 1.819 2.550 2.854 2.884 2.861 2.875 1–72 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 585 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–48. EP3SL50 Row Pins Output Timing Parameters (Part 4 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-18 GCLK — 2.969 4.378 4.883 5.148 5.040 5.174...
Page 586 4.424 4.919 5.194 5.045 5.215 GCLK — 1.926 2.593 2.877 2.937 2.903 2.898 Table 1–49 through Table 1–52 show the maximum I/O timing parameters for EP3SL50 devices for differential I/O standards. 1–74 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 587 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–49 specifies EP3SL50 Column Pins Input Timing parameters for differential I/O standards. Table 1–49. EP3SL50 Column Pins Input Timing Parameters (Part 1 of 2) Fast Model I/O Standard Clock Parameter Units...
Page 588 -0.769 -0.796 -0.882 -0.835 -1.120 2.5-V SSTL — 0.685 0.913 0.960 1.060 1.005 1.284 CLASS II GCLK — 0.566 1.068 1.253 1.382 1.321 1.205 — -0.457 -0.924 -1.089 -1.204 -1.151 -1.041 1–76 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 589 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–50 specifies EP3SL50 Row Pins Input Timing parameters for differential I/O standards. Table 1–50. EP3SL50 Row Pins Input Timing Parameters (Part 1 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V...
Page 590 -0.728 -0.752 -0.833 -0.791 -1.043 2.5-V SSTL — 0.667 0.872 0.916 1.011 0.961 1.207 CLASS I GCLK — 0.580 1.165 1.367 1.515 1.442 1.353 — -0.477 -1.020 -1.202 -1.332 -1.270 -1.188 1–78 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 591 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–50. EP3SL50 Row Pins Input Timing Parameters (Part 3 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -0.558 -0.728 -0.752 -0.833 -0.791 -1.043 2.5-V SSTL...
Page 592 2.511 2.833 2.921 2.873 2.885 CLASS I DIFFERENTIAL 16mA GCLK — 2.665 4.336 4.866 5.169 5.012 5.196 1.5-V HSTL GCLK — 1.510 2.486 2.804 2.891 2.843 2.856 CLASS II 1–80 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 593 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–51. EP3SL50 Column Pins Output Timing Parameters (Part 3 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.672 4.351 4.883 5.187 5.030 5.213...
Page 594 2.508 2.830 2.918 2.870 2.882 CLASS I DIFFERENTIAL 10mA GCLK — 2.675 4.356 4.889 5.193 5.036 5.219 2.5-V SSTL GCLK — 1.520 2.506 2.827 2.915 2.867 2.879 CLASS I 1–82 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 595 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–51. EP3SL50 Column Pins Output Timing Parameters (Part 5 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL 12mA GCLK —...
Page 596 1.513 2.488 2.807 2.890 2.846 2.827 CLASS I DIFFERENTIAL GCLK — 2.656 4.319 4.848 5.146 4.994 5.145 1.8-V HSTL GCLK — 1.507 2.477 2.794 2.877 2.833 2.814 CLASS I 1–84 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 597 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–52. EP3SL50 Row Pins Output Timing Parameters (Part 3 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.658 4.322 4.852 5.150 4.998 5.149...
Page 598 GCLK values. These adder values are used to determine I/O timing when I/O pin is driven using regional clock. This applies for all I/O standards supported by Stratix III. Table 1–53 specifies EP3SL50 Column Pin delay adders when using the Regional Clock.
Page 599 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–53. EP3SL50 Column Pin Delay Adders for Regional Clock Fast Model Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V RCLK output adder — -0.033 0.045 0.123 0.241 0.197 0.38 RCLK PLL output adder —...
Page 600 — -0.640 -0.894 -0.942 -1.030 -0.982 -1.267 — 0.749 1.036 1.104 1.206 1.151 1.429 GCLK — 0.506 0.945 1.110 1.237 1.177 1.062 — -0.397 -0.803 -0.948 -1.061 -1.008 -0.900 1–88 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 601 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–55. EP3SL70 Column Pins Input Timing Parameters (Part 3 of 4) Fast Model Clock Parameter Units Standard Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-2 GCLK — -0.580 -0.771 -0.799 -0.885 -0.838 -1.124 CLASS I —...
Page 602 -0.702 -1.018 -1.087 -1.177 -1.129 -1.412 LVTTL — 0.810 1.160 1.248 1.352 1.296 1.573 GCLK — 0.444 0.821 0.965 1.090 1.030 0.917 — -0.336 -0.679 -0.804 -0.915 -0.863 -0.756 1–90 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 603 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–56. EP3SL70 Row Pins Input Timing Parameters (Part 2 of 4) Fast Model Clock Parameter Units Standard Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V GCLK — -0.702 -1.018 -1.087 -1.177 -1.129 -1.412 LVCMOS —...
Page 604 1.317 1.448 1.386 1.270 HSTL — -0.482 -0.977 -1.150 -1.266 -1.213 -1.102 CLASS I GCLK — -0.539 -0.688 -0.703 -0.786 -0.740 -1.027 — 0.607 1.151 1.349 1.481 1.419 1.302 1–92 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 605 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–56. EP3SL70 Row Pins Input Timing Parameters (Part 4 of 4) Fast Model Clock Parameter Units Standard Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8-V GCLK — -0.495 -1.004 -1.182 -1.298 -1.245 -1.134 HSTL —...
Page 606 5.210 5.829 6.112 5.966 6.157 GCLK — 2.376 3.378 3.784 3.852 3.814 3.835 3.0-V LVTTL GCLK — 3.387 5.013 5.600 5.883 5.737 5.928 GCLK — 2.248 3.182 3.555 3.623 3.585 3.606 1–94 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 607 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–57. EP3SL70 Column Pins Output Timing Parameters (Part 2 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.0-V LVTTL 12mA GCLK —...
Page 608 5.605 6.326 6.609 6.463 6.654 GCLK — 2.579 3.773 4.281 4.349 4.311 4.332 1.5 V 12mA GCLK — 3.635 5.491 6.264 6.544 6.402 6.593 GCLK — 2.496 3.659 4.218 4.283 4.249 4.270 1–96 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 609 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–57. EP3SL70 Column Pins Output Timing Parameters (Part 4 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2 V GCLK —...
Page 610 4.377 4.892 5.172 5.030 5.221 GCLK — 1.811 2.545 2.847 2.912 2.878 2.899 SSTL-15 CLASS II 16mA GCLK — 2.948 4.380 4.898 5.178 5.036 5.227 GCLK — 1.809 2.548 2.853 2.918 2.884 2.905 1–98 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 611 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–57. EP3SL70 Column Pins Output Timing Parameters (Part 6 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8-V HSTL GCLK —...
Page 612 4.442 4.939 5.219 5.077 5.268 GCLK — 1.926 2.610 2.894 2.959 2.925 2.946 3.0-V PCI-X — GCLK — 3.065 4.442 4.939 5.219 5.077 5.268 GCLK — 1.926 2.610 2.894 2.959 2.925 2.946 1–100 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 613 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–58 specifies EP3SL70 Row Pins Output Timing parameters for single-ended I/O standards. Table 1–58. EP3SL70 Row Pins Output Timing Parameters (Part 1 of 5) Fast Model Current I/O Standard Clock Parameter...
Page 614 5.386 6.069 6.344 6.206 6.367 GCLK — 2.443 3.538 4.004 4.063 4.040 4.026 1.5 V GCLK — 3.503 5.249 5.899 6.177 6.035 6.196 GCLK — 2.350 3.401 3.834 3.896 3.869 3.855 1–102 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 615 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–58. EP3SL70 Row Pins Output Timing Parameters (Part 3 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2 V GCLK —...
Page 616 CLASS II GCLK — 1.807 2.518 2.812 2.871 2.848 2.834 1.5-V HSTL GCLK — 3.017 4.416 4.936 5.211 5.073 5.234 CLASS I GCLK — 1.864 2.568 2.871 2.930 2.907 2.893 1–104 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 617 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–58. EP3SL70 Row Pins Output Timing Parameters (Part 5 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.5-V HSTL GCLK —...
Page 618 -0.686 -0.700 -0.783 -0.737 -1.023 1.5-V SSTL — 0.647 0.833 0.867 0.966 0.911 1.191 CLASS I GCLK — 0.607 1.151 1.349 1.481 1.419 1.302 — -0.495 -1.004 -1.182 -1.298 -1.245 -1.134 1–106 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 619 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–59. EP3SL70 Column Pins Input Timing Parameters (Part 2 of 2) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -0.535 -0.686 -0.700 -0.783 -0.737 -1.023 1.5-V SSTL...
Page 620 -0.645 -0.656 -0.734 -0.693 -0.946 1.5-V HSTL — 0.629 0.792 0.823 0.917 0.867 1.114 CLASS II GCLK — 0.641 1.288 1.512 1.658 1.586 1.496 — -0.535 -1.137 -1.339 -1.470 -1.407 -1.325 1–108 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 621 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–60. EP3SL70 Row Pins Input Timing Parameters (Part 2 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -0.531 -0.672 -0.688 -0.767 -0.726 -0.978 1.8-V HSTL...
Page 622 GCLK — 1.603 2.675 3.025 3.115 3.066 3.077 DIFFERENTIAL GCLK — 2.690 4.386 4.925 5.229 5.072 5.255 1.2-V HSTL GCLK — 1.535 2.536 2.863 2.951 2.903 2.915 CLASS I 1–110 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 623 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–61. EP3SL70 Column Pins Output Timing Parameters (Part 2 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.682 4.371 4.907 5.211 5.054 5.237...
Page 624 2.521 2.845 2.933 2.885 2.897 CLASS I DIFFERENTIAL 12mA GCLK — 2.680 4.367 4.902 5.206 5.049 5.232 1.5-V SSTL GCLK — 1.525 2.517 2.840 2.928 2.880 2.892 CLASS I 1–112 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 625 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–61. EP3SL70 Column Pins Output Timing Parameters (Part 4 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.672 4.350 4.882 5.186 5.029 5.212...
Page 626 4.483 5.040 5.340 5.187 5.337 LVDS_E_1R GCLK — 1.588 2.641 2.986 3.071 3.026 3.006 MINI- — GCLK — 2.737 4.483 5.040 5.340 5.187 5.337 LVDS_E_3R GCLK — 1.588 2.641 2.986 3.071 3.026 3.006 1–114 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 627 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–62. EP3SL70 Row Pins Output Timing Parameters (Part 2 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V RSDS — GCLK —...
Page 628 2.499 2.820 2.903 2.859 2.840 CLASS I DIFFERENTIAL 10mA GCLK — 2.666 4.339 4.872 5.170 5.018 5.169 1.8-V SSTL GCLK — 1.517 2.497 2.818 2.901 2.857 2.838 CLASS I 1–116 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 629 GCLK values. These adder values are used to determine I/O timing when I/O pin is driven using regional clock. This applies for all I/O standards supported by Stratix III devices. Table 1–63 specifies EP3SL70 Column Pin delay adders when using the Regional Clock.
Page 630 -0.928 -1.360 -1.452 -1.601 -1.542 -1.910 LVTTL — 1.036 1.502 1.613 1.776 1.709 2.071 GCLK — 0.444 0.838 0.986 1.135 1.071 0.977 — -0.336 -0.696 -0.825 -0.960 -0.904 -0.816 1–118 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 631 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–65. EP3SL110 Column Pins Input Timing Parameters (Part 2 of 4) Fast Model Clock Parameter Units Standard Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V GCLK — -0.928 -1.360 -1.452 -1.601 -1.542 -1.910 LVCMOS —...
Page 632 -0.994 -1.171 -1.311 -1.254 -1.162 1.5-V GCLK — -0.765 -1.030 -1.068 -1.210 -1.153 -1.525 HSTL GCLK — 0.607 1.168 1.370 1.526 1.460 1.362 CLASS I — -0.495 -1.021 -1.203 -1.343 -1.286 -1.194 1–120 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 633 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–65. EP3SL110 Column Pins Input Timing Parameters (Part 4 of 4) Fast Model Clock Parameter Units Standard Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.5-V GCLK — -0.765 -1.030 -1.068 -1.210 -1.153 -1.525...
Page 634 — -0.871 -1.160 -1.213 -1.316 -1.241 -1.619 — 0.973 1.304 1.376 1.497 1.412 1.782 GCLK — 0.525 1.062 1.247 1.448 1.336 1.299 — -0.423 -0.918 -1.084 -1.267 -1.165 -1.136 1–122 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 635 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–66. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 4) Fast Model Clock Parameter Units Standard Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-2 GCLK — -0.789 -1.012 -1.037 -1.165 -1.091 -1.470 CLASS I —...
Page 636 -0.915 -1.268 -1.335 -1.467 -1.391 -1.768 PCI-X — 1.017 1.411 1.497 1.646 1.560 1.930 GCLK — 0.462 0.934 1.098 1.294 1.186 1.140 — -0.360 -0.791 -0.936 -1.115 -1.017 -0.978 1–124 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 637 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–67 specifies EP3SL110 Column Pins Output Timing parameters for single-ended I/O standards. Table 1–67. EP3SL110 Column Pins Output Timing Parameters (Part 1 of 7) Fast Model Current I/O Standard Clock Parameter...
Page 638 5.819 6.544 6.834 6.678 6.954 GCLK — 2.456 3.572 4.057 4.138 4.102 4.105 1.8 V GCLK — 4.008 6.065 6.812 7.102 6.946 7.222 GCLK — 2.587 3.818 4.325 4.406 4.370 4.373 1–126 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 639 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–67. EP3SL110 Column Pins Output Timing Parameters (Part 3 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8 V GCLK —...
Page 640 4.755 5.297 5.584 5.432 5.708 GCLK — 1.792 2.508 2.810 2.888 2.856 2.859 SSTL-18 CLASS I GCLK — 3.197 4.743 5.285 5.572 5.420 5.696 GCLK — 1.776 2.496 2.798 2.876 2.844 2.847 1–128 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 641 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–67. EP3SL110 Column Pins Output Timing Parameters (Part 5 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-18 CLASS I 10mA GCLK —...
Page 642 GCLK — 1.767 2.481 2.781 2.859 2.827 2.830 1.5-V HSTL 12mA GCLK — 3.186 4.733 5.276 5.563 5.411 5.687 CLASS I GCLK — 1.765 2.486 2.789 2.867 2.835 2.838 1–130 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 643 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–67. EP3SL110 Column Pins Output Timing Parameters (Part 7 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.5-V HSTL 16mA GCLK —...
Page 644 5.667 6.212 6.609 6.467 6.710 GCLK — 2.360 3.343 3.749 3.876 3.882 3.826 3.0-V LVCMOS GCLK — 3.808 5.623 6.181 6.563 6.421 6.664 GCLK — 2.359 3.316 3.718 3.830 3.836 3.780 1–132 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 645 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–68. EP3SL110 Row Pins Output Timing Parameters (Part 2 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 2.5 V GCLK —...
Page 646 4.686 5.225 5.519 5.373 5.620 GCLK — 1.759 2.462 2.762 2.788 2.765 2.739 SSTL-18 CLASS II GCLK — 3.168 4.687 5.223 5.517 5.371 5.618 GCLK — 1.770 2.463 2.760 2.785 2.762 2.736 1–134 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 647 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–68. EP3SL110 Row Pins Output Timing Parameters (Part 4 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-18 CLASS II 16mA GCLK —...
Page 648 4.750 5.269 5.551 5.387 5.664 GCLK — 1.880 2.526 2.806 2.824 2.802 2.782 Table 1–69 through Table 1–74 show the maximum I/O timing parameters for EP3SL110 devices for differential I/O standards. 1–136 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 649 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–69 specifies EP3SL110 Column Pins Input Timing parameters for differential I/O standards. Table 1–69. EP3SL110 Column Pins Input Timing Parameters (Part 1 of 2) Fast Model I/O Standard Clock Parameter Units...
Page 650 -1.141 -1.193 -1.302 -1.244 -1.614 SSTL CLASS II — 0.944 1.285 1.357 1.480 1.414 1.778 GCLK — 0.606 1.125 1.314 1.450 1.387 1.289 — -0.497 -0.981 -1.150 -1.272 -1.217 -1.125 1–138 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 651 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–70 specifies EP3SL110 Row Pins Input Timing parameters for differential I/O standards. Table 1–70. EP3SL110 Row Pins Input Timing Parameters (Part 1 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V...
Page 652 -1.053 -1.100 -1.199 -1.147 -1.491 SSTL CLASS I — 0.877 1.197 1.264 1.377 1.317 1.655 GCLK — 0.623 1.225 1.432 1.593 1.514 1.440 — -0.520 -1.080 -1.267 -1.410 -1.342 -1.275 1–140 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 653 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–70. EP3SL110 Row Pins Input Timing Parameters (Part 3 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL 2.5-V GCLK — -0.770 -1.053 -1.100 -1.199 -1.147 -1.491 SSTL CLASS II —...
Page 654 2.454 2.773 2.852 2.810 2.801 CLASS I DIFFERENTIAL 16mA GCLK — 2.887 4.661 5.217 5.541 5.374 5.639 1.5-V HSTL GCLK — 1.471 2.429 2.744 2.822 2.780 2.772 CLASS II 1–142 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 655 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–71. EP3SL110 Column Pins Output Timing Parameters (Part 3 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.894 4.676 5.234 5.559 5.392 5.656...
Page 656 2.451 2.770 2.849 2.807 2.798 CLASS I DIFFERENTIAL 10mA GCLK — 2.897 4.681 5.240 5.565 5.398 5.662 2.5-V SSTL GCLK — 1.481 2.449 2.767 2.846 2.804 2.795 CLASS I 1–144 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 657 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–71. EP3SL110 Column Pins Output Timing Parameters (Part 5 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL 12mA GCLK —...
Page 658 1.441 2.397 2.713 2.784 2.746 2.710 CLASS I DIFFERENTIAL GCLK — 2.856 4.633 5.187 5.503 5.343 5.584 1.8-V HSTL GCLK — 1.435 2.386 2.700 2.771 2.733 2.697 CLASS I 1–146 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 659 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–72. EP3SL110 Row Pins Output Timing Parameters (Part 3 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.858 4.636 5.191 5.507 5.347 5.588...
Page 660 GCLK values. These adder values are used to determine I/O timing when I/O pin is driven using regional clock. This applies for all I/O standards supported by Stratix III devices. Table 1–73 specifies EP3SL110 Column Pin delay adders when using the Regional Clock.
Page 661 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–73. EP3SL110 Column Pin Delay Adders for Regional Clock Fast Model Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V RCLK output adder — -0.023 0.046 0.126 0.245 0.201 0.407 RCLK PLL output adder —...
Page 662 — -0.895 -1.264 -1.363 -1.474 -1.415 -1.765 — 1.004 1.406 1.525 1.650 1.584 1.927 GCLK — 0.500 0.957 1.122 1.256 1.192 1.101 — -0.391 -0.815 -0.960 -1.080 -1.023 -0.939 1–150 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 663 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–75. EP3SL150 Column Pins Input Timing Parameters (Part 3 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-2 CLASS I GCLK — -0.835 -1.141 -1.220 -1.329 -1.271 -1.622...
Page 664 — -0.945 -1.298 -1.372 -1.464 -1.418 -1.766 — 1.047 1.441 1.534 1.643 1.587 1.928 GCLK — 0.512 0.983 1.150 1.253 1.176 1.144 — -0.410 -0.840 -0.988 -1.074 -1.007 -0.982 1–152 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 665 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–76. EP3SL150 Row Pins Input Timing Parameters (Part 2 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V LVCMOS GCLK — -0.945 -1.298 -1.372 -1.464 -1.418 -1.766 —...
Page 666 — -0.739 -0.993 -1.070 -1.051 -1.007 -1.357 — 0.848 1.140 1.237 1.239 1.185 1.527 GCLK — 0.685 1.334 1.542 1.666 1.587 1.529 — -0.579 -1.184 -1.370 -1.478 -1.409 -1.359 1–154 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 667 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–76. EP3SL150 Row Pins Input Timing Parameters (Part 4 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8-V HSTL CLASS II GCLK —...
Page 668 5.541 6.190 6.495 6.339 6.615 GCLK — 2.296 3.268 3.705 3.765 3.732 3.724 3.0-V LVTTL GCLK — 3.604 5.344 5.961 6.266 6.110 6.386 GCLK — 2.168 3.072 3.476 3.536 3.503 3.495 1–156 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 669 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–77. EP3SL150 Column Pins Output Timing Parameters (Part 2 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.0-V LVTTL 12mA GCLK —...
Page 670 5.936 6.687 6.992 6.836 7.112 GCLK — 2.499 3.663 4.202 4.262 4.229 4.221 1.5 V 12mA GCLK — 3.852 5.822 6.625 6.927 6.775 7.051 GCLK — 2.416 3.549 4.140 4.197 4.168 4.159 1–158 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 671 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–77. EP3SL150 Column Pins Output Timing Parameters (Part 4 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2 V GCLK —...
Page 672 4.708 5.253 5.555 5.403 5.679 GCLK — 1.731 2.435 2.768 2.825 2.796 2.788 SSTL-15 CLASS II 16mA GCLK — 3.165 4.711 5.259 5.561 5.409 5.685 GCLK — 1.729 2.438 2.774 2.831 2.802 2.794 1–160 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 673 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–77. EP3SL150 Column Pins Output Timing Parameters (Part 6 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8-V HSTL CLASS I GCLK —...
Page 674 4.773 5.300 5.602 5.450 5.726 GCLK — 1.846 2.500 2.815 2.872 2.843 2.835 3.0-V PCI-X — GCLK — 3.282 4.773 5.300 5.602 5.450 5.726 GCLK — 1.846 2.500 2.815 2.872 2.843 2.835 1–162 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 675 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–78 specifies EP3SL150 Row Pins Output Timing parameters for single-ended I/O standards. Table 1–78. EP3SL150 Row Pins Output Timing Parameters (Part 1 of 5) Fast Model Current I/O Standard Clock Parameter...
Page 676 5.616 6.301 6.570 6.533 6.672 GCLK — 2.363 3.441 3.886 3.937 3.914 3.786 1.5 V GCLK — 3.667 5.477 6.130 6.399 6.362 6.501 GCLK — 2.270 3.304 3.716 3.770 3.743 3.615 1–164 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 677 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–78. EP3SL150 Row Pins Output Timing Parameters (Part 3 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2 V GCLK —...
Page 678 4.705 5.239 5.505 5.359 5.611 GCLK — 1.727 2.421 2.716 2.774 2.741 2.725 1.5-V HSTL CLASS I GCLK — 3.223 4.733 5.273 5.539 5.400 5.645 GCLK — 1.784 2.471 2.753 2.808 2.781 2.759 1–166 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 679 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–78. EP3SL150 Row Pins Output Timing Parameters (Part 5 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.5-V HSTL CLASS I GCLK —...
Page 680 -1.058 -1.097 -1.203 -1.146 -1.517 SSTL CLASS I — 0.906 1.205 1.264 1.386 1.320 1.685 GCLK — 0.647 1.208 1.410 1.549 1.485 1.386 — -0.535 -1.061 -1.243 -1.366 -1.311 -1.218 1–168 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 681 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–79. EP3SL150 Column Pins Input Timing Parameters (Part 2 of 2) Fast Model Units I/O Standard Clock Parameter Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL 1.5-V GCLK — -0.794 -1.058 -1.097 -1.203 -1.146 -1.517 SSTL CLASS II —...
Page 682 -0.970 -1.004 -1.100 -1.049 -1.394 HSTL CLASS II — 0.839 1.117 1.171 1.283 1.223 1.562 GCLK — 0.684 1.348 1.577 1.736 1.658 1.583 — -0.578 -1.197 -1.404 -1.548 -1.479 -1.412 1–170 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 683 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–80. EP3SL150 Row Pins Input Timing Parameters (Part 2 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL 1.8-V GCLK — -0.741 -0.997 -1.036 -1.133 -1.082 -1.426 HSTL CLASS I —...
Page 684 GCLK — 1.564 2.618 2.965 3.046 3.003 2.993 DIFFERENTIAL GCLK — 2.912 4.711 5.276 5.601 5.434 5.698 1.2-V HSTL GCLK — 1.496 2.479 2.803 2.882 2.840 2.831 CLASS I 1–172 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 685 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–81. EP3SL150 Column Pins Output Timing Parameters (Part 2 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.904 4.696 5.258 5.583 5.416 5.680...
Page 686 2.464 2.785 2.864 2.822 2.813 CLASS I DIFFERENTIAL 12mA GCLK — 2.902 4.692 5.253 5.578 5.411 5.675 1.5-V SSTL GCLK — 1.486 2.460 2.780 2.859 2.817 2.808 CLASS I 1–174 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 687 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–81. EP3SL150 Column Pins Output Timing Parameters (Part 4 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.894 4.675 5.233 5.558 5.391 5.655...
Page 688 4.797 5.379 5.697 5.536 5.776 LVDS_E_1R GCLK — 1.516 2.550 2.892 2.965 2.926 2.889 MINI- — GCLK — 2.937 4.797 5.379 5.697 5.536 5.776 LVDS_E_3R GCLK — 1.516 2.550 2.892 2.965 2.926 2.889 1–176 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 689 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–82. EP3SL150 Row Pins Output Timing Parameters (Part 2 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V RSDS — GCLK —...
Page 690 2.408 2.726 2.797 2.759 2.723 CLASS I DIFFERENTIAL 10mA GCLK — 2.866 4.653 5.211 5.527 5.367 5.608 1.8-V SSTL GCLK — 1.445 2.406 2.724 2.795 2.757 2.721 CLASS I 1–178 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 691 GCLK values. These adder values are used to determine I/O timing when I/O pin is driven using regional clock. This applies for all I/O standards supported by Stratix III devices. Table 1–83 specifies EP3SL150 Column Pin delay adders when using the Regional Clock.
Page 692 — -1.166 -1.691 -1.810 -1.943 -1.874 -2.327 — 1.274 1.833 1.971 2.118 2.041 2.488 GCLK — 0.500 0.919 1.074 1.212 1.145 1.026 — -0.392 -0.777 -0.913 -1.037 -0.978 -0.865 1–180 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 693 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–85. EP3SL200 Column Pins Input Timing Parameters (Part 2 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V LVCMOS GCLK — -1.166 -1.691 -1.810 -1.943 -1.874 -2.327 —...
Page 694 -1.075 -1.259 -1.388 -1.328 -1.211 1.5-V HSTL CLASS I GCLK — -1.003 -1.361 -1.426 -1.552 -1.485 -1.942 GCLK — 0.663 1.249 1.458 1.603 1.534 1.411 — -0.551 -1.102 -1.291 -1.420 -1.360 -1.243 1–182 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 695 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–85. EP3SL200 Column Pins Input Timing Parameters (Part 4 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.5-V HSTL CLASS II GCLK —...
Page 696 — -1.076 -1.459 -1.543 -1.648 -1.589 -2.044 — 1.178 1.603 1.706 1.829 1.760 2.207 GCLK — 0.583 1.144 1.346 1.501 1.432 1.327 — -0.481 -1.000 -1.183 -1.320 -1.261 -1.164 1–184 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 697 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–86. EP3SL200 Row Pins Input Timing Parameters (Part 3 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-2 CLASS I GCLK — -0.994 -1.314 -1.394 -1.479 -1.428 -1.877...
Page 698 — -1.120 -1.570 -1.692 -1.781 -1.728 -2.175 — 1.222 1.713 1.854 1.960 1.897 2.337 GCLK — 0.520 1.016 1.192 1.345 1.271 1.176 — -0.418 -0.873 -1.030 -1.166 -1.102 -1.014 1–186 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 699 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–87 specifies EP3SL200 Column Pins Output Timing parameters for single-ended I/O standards. Table 1–87. EP3SL200 Column Pins Output Timing Parameters (Part 1 of 7) Fast Model Current I/O Standard Clock Parameter...
Page 700 6.148 6.899 7.225 7.057 7.426 GCLK — 2.439 3.531 4.008 4.063 4.031 4.064 1.8 V GCLK — 4.243 6.394 7.167 7.493 7.325 7.694 GCLK — 2.570 3.777 4.276 4.331 4.299 4.332 1–188 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 701 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–87. EP3SL200 Column Pins Output Timing Parameters (Part 3 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8 V GCLK —...
Page 702 5.084 5.652 5.975 5.811 6.180 GCLK — 1.775 2.467 2.761 2.813 2.785 2.818 SSTL-18 CLASS I GCLK — 3.432 5.072 5.640 5.963 5.799 6.168 GCLK — 1.759 2.455 2.749 2.801 2.773 2.806 1–190 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 703 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–87. EP3SL200 Column Pins Output Timing Parameters (Part 5 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-18 CLASS I 10mA GCLK —...
Page 704 GCLK — 1.750 2.440 2.732 2.784 2.756 2.789 1.5-V HSTL 12mA GCLK — 3.421 5.062 5.631 5.954 5.790 6.159 CLASS I GCLK — 1.748 2.445 2.740 2.792 2.764 2.797 1–192 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 705 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–87. EP3SL200 Column Pins Output Timing Parameters (Part 7 of 7) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.5-V HSTL 16mA GCLK —...
Page 706 5.877 6.707 6.865 6.708 7.186 GCLK — 2.332 3.291 3.823 3.739 3.847 3.846 3.0-V LVCMOS GCLK — 3.971 5.850 6.661 6.834 6.677 7.140 GCLK — 2.331 3.264 3.777 3.708 3.801 3.800 1–194 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 707 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–88. EP3SL200 Row Pins Output Timing Parameters (Part 2 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 2.5 V GCLK —...
Page 708 5.031 5.603 5.914 5.754 6.112 GCLK — 1.731 2.410 2.693 2.744 2.712 2.732 SSTL-18 CLASS II GCLK — 3.414 5.032 5.600 5.911 5.751 6.109 GCLK — 1.742 2.411 2.691 2.742 2.710 2.729 1–196 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 709 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–88. EP3SL200 Row Pins Output Timing Parameters (Part 4 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-18 CLASS II 16mA GCLK —...
Page 710 5.060 5.626 5.919 5.766 6.117 GCLK — 1.852 2.474 2.742 2.793 2.767 2.766 Table 1–89 through Table 1–92 show the maximum I/O timing parameters for EP3SL200 devices for differential I/O standards. 1–198 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 711 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–89 specifies EP3SL200 Column Pins Input Timing parameters for differential I/O standards. Table 1–89. EP3SL200 Column Pins Input Timing Parameters (Part 1 of 2) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V...
Page 712 -1.444 -1.522 -1.651 -1.583 -2.057 2.5-V SSTL — 1.153 1.588 1.686 1.829 1.753 2.221 CLASS II GCLK — 0.624 1.168 1.364 1.506 1.439 1.314 — -0.515 -1.024 -1.200 -1.328 -1.269 -1.150 1–200 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 713 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–90 specifies EP3SL200 Row Pins Input Timing parameters for differential I/O standards. Table 1–90. EP3SL200 Row Pins Input Timing Parameters (Part 1 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V...
Page 714 -1.391 -1.460 -1.587 -1.521 -1.963 2.5-V SSTL — 1.121 1.535 1.624 1.765 1.691 2.127 CLASS I GCLK — 0.646 1.272 1.490 1.652 1.573 1.476 — -0.543 -1.127 -1.325 -1.469 -1.401 -1.311 1–202 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 715 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–90. EP3SL200 Row Pins Input Timing Parameters (Part 3 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -1.012 -1.391 -1.460 -1.587 -1.521 -1.963 2.5-V SSTL...
Page 716 2.396 2.706 2.783 2.741 2.760 CLASS I DIFFERENTIAL 16mA GCLK — 3.108 4.985 5.564 5.912 5.733 6.104 1.5-V HSTL GCLK — 1.438 2.371 2.677 2.753 2.711 2.731 CLASS II 1–204 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 717 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–91. EP3SL200 Column Pins Output Timing Parameters (Part 3 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 3.115 5.000 5.581 5.930 5.751 6.121...
Page 718 2.393 2.703 2.780 2.738 2.757 CLASS I DIFFERENTIAL 10mA GCLK — 3.118 5.005 5.587 5.936 5.757 6.127 2.5-V SSTL GCLK — 1.448 2.391 2.700 2.777 2.735 2.754 CLASS I 1–206 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 719 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–91. EP3SL200 Column Pins Output Timing Parameters (Part 5 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL 12mA GCLK —...
Page 720 1.442 2.373 2.677 2.748 2.711 2.697 CLASS I DIFFERENTIAL GCLK — 3.094 4.963 5.540 5.883 5.708 6.047 1.8-V HSTL GCLK — 1.436 2.362 2.664 2.735 2.698 2.684 CLASS I 1–208 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 721 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–92. EP3SL200 Row Pins Output Timing Parameters (Part 3 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 3.098 4.966 5.544 5.887 5.712 6.051...
Page 722 GCLK values. These adder values are used to determine I/O timing when I/O pin is driven using regional clock. This applies for all I/O standards supported by Stratix III devices. Table 1–93 specifies EP3SL200 Column Pin delay adders when using the Regional Clock.
Page 723 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–93. EP3SL200 Column Pin Delay Adders for Regional Clock (Part 2 of 2) Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V RCLK output —...
Page 724 — -1.250 — -1.932 -2.076 -1.998 -2.493 — 1.358 — 2.093 2.251 2.165 2.654 GCLK — 0.470 — 1.048 1.167 1.123 0.992 — -0.362 — -0.887 -0.992 -0.956 -0.831 1–212 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 725 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–95. EP3SL340 Column Pins Input Timing Parameters (Part 2 of 3) Fast Model Clock Parameter Units Standard Industrial Commercial 1.1V 1.1V 1.1V 1.1V 1.2 V GCLK — -1.193 — -1.798 -1.941 -1.863 -2.359...
Page 726 -1.255 — -1.943 -2.088 -2.010 -2.504 PCI-X — 1.363 — 2.104 2.263 2.177 2.665 GCLK — 0.465 — 1.037 1.155 1.111 0.981 — -0.357 — -0.876 -0.980 -0.944 -0.820 1–214 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 727 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–96 specifies EP3SL340 Row Pins Input Timing parameters for single-ended I/O standards. Table 1–96. EP3SL340 Row Pins Input Timing Parameters (Part 1 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V...
Page 728 — -1.432 -1.676 -1.610 -1.947 CLASS II — 1.167 — 1.604 1.858 1.783 2.117 GCLK — 0.661 — 1.563 1.714 1.646 1.538 — -0.555 — -1.391 -1.526 -1.468 -1.368 1–216 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 729 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–96. EP3SL340 Row Pins Input Timing Parameters (Part 3 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8-V HSTL GCLK — -1.061 —...
Page 730 6.713 7.050 6.887 7.278 LVCMOS GCLK — 2.383 — 3.744 3.813 3.772 3.803 3.3-V 12mA GCLK — 4.149 — 6.781 7.118 6.955 7.346 LVCMOS GCLK — 2.435 — 3.812 3.881 3.840 3.871 1–218 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 731 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–97. EP3SL340 Column Pins Output Timing Parameters (Part 2 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V 16mA GCLK —...
Page 732 6.895 7.232 7.069 7.460 GCLK — 2.407 — 3.926 3.995 3.954 3.985 1.5 V GCLK — 4.075 — 6.814 7.151 6.988 7.379 GCLK — 2.361 — 3.845 3.914 3.873 3.904 1–220 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 733 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–97. EP3SL340 Column Pins Output Timing Parameters (Part 4 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.5 V GCLK —...
Page 734 CLASS I GCLK — 1.789 — 2.797 2.863 2.826 2.857 SSTL-15 10mA GCLK — 3.500 — 5.768 6.102 5.943 6.334 CLASS I GCLK — 1.786 — 2.799 2.865 2.828 2.859 1–222 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 735 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–97. EP3SL340 Column Pins Output Timing Parameters (Part 6 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-15 12mA GCLK —...
Page 736 CLASS II GCLK — 1.809 — 2.810 2.876 2.839 2.870 3.0-V PCI — GCLK — 3.618 — 5.795 6.129 5.970 6.361 GCLK — 1.904 — 2.826 2.892 2.855 2.886 1–224 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 737 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–97. EP3SL340 Column Pins Output Timing Parameters (Part 8 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.0-V PCI-X — GCLK —...
Page 738 7.142 7.504 7.325 7.691 GCLK — 2.541 — 4.035 4.238 4.055 4.210 1.5 V GCLK — 4.379 — 7.341 7.703 7.524 7.890 GCLK — 2.657 — 4.144 4.437 4.164 4.409 1–226 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 739 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–98. EP3SL340 Row Pins Output Timing Parameters (Part 3 of 5) Fast Model Current Clock Parameter Units Standard Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.5 V GCLK — 4.204 —...
Page 740 1.774 — 2.725 2.797 2.746 2.773 CLASS I 1.8-V 10mA GCLK — 3.496 — 5.723 6.065 5.890 6.256 HSTL GCLK — 1.774 — 2.728 2.799 2.749 2.775 CLASS I 1–228 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 741 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–98. EP3SL340 Row Pins Output Timing Parameters (Part 5 of 5) Fast Model Current Clock Parameter Units Standard Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8-V 12mA GCLK — 3.488 —...
Page 742 -1.565 -1.703 -1.627 -2.124 1.5-V SSTL — 1.209 — 1.732 1.886 1.801 2.292 CLASS I GCLK — 0.644 — 1.423 1.562 1.500 1.368 — -0.532 — -1.256 -1.379 -1.326 -1.200 1–230 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 743 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–99. EP3SL340 Column Pins Input Timing Parameters (Part 2 of 2) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -1.097 — -1.565 -1.703 -1.627 -2.124 1.5-V SSTL...
Page 744 -1.514 -1.643 -1.577 -2.044 1.5-V HSTL — 1.188 — 1.681 1.826 1.751 2.212 CLASS II GCLK — 0.669 — 1.582 1.739 1.662 1.557 — -0.563 — -1.409 -1.551 -1.483 -1.386 1–232 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 745 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–100. EP3SL340 Row Pins Input Timing Parameters (Part 2 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -1.090 — -1.546 -1.676 -1.610 -2.076 1.8-V HSTL...
Page 746 GCLK — 1.576 — 2.961 3.044 2.996 3.020 DIFFERENTIAL GCLK — 3.248 — 5.784 6.143 5.957 6.348 1.2-V HSTL GCLK — 1.508 — 2.799 2.880 2.833 2.858 CLASS I 1–234 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 747 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–101. EP3SL340 Column Pins Output Timing Parameters (Part 2 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 3.240 —...
Page 748 — 2.781 2.862 2.815 2.840 CLASS I DIFFERENTIAL 12mA GCLK — 3.238 — 5.761 6.120 5.934 6.325 1.5-V SSTL GCLK — 1.498 — 2.776 2.857 2.810 2.835 CLASS I 1–236 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 749 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–101. EP3SL340 Column Pins Output Timing Parameters (Part 4 of 5) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 3.230 —...
Page 750 5.894 6.244 6.066 6.427 LVDS_E_1R GCLK — 1.557 — 2.912 2.985 2.946 2.942 MINI- — GCLK — 3.293 — 5.894 6.244 6.066 6.427 LVDS_E_3R GCLK — 1.557 — 2.912 2.985 2.946 2.942 1–238 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 751 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–102. EP3SL340 Row Pins output Timing Parameters (Part 2 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V RSDS — GCLK —...
Page 752 — 2.746 2.817 2.779 2.776 CLASS I DIFFERENTIAL 10mA GCLK — 3.216 — 5.720 6.068 5.891 6.256 1.8-V SSTL GCLK — 1.486 — 2.744 2.815 2.777 2.774 CLASS I 1–240 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 753 GCLK values. These adder values are used to determine I/O timing when I/O pin is driven using regional clock. This applies for all I/O standards supported by Stratix III devices. Table 1–103 specifies EP3SL340 Column Pin delay adders when using the Regional Clock.
Page 754 — -0.729 -1.055 -1.144 -1.238 -1.187 -1.479 — 0.837 1.197 1.305 1.413 1.354 1.640 GCLK — 0.412 0.785 0.928 1.051 0.993 0.875 — -0.304 -0.643 -0.767 -0.876 -0.826 -0.714 1–242 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 755 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–105. EP3SE50 Column Pins Input Timing Parameters (Part 2 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.0-V GCLK — -0.729 -1.055 -1.144 -1.238 -1.187 -1.479 LVCMOS —...
Page 756 -0.982 -1.161 -1.275 -1.224 -1.108 1.2-V HSTL GCLK — -0.559 -0.710 -0.744 -0.831 -0.782 -1.078 CLASS II GCLK — 0.582 1.130 1.328 1.458 1.398 1.276 — -0.470 -0.982 -1.161 -1.275 -1.224 -1.108 1–244 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 757 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–105. EP3SE50 Column Pins Input Timing Parameters (Part 4 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.0-V PCI GCLK — -0.729 -1.055 -1.144 -1.238 -1.187 -1.479 —...
Page 758 -0.686 -0.711 -0.777 -0.743 -1.007 CLASS II — 0.672 0.831 0.876 0.960 0.915 1.172 GCLK — 0.576 1.156 1.368 1.516 1.445 1.351 — -0.473 -1.011 -1.203 -1.333 -1.273 -1.186 1–246 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 759 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–106. EP3SE50 Row Pins Input Timing Parameters (Part 3 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-18 GCLK — -0.522 -0.591 -0.596 -0.665 -0.629 -0.885 CLASS I —...
Page 760 Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V LVTTL GCLK — 3.552 5.255 5.897 6.184 6.035 6.236 GCLK — 2.411 3.415 3.823 3.893 3.853 3.879 1–248 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 761 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–107. EP3SE50 Column Pins Output Timing Parameters (Part 2 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V LVTTL GCLK —...
Page 762 5.378 6.123 6.407 6.262 6.463 GCLK — 2.441 3.538 4.049 4.116 4.080 4.106 1.8 V GCLK — 3.648 5.472 6.179 6.466 6.317 6.518 GCLK — 2.507 3.632 4.105 4.175 4.135 4.161 1–250 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 763 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–107. EP3SE50 Column Pins Output Timing Parameters (Part 4 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8 V GCLK —...
Page 764 CLASS I GCLK — 1.840 2.583 2.888 2.955 2.919 2.945 SSTL-18 12mA GCLK — 2.980 4.422 4.962 5.246 5.101 5.302 CLASS I GCLK — 1.839 2.582 2.888 2.955 2.919 2.945 1–252 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 765 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–107. EP3SE50 Column Pins Output Timing Parameters (Part 6 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-18 GCLK — 2.991 4.423 4.959 5.243 5.098 5.299...
Page 766 CLASS II GCLK — 1.846 2.571 2.871 2.938 2.902 2.928 1.2-V HSTL GCLK — 3.020 4.458 5.007 5.291 5.146 5.347 CLASS I GCLK — 1.879 2.618 2.933 3.000 2.964 2.990 1–254 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 767 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–107. EP3SE50 Column Pins Output Timing Parameters (Part 8 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2-V HSTL GCLK —...
Page 768 5.738 6.265 6.542 6.402 6.568 GCLK — 2.663 3.886 4.408 4.471 4.436 4.428 2.5 V GCLK — 3.614 5.430 5.949 6.226 6.086 6.252 GCLK — 2.462 3.578 4.054 4.117 4.082 4.074 1–256 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 769 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–108. EP3SE50 Row Pins Output Timing Parameters (Part 3 of 6) Fast Model Current Clock Parameter Units Standard Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 2.5 V 12mA GCLK —...
Page 770 CLASS II GCLK — 1.804 2.529 2.840 2.899 2.870 2.856 SSTL-15 GCLK — 2.993 4.412 4.947 5.222 5.084 5.242 CLASS I GCLK — 1.869 2.593 2.914 2.973 2.944 2.930 1–258 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 771 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–108. EP3SE50 Row Pins Output Timing Parameters (Part 5 of 6) Fast Model Current Clock Parameter Units Standard Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-15 GCLK — 2.968 4.395 4.930 5.205 5.067 5.225...
Page 772 -0.724 -0.744 -0.831 -0.782 -1.078 1.2-V HSTL — 0.686 0.872 0.911 1.014 0.956 1.246 CLASS I GCLK — 0.589 1.136 1.330 1.460 1.400 1.276 — -0.477 -0.988 -1.163 -1.277 -1.226 -1.108 1–260 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 773 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–109. EP3SE50 Column Pins Input Timing Parameters (Part 2 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -0.574 -0.724 -0.744 -0.831 -0.782 -1.078 1.2-V HSTL...
Page 774 — -0.614 -0.802 -0.836 -0.919 -0.876 -1.136 — 0.719 0.945 1.000 1.097 1.046 1.300 GCLK — 0.533 1.064 1.252 1.395 1.326 1.233 — -0.428 -0.916 -1.081 -1.209 -1.149 -1.064 1–262 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 775 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–110. EP3SE50 Row Pins Input Timing Parameters (Part 2 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V MINI-LVDS GCLK — -0.614 -0.802 -0.836 -0.919 -0.876 -1.136 —...
Page 776 -0.743 -0.768 -0.850 -0.807 -1.068 2.5-V SSTL — 0.675 0.887 0.932 1.028 0.977 1.232 CLASS II GCLK — 0.583 1.166 1.368 1.516 1.445 1.351 — -0.480 -1.021 -1.203 -1.333 -1.273 -1.186 1–264 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 777 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–111 specifies EP3SE50 Column Pins Output Timing parameters for differential I/O standards. Table 1–111. EP3SE50 Column Pins Output Timing Parameters (Part 1 of 4) Fast Model Current I/O Standard Clock Parameter...
Page 778 1.534 2.518 2.839 2.926 2.877 2.894 CLASS I DIFFERENTIAL GCLK — 2.699 4.384 4.919 5.225 5.066 5.256 1.8-V HSTL GCLK — 1.538 2.525 2.847 2.935 2.886 2.902 CLASS I 1–266 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 779 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–111. EP3SE50 Column Pins Output Timing Parameters (Part 3 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL 10mA GCLK —...
Page 780 2.529 2.852 2.939 2.890 2.907 CLASS I DIFFERENTIAL 16mA GCLK — 2.699 4.385 4.920 5.226 5.067 5.257 2.5-V SSTL GCLK — 1.538 2.526 2.848 2.936 2.887 2.903 CLASS II 1–268 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 781 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–112 specifies EP3SE50 Row Pins Output Timing parameters for differential I/O standards. Table 1–112. EP3SE50 Row Pins Output Timing Parameters (Part 1 of 4) Fast Model Current I/O Standard Clock Parameter...
Page 782 2.473 2.791 2.872 2.831 2.813 CLASS I DIFFERENTIAL 16mA GCLK — 2.654 4.313 4.841 5.137 4.986 5.145 1.8-V HSTL GCLK — 1.494 2.455 2.770 2.850 2.809 2.792 CLASS II 1–270 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 783 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–112. EP3SE50 Row Pins Output Timing Parameters (Part 3 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.686 4.377 4.915 5.213 5.061 5.219...
Page 784 GCLK values. These adder values are used to determine I/O timing when I/O pin is driven using regional clock. This applies for all I/O standards supported by Stratix III devices. Table 1–113 specifies EP3SE50 Column Pin delay adders when using the Regional Clock in Stratix III devices.
Page 785 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–114. EP3SE50 Row Pin Delay Adders for Regional Clock Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V RCLK output adder — 0.077 0.269 0.37...
Page 786 -1.019 -1.196 -1.321 -1.263 -1.184 SSTL-18 GCLK — -0.832 -1.122 -1.170 -1.280 -1.221 -1.611 CLASS II GCLK — 0.621 1.166 1.363 1.503 1.436 1.352 — -0.510 -1.019 -1.196 -1.321 -1.263 -1.184 1–274 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 787 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–115. EP3SE80 Column Pins Input Timing Parameters (Part 3 of 4) Fast Model Clock Parameter Units Standard Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-15 GCLK — -0.818 -1.095 -1.138 -1.247 -1.188 -1.579...
Page 788 -0.948 -1.315 -1.393 -1.485 -1.438 -1.801 LVCMOS — 1.050 1.458 1.555 1.664 1.607 1.963 GCLK — 0.509 0.933 1.136 1.293 1.216 1.151 — -0.407 -0.791 -0.974 -1.114 -1.047 -0.989 1–276 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 789 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–116. EP3SE80 Row Pins Input Timing Parameters (Part 2 of 4) Fast Model Clock Parameter Units Standard Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 2.5 V GCLK — -0.953 -1.325 -1.404 -1.497 -1.450 -1.812 —...
Page 790 -1.011 -1.047 -1.023 -0.978 -1.344 HSTL — 0.875 1.159 1.214 1.211 1.157 1.514 CLASS II GCLK — 0.690 1.278 1.603 1.755 1.676 1.612 — -0.578 -1.130 -1.431 -1.567 -1.497 -1.442 1–278 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 791 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–116. EP3SE80 Row Pins Input Timing Parameters (Part 4 of 4) Fast Model Clock Parameter Units Standard Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2-V GCLK — -0.763 -1.011 -1.047 -1.023 -0.978 -1.344 HSTL —...
Page 792 5.643 6.298 6.607 6.449 6.744 GCLK — 2.367 3.362 3.772 3.831 3.799 3.789 3.0-V LVCMOS GCLK — 3.828 5.673 6.329 6.638 6.480 6.775 GCLK — 2.383 3.392 3.802 3.861 3.829 3.819 1–280 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 793 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–117. EP3SE80 Column Pins Output Timing Parameters (Part 3 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.0-V LVCMOS GCLK —...
Page 794 5.827 6.660 6.966 6.812 7.107 GCLK — 2.425 3.546 4.134 4.190 4.162 4.152 1.2 V GCLK — 3.805 5.708 6.409 6.718 6.560 6.855 GCLK — 2.359 3.427 3.883 3.942 3.910 3.900 1–282 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 795 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–117. EP3SE80 Column Pins Output Timing Parameters (Part 5 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2 V GCLK —...
Page 796 CLASS I GCLK — 1.791 2.503 2.800 2.856 2.828 2.818 1.8-V HSTL GCLK — 3.225 4.775 5.316 5.622 5.468 5.763 CLASS I GCLK — 1.779 2.494 2.790 2.846 2.818 2.808 1–284 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 797 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–117. EP3SE80 Column Pins Output Timing Parameters (Part 7 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8-V HSTL 10mA GCLK —...
Page 798 5.734 6.393 6.692 6.541 6.808 GCLK — 2.315 3.277 3.854 3.904 3.878 3.850 3.3-V LVTTL GCLK — 3.718 5.490 6.117 6.416 6.265 6.532 GCLK — 2.188 3.083 3.578 3.628 3.602 3.574 1–286 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 799 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–118. EP3SE80 Row Pins Output Timing Parameters (Part 2 of 6) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V LVTTL 12mA GCLK —...
Page 800 5.787 6.614 7.091 6.944 7.031 GCLK — 2.398 3.498 4.258 4.303 4.281 4.253 SSTL-2 GCLK — 3.256 4.787 5.326 5.622 5.475 5.742 CLASS I GCLK — 1.775 2.467 2.787 2.834 2.812 2.784 1–288 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 801 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–118. EP3SE80 Row Pins Output Timing Parameters (Part 4 of 6) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-2 12mA GCLK —...
Page 802 CLASS I GCLK — 1.763 2.460 2.779 2.824 2.802 2.774 1.2-V HSTL GCLK — 3.237 4.774 5.326 5.655 5.508 5.743 CLASS I GCLK — 1.784 2.485 2.822 2.867 2.845 2.817 1–290 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 803 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–118. EP3SE80 Row Pins Output Timing Parameters (Part 6 of 6) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2-V HSTL GCLK —...
Page 804 -1.129 -1.177 -1.288 -1.230 -1.617 1.8-V SSTL — 0.950 1.276 1.344 1.470 1.403 1.785 CLASS I GCLK — 0.615 1.160 1.356 1.496 1.429 1.336 — -0.504 -1.013 -1.189 -1.314 -1.256 -1.168 1–292 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 805 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–119. EP3SE80 Column Pins Input Timing Parameters (Part 3 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -0.839 -1.129 -1.177 -1.288 -1.230 -1.617 1.8-V SSTL...
Page 806 -1.052 -1.094 -1.196 -1.143 -1.503 1.8-V HSTL — 0.895 1.199 1.261 1.378 1.316 1.671 CLASS II GCLK — 0.674 1.321 1.547 1.706 1.627 1.560 — -0.568 -1.171 -1.375 -1.518 -1.449 -1.390 1–294 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 807 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–120. EP3SE80 Row Pins Input Timing Parameters (Part 3 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -0.770 -1.025 -1.062 -1.163 -1.110 -1.471 1.5-V SSTL...
Page 808 2.477 2.797 2.876 2.834 2.824 CLASS I DIFFERENTIAL 10mA GCLK — 2.942 4.757 5.323 5.654 5.484 5.768 1.2-V HSTL GCLK — 1.498 2.479 2.799 2.878 2.836 2.826 CLASS I 1–296 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 809 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–121. EP3SE80 Column Pins Output Timing Parameters (Part 2 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL 12mA GCLK —...
Page 810 1.489 2.461 2.778 2.857 2.815 2.805 CLASS II DIFFERENTIAL GCLK — 2.944 4.760 5.327 5.658 5.488 5.772 1.8-V SSTL GCLK — 1.500 2.482 2.803 2.882 2.840 2.830 CLASS I 1–298 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 811 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–121. EP3SE80 Column Pins Output Timing Parameters (Part 4 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.937 4.746 5.310 5.641 5.471 5.755...
Page 812 GCLK — 1.535 2.572 2.912 2.985 2.947 2.906 DIFFERENTIAL GCLK — 2.931 4.743 5.307 5.629 5.467 5.723 1.2-V HSTL GCLK — 1.476 2.453 2.772 2.844 2.807 2.766 CLASS I 1–300 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 813 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–122. EP3SE80 Row Pins Output Timing Parameters (Part 2 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.923 4.726 5.288 5.610 5.447 5.704...
Page 814 1.456 2.412 2.725 2.796 2.759 2.719 CLASS II DIFFERENTIAL GCLK — 2.919 4.717 5.278 5.599 5.437 5.694 2.5-V SSTL GCLK — 1.464 2.427 2.743 2.814 2.777 2.737 CLASS I 1–302 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 815 GCLK values. These adder values are used to determine I/O timing when I/O pin is driven using regional clock. This applies for all I/O standards supported by Stratix III devices. Table 1–123 specifies EP3SE80 Column Pin delay adders when using the Regional Clock.
Page 816 — -0.981 -1.425 -1.522 -1.638 -1.577 -1.964 — 1.089 1.567 1.683 1.813 1.744 2.125 GCLK — 0.474 0.865 1.013 1.147 1.081 0.990 — -0.366 -0.723 -0.852 -0.972 -0.914 -0.829 1–304 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 817 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–125. EP3SE110 Column Pins Input Timing Parameters (Part 2 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.0-V GCLK — -0.981 -1.425 -1.522 -1.638 -1.577 -1.964 LVCMOS —...
Page 818 -1.062 -1.246 -1.371 -1.312 -1.223 1.2-V HSTL GCLK — -0.811 -1.080 -1.122 -1.231 -1.172 -1.563 CLASS II GCLK — 0.644 1.210 1.413 1.554 1.486 1.391 — -0.532 -1.062 -1.246 -1.371 -1.312 -1.223 1–306 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 819 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–125. EP3SE110 Column Pins Input Timing Parameters (Part 4 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.0-V PCI GCLK — -0.981 -1.425 -1.522 -1.638 -1.577 -1.964 —...
Page 820 -1.109 -1.159 -1.192 -1.145 -1.499 CLASS II — 0.932 1.253 1.323 1.375 1.317 1.664 GCLK — 0.622 1.220 1.434 1.602 1.522 1.453 — -0.519 -1.075 -1.269 -1.419 -1.350 -1.288 1–308 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 821 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–126. EP3SE110 Row Pins Input Timing Parameters (Part 3 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-18 GCLK — -0.782 -0.971 -0.978 -1.081 -1.034 -1.384 CLASS I —...
Page 822 Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V LVTTL GCLK — 3.796 5.617 6.265 6.574 6.416 6.711 GCLK — 2.352 3.338 3.741 3.800 3.767 3.768 1–310 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 823 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–127. EP3SE110 Column Pins Output Timing Parameters (Part 2 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V LVTTL GCLK —...
Page 824 5.740 6.491 6.797 6.643 6.938 GCLK — 2.382 3.461 3.967 4.023 3.994 3.995 1.8 V GCLK — 3.892 5.834 6.547 6.856 6.698 6.993 GCLK — 2.448 3.555 4.023 4.082 4.049 4.050 1–312 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 825 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–127. EP3SE110 Column Pins Output Timing Parameters (Part 4 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8 V GCLK —...
Page 826 CLASS I GCLK — 1.781 2.506 2.806 2.862 2.833 2.834 SSTL-18 12mA GCLK — 3.224 4.784 5.330 5.636 5.482 5.777 CLASS I GCLK — 1.780 2.505 2.806 2.862 2.833 2.834 1–314 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 827 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–127. EP3SE110 Column Pins Output Timing Parameters (Part 6 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-18 GCLK — 3.235 4.785 5.327 5.633 5.479 5.774...
Page 828 CLASS II GCLK — 1.787 2.494 2.789 2.845 2.816 2.817 1.2-V HSTL GCLK — 3.264 4.820 5.375 5.681 5.527 5.822 CLASS I GCLK — 1.820 2.541 2.851 2.907 2.878 2.879 1–316 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 829 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–127. EP3SE110 Column Pins Output Timing Parameters (Part 8 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2-V HSTL GCLK —...
Page 830 6.118 6.867 7.179 7.026 7.282 GCLK — 2.500 3.635 4.120 4.382 4.356 4.317 2.5 V GCLK — 3.874 5.810 6.513 6.825 6.672 6.928 GCLK — 2.327 3.371 3.804 4.028 4.002 3.963 1–318 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 831 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–128. EP3SE110 Row Pins Output Timing Parameters (Part 3 of 6) Fast Model Current Clock Parameter Units Standard Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 2.5 V 12mA GCLK —...
Page 832 CLASS II GCLK — 1.762 2.469 2.757 2.816 2.793 2.749 SSTL-15 GCLK — 3.281 4.825 5.368 5.677 5.528 5.780 CLASS I GCLK — 1.825 2.533 2.804 2.890 2.867 2.819 1–320 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 833 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–128. EP3SE110 Row Pins Output Timing Parameters (Part 5 of 6) Fast Model Current Clock Parameter Units Standard Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-15 GCLK — 3.247 4.801 5.342 5.651 5.502 5.754...
Page 834 -1.087 -1.129 -1.239 -1.181 -1.569 1.2-V HSTL — 0.930 1.235 1.296 1.422 1.355 1.737 CLASS I GCLK — 0.636 1.202 1.404 1.545 1.478 1.384 — -0.524 -1.054 -1.237 -1.362 -1.304 -1.216 1–322 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 835 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–129. EP3SE110 Column Pins Input Timing Parameters (Part 2 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -0.818 -1.087 -1.129 -1.239 -1.181 -1.569 1.2-V HSTL...
Page 836 GCLK — -1.167 -1.226 -1.331 -1.277 -1.636 0.982 — 1.312 1.390 1.509 1.447 1.800 0.577 GCLK — 1.124 1.318 1.474 1.397 1.331 -0.472 — -0.976 -1.147 -1.288 -1.220 -1.162 1–324 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 837 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–130. EP3SE110 Row Pins Input Timing Parameters (Part 2 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V -0.877 MINI-LVDS GCLK — -1.167 -1.226 -1.331 -1.277 -1.636 0.982...
Page 838 -1.108 -1.158 -1.262 -1.208 -1.568 2.5-V SSTL 0.930 — 1.252 1.322 1.440 1.378 1.732 CLASS II 0.627 GCLK — 1.226 1.434 1.595 1.516 1.449 -0.524 — -1.081 -1.269 -1.412 -1.344 -1.284 1–326 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 839 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–131 specifies EP3SE110 Column Pins Output Timing parameters for differential I/O standards. Table 1–131. EP3SE110 Column Pins Output Timing Parameters (Part 1 of 4) Fast Model Current I/O Standard Clock Parameter...
Page 840 1.482 2.447 2.762 2.840 2.798 2.789 CLASS I DIFFERENTIAL GCLK — 2.930 4.732 5.294 5.625 5.455 5.739 1.8-V HSTL GCLK — 1.486 2.454 2.770 2.849 2.807 2.797 CLASS I 1–328 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 841 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–131. EP3SE110 Column Pins Output Timing Parameters (Part 3 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL 10mA GCLK —...
Page 842 2.458 2.775 2.853 2.811 2.802 CLASS I DIFFERENTIAL 16mA GCLK — 2.930 4.733 5.295 5.626 5.456 5.740 2.5-V SSTL GCLK — 1.486 2.455 2.771 2.850 2.808 2.798 CLASS II 1–330 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 843 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–132 specifies EP3SE110 Row Pins Output Timing parameters for differential I/O standards. Table 1–132. EP3SE110 Row Pins Output Timing Parameters (Part 1 of 4) Fast Model Current I/O Standard Clock Parameter...
Page 844 2.406 2.718 2.789 2.752 2.712 CLASS I DIFFERENTIAL 16mA GCLK — 2.899 4.678 5.232 5.552 5.390 5.648 1.8-V HSTL GCLK — 1.444 2.388 2.697 2.767 2.730 2.691 CLASS II 1–332 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 845 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–132. EP3SE110 Row Pins Output Timing Parameters (Part 3 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 2.931 4.742 5.306 5.628 5.465 5.722...
Page 846 GCLK values. These adder values are used to determine I/O timing when I/O pin is driven using regional clock. This applies for all I/O standards supported by Stratix III devices. Table 1–133 specifies EP3SE110 Column Pin delay adders when using the Regional Clock.
Page 847 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–134. EP3SE110 Row Pin Delay Adders for Regional Clock Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V RCLK output adder — -0.055 0.083 0.118...
Page 848 -1.259 -1.388 -1.328 -1.211 SSTL-18 GCLK — -1.017 — -1.458 -1.585 -1.518 -1.974 CLASS II GCLK — 0.649 — 1.426 1.570 1.501 1.379 — -0.538 — -1.259 -1.388 -1.328 -1.211 1–336 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 849 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–135. EP3SE260 Column Pins Input Timing Parameters (Part 3 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-15 GCLK — -1.003 — -1.426 -1.552 -1.485 -1.942...
Page 850 -1.120 — -1.692 -1.781 -1.728 -2.175 LVCMOS — 1.222 — 1.854 1.960 1.897 2.337 GCLK — 0.520 — 1.192 1.345 1.271 1.176 — -0.418 — -1.030 -1.166 -1.102 -1.014 1–338 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 851 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–136. EP3SE260 Row Pins Input Timing Parameters (Part 2 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 2.5 V GCLK — -1.125 —...
Page 852 — -1.233 -1.337 -1.279 -1.736 CLASS II — 1.051 — 1.405 1.525 1.458 1.906 GCLK — 0.714 — 1.656 1.812 1.742 1.635 — -0.608 — -1.484 -1.624 -1.563 -1.465 1–340 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 853 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–136. EP3SE260 Row Pins Input Timing Parameters (Part 4 of 4) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2-V HSTL GCLK — -0.945 —...
Page 854 6.593 6.919 6.751 7.120 GCLK — 2.332 — 3.702 3.757 3.725 3.758 3.0-V GCLK — 4.021 — 6.623 6.949 6.781 7.150 LVCMOS GCLK — 2.347 — 3.733 3.788 3.756 3.789 1–342 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 855 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–137. EP3SE260 Column Pins Output Timing Parameters (Part 3 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.0-V GCLK — 4.017 —...
Page 856 6.955 7.278 7.114 7.483 GCLK — 2.390 — 4.064 4.116 4.088 4.121 1.2 V GCLK — 3.997 — 6.704 7.030 6.862 7.231 GCLK — 2.324 — 3.813 3.868 3.836 3.869 1–344 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 857 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–137. EP3SE260 Column Pins Output Timing Parameters (Part 5 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2 V GCLK —...
Page 858 CLASS I GCLK — 1.756 — 2.730 2.782 2.754 2.787 1.8-V HSTL GCLK — 3.417 — 5.611 5.934 5.770 6.139 CLASS I GCLK — 1.744 — 2.720 2.772 2.744 2.777 1–346 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 859 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–137. EP3SE260 Column Pins Output Timing Parameters (Part 7 of 8) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.8-V HSTL 10mA GCLK —...
Page 860 6.692 6.802 6.645 7.171 GCLK — 2.301 — 3.808 3.676 3.832 3.831 3.3-V LVTTL GCLK — 3.814 — 6.416 6.576 6.419 6.895 GCLK — 2.174 — 3.532 3.450 3.556 3.555 1–348 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 861 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–138. EP3SE260 Row Pins Output Timing Parameters (Part 2 of 6) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 3.3-V LVTTL 12mA GCLK —...
Page 862 7.094 7.405 7.245 7.603 GCLK — 2.384 — 4.025 4.076 4.044 4.223 SSTL-2 GCLK — 3.401 — 5.625 5.887 5.734 6.105 CLASS I GCLK — 1.761 — 2.741 2.761 2.766 2.765 1–350 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 863 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–138. EP3SE260 Row Pins Output Timing Parameters (Part 4 of 6) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V SSTL-2 12mA GCLK —...
Page 864 CLASS I GCLK — 1.749 — 2.702 2.753 2.721 2.744 1.2-V HSTL GCLK — 3.450 — 5.658 5.969 5.809 6.167 CLASS I GCLK — 1.770 — 2.737 2.788 2.756 2.787 1–352 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 865 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–138. EP3SE260 Row Pins Output Timing Parameters (Part 6 of 6) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V 1.2-V HSTL GCLK —...
Page 866 -1.458 -1.585 -1.518 -1.992 1.8-V SSTL — 1.128 — 1.625 1.767 1.691 2.160 CLASS I GCLK — 0.651 — 1.428 1.572 1.504 1.379 — -0.540 — -1.261 -1.390 -1.331 -1.211 1–354 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 867 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–139. EP3SE260 Column Pins Input Timing Parameters (Part 3 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -1.017 — -1.458 -1.585 -1.518 -1.992 1.8-V SSTL...
Page 868 -1.396 -1.521 -1.456 -1.898 1.8-V HSTL — 1.096 — 1.563 1.703 1.629 2.066 CLASS II GCLK — 0.693 — 1.603 1.763 1.684 1.587 — -0.587 — -1.431 -1.575 -1.506 -1.417 1–356 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 869 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–140. EP3SE260 Row Pins Input Timing Parameters (Part 3 of 3) Fast Model I/O Standard Clock Parameter Units Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — -0.971 — -1.364 -1.488 -1.423 -1.866 1.5-V SSTL...
Page 870 — 2.718 2.795 2.753 2.772 CLASS I DIFFERENTIAL 10mA GCLK — 3.126 — 5.607 5.956 5.777 6.147 1.2-V HSTL GCLK — 1.456 — 2.720 2.797 2.755 2.774 CLASS I 1–358 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 871 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–141. EP3SE260 Column Pins Output Timing Parameters (Part 2 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL 12mA GCLK —...
Page 872 1.447 — 2.699 2.776 2.734 2.753 CLASS II DIFFERENTIAL GCLK — 3.128 — 5.611 5.960 5.781 6.151 1.8-V SSTL GCLK — 1.458 — 2.724 2.801 2.759 2.778 CLASS I 1–360 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 873 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–141. EP3SE260 Column Pins Output Timing Parameters (Part 4 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 3.121 —...
Page 874 GCLK — 1.517 — 2.856 2.929 2.891 2.876 DIFFERENTIAL GCLK — 3.117 — 5.592 5.936 5.761 6.099 1.2-V HSTL GCLK — 1.458 — 2.716 2.788 2.751 2.736 CLASS I 1–362 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 875 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–142. EP3SE260 Row Pins Output Timing Parameters (Part 2 of 4) Fast Model Current I/O Standard Clock Parameter Units Strength Industrial Commercial 1.1V 1.1V 1.1V 1.1V 0.9V DIFFERENTIAL GCLK — 3.109 —...
Page 876 1.438 — 2.669 2.740 2.703 2.689 CLASS II DIFFERENTIAL GCLK — 3.103 — 5.563 5.906 5.731 6.070 2.5-V SSTL GCLK — 1.446 — 2.687 2.758 2.721 2.707 CLASS I 1–364 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 877 GCLK values. These adder values are used to determine I/O timing when I/O pin is driven using regional clock. This applies for all I/O standards supported by Stratix III devices. Table 1–143 specifies EP3SE260 Column Pin delay adders when using the Regional Clock.
Page 878 0.103 Dedicated Clock Pin Timing Table 1–145 Table 1–205 show clock pin timing for Stratix III devices when the clock is driven by global clock, regional clock, periphery clock and a PLL. Table 1–145 describes Stratix III clock timing parameters.
Page 879 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–147. EP3SL50 Row Pin Global Clock Timing Specifications Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V tcin — 1.549 2.340 2.569 2.747 2.654 2.906...
Page 880 2.429 2.699 2.912 2.800 3.240 tcout — 1.565 2.429 2.699 2.912 2.800 3.240 tpllcin — 0.393 0.569 0.634 0.629 0.628 0.887 tpllcout — 0.393 0.569 0.634 0.629 0.628 0.887 1–368 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 881 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–153. EP3SL70 Row Pin Global Clock Timing Specifications Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V tcin — 1.549 2.340 2.569 2.750 2.654 2.906...
Page 882 2.785 3.077 3.311 3.192 3.743 tcout — 1.802 2.785 3.077 3.311 3.192 3.743 tpllcin — 0.346 0.505 0.568 0.566 0.563 0.834 tpllcout — 0.346 0.505 0.568 0.566 0.563 0.834 1–370 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 883 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–159. EP3SL110 Row Pin Global Clock Timing Specifications Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V tcin — 1.775 2.675 2.926 3.124 3.026 3.354...
Page 884 2.772 3.098 3.299 3.200 3.743 tcout — 1.795 2.772 3.098 3.299 3.200 3.743 tpllcin — 0.338 0.495 0.580 0.551 0.563 0.834 tpllcout — 0.338 0.495 0.585 0.551 0.563 0.834 1–372 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 885 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–165. EP3SL150 Row Pin Global Clock Timing Specifications Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V tcin — 1.772 2.675 2.926 3.124 3.026 3.340...
Page 886 3.107 3.409 3.657 3.556 4.169 tcout — 2.028 3.107 3.409 3.657 3.556 4.169 tpllcin — 0.343 0.482 0.508 0.497 0.526 0.789 tpllcout — 0.343 0.482 0.508 0.497 0.526 0.789 1–374 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 887 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–171. EP3SL200 Row Pin Global Clock Timing Specifications Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V tcin — 1.992 2.998 3.275 3.501 3.382 3.803...
Page 888 — 3.537 3.794 3.674 4.338 tcout — 2.098 — 3.537 3.794 3.674 4.338 tpllcin — 0.337 — 0.539 0.530 0.548 0.834 tpllcout — 0.337 — 0.539 0.530 0.548 0.834 1–376 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 889 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–177. EP3SL340 Row Pin Global Clock Timing Specifications Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V tcin — 2.116 — 3.446 3.676 3.555 4.008...
Page 890 2.467 2.746 2.960 2.847 3.321 tcout — 1.596 2.467 2.746 2.960 2.847 3.321 tpllcin — 0.414 0.590 0.662 0.669 0.660 0.953 tpllcout — 0.414 0.590 0.662 0.668 0.660 0.953 1–378 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 891 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–183. EP3SE50 Row Pin Global Clock Timing Specifications Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V tcin — 1.556 2.349 2.572 2.753 2.657 2.909...
Page 892 2.807 3.126 3.365 3.245 3.785 tcout — 1.816 2.807 3.126 3.365 3.245 3.785 tpllcin — 0.350 0.519 0.556 0.574 0.579 0.818 tpllcout — 0.350 0.519 0.556 0.574 0.579 0.818 1–380 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 893 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–189. EP3SE80 Row Pin Global Clock Timing Specifications Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V tcin — 1.802 2.718 2.967 3.172 3.073 3.410...
Page 894 2.825 3.123 3.365 3.276 3.814 tcout — 1.828 2.825 3.123 3.365 3.276 3.814 tpllcin — 0.353 0.515 0.577 0.574 0.603 0.816 tpllcout — 0.353 0.515 0.577 0.574 0.603 0.816 1–382 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 895 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–195. EP3SE110 Row Pin Global Clock Timing Specifications Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V tcin — 1.809 2.725 2.982 3.185 3.084 3.425...
Page 896 — 3.409 3.657 3.556 4.169 tcout — 2.028 — 3.409 3.657 3.556 4.169 tpllcin — 0.343 — 0.508 0.497 0.526 0.789 tpllcout — 0.343 — 0.508 0.497 0.526 0.789 1–384 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 897 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–201. EP3SE260 Row Pin Global Clock Timing Specifications Fast Model Parameter Units Industrial Commercial V =1.1V V =1.1V V =1.1V V =1.1V V =0.9V tcin — 1.992 — 3.275 3.501 3.382 3.803...
Page 898 — 2.078 2.233 2.150 2.343 tcout — 1.008 — 1.797 1.933 1.860 2.062 tpllcin — 0.301 — 0.375 0.329 0.345 0.427 tpllcout — 0.102 — 0.094 0.029 0.055 0.146 1–386 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 899 Stratix III Device Datasheet: DC and Switching Characteristics Glossary Table 1–206 shows the glossary for this chapter. Table 1–206. Glossary Table Letter Subject Definitions — — — — — — Differential I/O Receiver Input Waveforms Standards Single-Ended Waveform Positive Channel (p) = V...
Page 900 HIGH-SPEED I/O Block: Deserialization factor (width of parallel data bus). JTAG Timing JTAG Timing Specifications are in the following figure: Specifications JPSU JPZX JPXZ JPCO — — — — — — — — — — 1–388 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 901 Reconfigurable in User Mode Note: CoreClock can only be fed by dedicated clock input pins or PLL outputs. — — Receiver differential input discrete resistor (external to Stratix III device). Altera Corporation 1–389 November 2007 Stratix III Device Handbook, Volume 2...
Page 902 This approach is intended to provide predictable receiver timing in the presence of input waveform ringing (The following figure): Single-Ended Voltage Referenced I/O Standard CCIO IH ( AC ) IH(DC) IL(DC) IL(AC ) 1–390 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...
Page 903 Stratix III Device Datasheet: DC and Switching Characteristics Table 1–206. Glossary Table Letter Subject Definitions High-speed receiver/transmitter input and output clock period. TCCS (channel- The timing difference between the fastest and the slowest output edges, including to-channel- variation and clock skew, across channels driven by the same PLL. The clock is...
Page 904 Added new contact information table to the About this Handbook — v1.3 section. May 2007 Updated Table 1–44 through Table 1–205. — v1.2 March 2007 Added I/O Timing section — v1.1 November 2006 Initial Release — v1.0 1–392 Altera Corporation Stratix III Device Handbook, Volume 2 November 2007...