Board Component Blocks - Altera Cyclone III Reference Manual

General Description
1–2
Cyclone III FPGA Starter Board Reference Manual

Board Component Blocks

■
Altera Cyclone III EP3C25F324 FPGA
25K logic elements (LEs)
●
66 M9K memory blocks (0.6 Mb)
●
16 18x18 multiplier blocks
●
Four PLLs
●
214 I/Os
●
■
Clock management system
One 50-MHz clock oscillator to support a variety of protocols
●
The Cyclone III device distributes the following clocks from its
●
on-board PLLs:
• DDR clock
• SSRAM clock
• Flash clock
■
HSMC connector
Provides 12 V and 3.3 V interface for installed daughtercards
●
Provides up to 84 I/O pins for communicating with HSMC
●
daughtercards
■
General user-interface
Four user LEDs
●
Two board-specific LEDs
●
Push-buttons:
●
• System reset
• User reset
• Four general user push-buttons
■
Memory subsystem
Synchronous SRAM device
●
• 1-MB standard synchronous SRAM
• 167-MHz
• Shares bus with parallel flash device
Parallel flash device
●
• 16-MB device for active parallel configuration and storage
• Shares bus with SRAM device
DDR SDRAM device
●
• 56-pin, 32-MB DDR SDRAM
• 167-MHz
• Connected to FPGA via dedicated 16-bit bus
■
Built-in USB-Blaster interface
With the Altera EPM3128A CPLD
●
For external configuration of Cyclone III device
●
For system debugging with the SignalTap
●
debugging console
Communications port for Board Diagnostic graphical user
●
interface (GUI)
® ®
and Nios
Altera Corporation
April 2012