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MAX 10 series
Altera MAX 10 series FPGA Development Kit Manuals
Manuals and User Guides for Altera MAX 10 series FPGA Development Kit. We have
5
Altera MAX 10 series FPGA Development Kit manuals available for free PDF download: User Manual
Altera MAX 10 series User Manual (65 pages)
High-Speed LVDS I/O
Brand:
Altera
| Category:
I/O Systems
| Size: 0.53 MB
Table of Contents
Table of Contents
2
MAX 10 High-Speed LVDS I/O Overview
4
Altera Soft LVDS Implementation Overview
5
MAX 10 High-Speed LVDS Architecture and Features
6
MAX 10 LVDS Channels Support
6
MAX 10 LVDS SERDES I/O Standards Support
12
MAX 10 High-Speed LVDS Circuitry
15
MAX 10 High-Speed LVDS I/O Location
16
Differential I/O Pins in Low Speed Region
19
MAX 10 LVDS Transmitter Design
21
High-Speed I/O Transmitter Circuitry
21
LVDS Transmitter Programmable I/O Features
21
Programmable Pre-Emphasis
21
Programmable Differential Output Voltage
22
LVDS Transmitter I/O Termination Schemes
23
Emulated LVDS External Termination
23
Sub-LVDS Transmitter External Termination
23
SLVS Transmitter External Termination
24
Emulated RSDS, Emulated Mini-LVDS, and Emulated PPDS Transmitter External Termination
24
LVDS Transmitter FPGA Design Implementation
25
Altera Soft LVDS IP Core in Transmitter Mode
26
High-Speed I/O Timing Budget
28
Guidelines: LVDS Transmitter Channels Placement
29
Guidelines: LVDS Channels PLL Placement
29
Guidelines: LVDS Transmitter Logic Placement
29
Guidelines: Enable LVDS Pre-Emphasis for E144 Package
30
LVDS Transmitter Debug and Troubleshooting
30
Perform RTL Simulation before Hardware Debug
30
Geometry-Based and Physics-Based I/O Rules
30
MAX 10 LVDS Receiver Design
31
High-Speed I/O Receiver Circuitry
31
Soft Deserializer
31
Data Realignment Block (Bit Slip)
32
LVDS Receiver I/O Termination Schemes
32
LVDS, Mini-LVDS, and RSDS Receiver External Termination
33
SLVS Receiver External Termination
33
Sub-LVDS Receiver External Termination
33
TMDS Receiver External Termination
34
Hispi Receiver External Termination
34
LVPECL External Termination
35
LVDS Receiver FPGA Design Implementation
36
Altera Soft LVDS IP Core in Receiver Mode
36
High-Speed I/O Timing Budget
39
Guidelines: Floating LVDS Input Pins
43
Guidelines: LVDS Receiver Channels Placement
43
Guidelines: LVDS Channels PLL Placement
43
Guidelines: LVDS Receiver Logic Placement
44
Guidelines: LVDS Receiver Timing Constraints
44
LVDS Receiver Debug and Troubleshooting
44
Perform RTL Simulation before Hardware Debug
44
Geometry-Based and Physics-Based I/O Rules
44
MAX 10 LVDS Transmitter and Receiver Design
46
Transmitter-Receiver Interfacing
46
LVDS Transmitter and Receiver FPGA Design Implementation
47
LVDS Transmitter and Receiver PLL Sharing Implementation
47
Initializing the Altera Soft LVDS IP Core
48
LVDS Transmitter and Receiver Debug and Troubleshooting
48
Perform RTL Simulation before Hardware Debug
48
Geometry-Based and Physics-Based I/O Rules
48
MAX 10 High-Speed LVDS Board Design Considerations
49
Guidelines: Improve Signal Quality
49
Guidelines: Control Channel-To-Channel Skew
49
Guidelines: Determine Board Design Constraints
50
Guidelines: Perform Board Level Simulations
50
Altera Soft LVDS IP Core References
52
Altera Soft LVDS Parameter Settings
52
Altera Soft LVDS Interface Signals
58
MAX 10 High-Speed LVDS I/O User Guide Archives
62
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Altera MAX 10 series User Manual (67 pages)
FPGA Development kit
Brand:
Altera
| Category:
Microcontrollers
| Size: 2.85 MB
Table of Contents
Table of Contents
2
Overview
4
General Description
5
Handling the Board
7
Getting Started
8
Quartus II Web Edition Software
8
Installing the Development Kit
8
Installing the USB-Blaster Driver
9
Board Update Portal
9
Board Test System
11
Using the Configure Menu
13
The System Info Tab
15
The GPIO Tab
17
The Flash Tab
19
The HSMC Tab
21
The DDR3 Tab
23
The ADC Tab
25
The HDMI Tab
27
The Sleep Mode Tab
28
The Power Monitor
30
The Clock Control
32
Board Components
35
Board Overview
35
Featured Device
37
Configuration
38
Using the Quartus II Programmer
38
Selecting the Internal Configuration Scheme
38
Switch and Jumper Settings
39
Status Elements
41
Setup Elements
42
General User Input/Output
42
Clock Circuitry
43
On-Board Oscillators
44
Off-Board Clock Input/Output
45
Components and Interfaces
46
10/100/1000 Ethernet PHY
46
Digital-To-Analog Converter
49
HDMI Video Output
50
Hsmc
51
Pmod Connectors
56
USB to UART
57
Memory
58
DDR3 Rev. B Board
58
DDR3 Rev. C Board
60
Flash
63
Power Distribution System
65
Additional Information
66
User Guide Revision History
66
Compliance and Conformity Statements
67
CE EMI Conformity Caution
67
Altera MAX 10 series User Manual (53 pages)
External Memory Interface
Brand:
Altera
| Category:
Recording Equipment
| Size: 1.7 MB
Table of Contents
Table of Contents
2
MAX 10 External Memory Interface Overview
4
MAX 10 External Memory Interface Support and Performance
5
MAX 10 External Memory Interface Architecture and Features
6
MAX 10 I/O Banks for External Memory Interface
6
MAX 10 DQ/DQS Groups
7
MAX 10 External Memory Interfaces Maximum Width
8
MAX 10 Memory Controller
10
MAX 10 External Memory Read Datapath
11
DDR Input Registers
12
MAX 10 External Memory Write Datapath
13
DDR Output Registers
13
MAX 10 Address/Command Path
15
MAX 10 PHY Clock (PHYCLK) Network
16
Phase Detector for VT Tracking
17
On-Chip Termination
17
Phase-Locked Loop
18
MAX 10 Low Power Feature
18
MAX 10 External Memory Interface Design Considerations
19
MAX 10 DDR2 and DDR3 Design Considerations
19
DDR2/DDR3 External Memory Interface Pins
19
DDR2/DDR3 Recommended Termination Schemes for MAX 10 Devices
21
LPDDR2 Design Considerations
22
LPDDR2 External Memory Interface Pins
22
LPPDDR2 Power Supply Variation Constraint
23
LPDDR2 Recommended Termination Schemes for MAX 10 Devices
24
Guidelines: MAX 10 DDR3, DDR2, and LPDDR2 External Memory Interface I/O Limitation
24
Guidelines: MAX 10 Board Design Requirement for DDR2, DDR3, and LPDDR2
26
Guidelines: Reading the MAX 10 Pin-Out Files
26
MAX 10 External Memory Interface Implementation Guides
27
Uniphy IP Core
27
LPDDR2 External Memory Interface Implementation
29
Supported LPDDR2 Topology
29
DDR2 and DDR3 External Memory Interface Implementation
30
MAX 10 Supported DDR2 or DDR3 Topology
30
Uniphy Parameter Settings for MAX 10
32
Uniphy Parameters-PHY Settings
32
Uniphy IP Core References for MAX 10
32
Uniphy Parameters-Memory Parameters
34
Uniphy Parameters-Memory Timing
38
Uniphy Parameters-Board Settings
40
Uniphy Parameters-Controller Settings
46
Uniphy Parameters-Diagnostics
49
MAX 10 External Memory Interface User Guide Archives
50
Additional Information for MAX 10 External Memory Interface User Guide
51
Document Revision History for MAX 10 External Memory Interface User Guide
51
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Altera MAX 10 series User Manual (32 pages)
User Flash Memory
Brand:
Altera
| Category:
Storage
| Size: 0.9 MB
Table of Contents
Table of Contents
2
MAX 10 User Flash Memory Overview
3
MAX 10 UFM Architecture and Features
4
UFM and CFM Array Size
4
UFM Memory Organization Map
5
UFM Block Diagrams
5
UFM Operating Modes
8
MAX 10 UFM Design Considerations
10
Guideline: UFM Power Supply Requirement
10
Guideline: Program and Read UFM with JTAG
10
Guideline: UFM Content Initialization
11
Guideline: Erase before Program
11
MAX 10 UFM Implementation Guides
12
Altera On-Chip Flash IP Core
12
UFM Avalon-MM Operating Modes
12
UFM Read Status and Control Register
12
UFM Write Control Register
13
UFM Program (Write) Operation
13
UFM Sector Erase Operation
15
UFM Page Erase Operation
15
UFM Read Operation
16
UFM Burst Read Operation
18
Flash Initialization Files
23
Altera On-Chip Flash IP Core References
24
Altera On-Chip Flash Parameters
24
Altera On-Chip Flash Signals
25
Altera On-Chip Flash Registers
27
MAX 10 User Flash Memory User Guide Archive
30
Document Revision History for MAX 10 User Flash Memory User Guide
31
Altera MAX 10 series User Manual (22 pages)
FPGA Power Management
Brand:
Altera
| Category:
Microcontrollers
| Size: 0.8 MB
Table of Contents
Table of Contents
2
MAX 10 Power Management Overview
3
MAX 10 Power Management Features and Architecture
3
Power Supply Device Options
4
Single-Supply Device
4
Dual-Supply Device
4
Comparison of the MAX 10 Power Supply Device Options
5
Power Supply Design
6
Power-On Reset Circuitry
7
Power Supplies Monitored and Not Monitored by the por Circuitry
8
Instant-On Support
10
Power Management Controller Scheme
10
Power Management Controller Architecture
10
Hot Socketing
12
Hot-Socketing Specifications
12
Hot-Socketing Feature Implementation
13
Hot-Socketing Feature Implementation
14
Power Management Controller Reference Design
15
Clock Control Block
16
I/O Buffer
16
Internal Oscillator
16
Power Management Controller
16
Entering State
17
Sleep State
17
Exiting State
17
Awake State
17
Entering or Exiting Sleep Mode
17
Entering Sleep Mode
18
Exiting Sleep Mode
18
Timing Parameters
19
Hardware Implementation and Current Measurement
19
Additional Information for MAX 10 Power Management User Guide
22
Document Revision History for MAX 10 Power Management User Guide
22
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