Intel Stratix 10 User Manual page 88

Figure 50. REFCLK LVPECL Pins
This diagram illustrates the nine
Tile.
Reference clock network within an E-Tile
Nine REFCLK LVPECL Pins
For details on LVPECL standard spec, refer to Intel Stratix 10 Device Datasheet.
Related Information
• PMA Analog Reset
• Register Map
• Intel Stratix 10 Device Datasheet
• Intel Stratix 10 Device Family Pin Connection Guidelines
• My Intel support
® ®
Intel Stratix 10 E-Tile Transceiver PHY User Guide
88
pins and the reference clock network within a given Intel Stratix 10 E-
refclk
+
+
+ Divide
+
Divide
+ by 2
LVPECL Divide
+ by 2 Divide
LVPECL
Divide
LVPECL + by 2
+ by 2
LVPECL
Divide
LVPECL + by 2
– Divide
by 2 Divide
– LVPECL
Divide
LVPECL by 2
–
by 2
– LVPECL
LVPECL by 2 REFCLK_8
–
–
–
–
–
on page 104
on page 165
refclk_in_A
refclk_in_B
refclk_in_A
refclk_in_B
REFCLK_0
4. Clock Network
UG-20056 | 2019.02.04
Transceiver
Transmitter
Receiver
Channels
23 to 0
Transceiver
Transmitter
Receiver
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