Design Description; Figure 3 Libero Smartdesign - Microsemi SmartFusion2 Demo Manual

SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo
2.2.1.3.2 Ethernet Packet Transmission
To loop back the Ethernet packet, the Cortex-M3processor reads the Ethernet packet data from LSRAM
memory through AHB interface and forwards it to it on the CoreTSE_AHB transmit (TX) path.
CoreTSE_AHB transmits the Ethernet packet to the on-board Ethernet PHY through high-speed
SERDES.
2.2.1.4 Ethernet Test Solution
There are many ways to evaluate the CoreTSE_AHB 1000 Base-T loopback demo on the SmartFusion2
Security Evaluation board.
2.2.1.4.1 Solution 1
• The Cat Karat packet generator software installed on the host PC is used to transmit the Ethernet
packet through RJ45 Ethernet copper cable.
• The Wireshark packet receiver software installed on the host PC captures the Ethernet packet
(loopback) through RJ45 Ethernet copper cable.
2.2.1.4.2 Solution 2
Spirent test center or an equivalent solution can be used to test the CoreTSE_AHB loopback demo. For
more information, see
2.2.2

Design Description

This demo design is implemented by configuring the CoreTSE_AHB for the TBI mode. The following
figure shows the Libero SoC hardware implementation for this demo design.
Figure 3 • Libero SmartDesign
Libero hardware project uses the following resources:
• CoreTSE_AHB
• Cortex M3 (microcontroller sub system) to configure CoreTSE_AHB and on-board Ethernet PHY
• High-speed serial interface (SERDES_IF) configured for EPCS lane 3 mode
• SoftConsole - application for initializing the CoreTSE_AHB and for transferring the Ethernet packet
data to/from LSRAM
• Dedicated input pad 0 as the clock source
Appendix: Running the Demo Design Using Spirent Test Center,
DG0637 Demo Guide Revision 3.0
page 14.
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