Microsemi SmartFusion2 Demo Manual
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Microsemi SmartFusion2 Demo Manual

Soc fpga code shadowing from emmc device to ddr memory - libero soc v11.4
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Download this manual See also: Configuration Manual, Demo Manual
SmartFusion2 SoC FPGA Code
Shadowing from eMMC Device to DDR
Memory - Libero SoC v11.4
Demo Guide
August 2014

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Summary of Contents for Microsemi SmartFusion2

  • Page 1 SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide August 2014...
  • Page 2 SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide Revision History Date Revision Change 28 August 2014 Second release 16 April 2014 First release Confidentiality Status This is a non-confidential document.

  • Page 3: Table Of Contents

    Publications ................4 SmartFusion2 SoC FPGA - Code Shadowing from eMMC Device to DDR Memory ....5 Introduction .

  • Page 4: Preface

    SmartFusion2 SoC FPGA Remapping eNVM, eSRAM, and DDR/SDR SDRAM Memories Application Note • Configuring Serial Terminal Emulation Programs Tutorial Refer to the following web page for a complete and up-to-date listing of SmartFusion2 device www.microsemi.com/products/fpga-soc/soc-fpga/sf2docs#documents documentation: R ev is i on 2...

  • Page 5: Smartfusion2 Soc Fpga - Code Shadowing From Emmc Device To Ddr Memory

    Cortex -M3 processor, and high performance communication interfaces on a single chip. The high speed memory controllers in the SmartFusion2 SoC FPGA devices are used to interface with the external DDR2/DDR3/LPDDR memories. The DDR2/DDR3 memories can be operated at maximum speed of 333 MHz.

  • Page 6: Demo Design

    HyperTerminal • TeraTerm • PuTTY Demo Design Introduction ® The demo design files are available for download from the following path in the Microsemi website: http://soc.microsemi.com/download/rsc/?f=SF2_CODE_SHADOWING_DDR_EMMC_11p4_DF The demo design files include: • Libero SoC project • STAPL programming files •...

  • Page 7: Demo Design Description

    SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide Demo Design Description This demo design implements code shadowing technique to boot the application image from DDR memory. The design also provides host interface over SmartFusion2 SoC FPGA multi-mode universal asynchronous/synchronous receiver/transmitter (MMUART) to load the target application executable image (*.bin) to the on-board eMMC.
  • Page 8 UART interface with host PC. The DIP switch1 on the SmartFusion2 Development Kit can be used to select whether to program the eMMC device or to execute the code from DDR memory.
  • Page 9 SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide If the executable target application is available in eMMC device, the code shadowing from eMMC device to DDR memory is started on device power-up. The boot engine initializes the MDDR, copies the Image from eMMC device to DDR memory, and remaps the DDR memory space to 0x00000000 by keeping the Cortex-M3 processor in reset.
  • Page 10 SmartFusion2 SoC FPGA - Code Shadowing from eMMC Device to DDR Memory The demo design flow is described in Figure Figure 5 • Design Flow for Hardware Boot Engine Method Creating Target Application Image for DDR Memory A target application image is executed from the DDR memory in this demo. The linker description file (included in the design files) is used to build production-execute-in-place-externalDDRorSDR.ld...

  • Page 11: Setting Up The Demo Design

    SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide eMMC Host PC Loader The eMMC host PC loader is implemented to transfer the executable target application image (*.bin) from the host PC to SmartFusion2 on-board eMMC device using MMUART_0 interface. The file is executed from the host PC command prompt.
  • Page 12 SmartFusion2 SoC FPGA - Code Shadowing from eMMC Device to DDR Memory 6. Connect the jumpers on the SmartFusion2 SoC FPGA Development Kit, as shown in Table While making the jumper connections, the power supply switch SW7 on the board should be in OFF position.

  • Page 13: Running The Demo Design For Multi-Stage Boot Process Method

    SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide Running the Demo Design for Multi-Stage Boot Process Method 1. Download the demo design from: http://soc.microsemi.com/download/rsc/?f=SF2_CODE_SHADOWING_DDR_EMMC_11p4_DF 2. Start any serial terminal emulation program such as: –...
  • Page 14 SmartFusion2 SoC FPGA - Code Shadowing from eMMC Device to DDR Memory 6. In the New Project window, type the project name. Figure 8 • FlashPro New Project 7. Click Browse and navigate to the location where the project needs to be saved.
  • Page 15 SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide 11. Click Browse and navigate to the location where the file is located and code_shadow_top.stp select the file. The default location is: <download_folder>\sf2_code_shadowing_to_ddr_from_emmc_df\stapl_programming_file\MultiSt ageBoot_method.
  • Page 16 SmartFusion2 SoC FPGA - Code Shadowing from eMMC Device to DDR Memory 12. Click PROGRAM to start programming the device. Figure 10 • Programming the Device Revisi on 2...
  • Page 17 SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide 13. Wait until a message is displayed, indicating that the program has passed. This demo requires the SmartFusion2 device to be programmed with the application, which runs from eNVM, to perform the code shadowing from eMMC to DDR3 memory.
  • Page 18 SmartFusion2 SoC FPGA - Code Shadowing from eMMC Device to DDR Memory The serial terminal emulation program displays the options as shown in Figure Figure 12 • Demo Options 15. Type 1 to copy the sample application image (*.bin) file to the eMMC device from host PC using UART interface.
  • Page 19 SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide 19. Run the file and launch the eMMC host PC loader to transfer the sample m2s_emmc_loader.exe application image file from host PC to SmartFusion2 on board eMMC device using UART interface.
  • Page 20 SmartFusion2 SoC FPGA - Code Shadowing from eMMC Device to DDR Memory 21. Type 2 to boot from DDR memory. The application running from SmartFusion2 eNVM copies the eMMC device contents to DDR memory and runs the bootloader function to jump the execution...

  • Page 21: Running The Demo Design For Hardware Boot Engine Method

    SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide Running the Demo Design for Hardware Boot Engine Method 1. Program the SmarFusion2 SoC FPGA device with the programming file provided in the design files, <download_folder>\\sf2_code_shadowing_to_ddr_from_emmc_df\stapl_programming_file\HWB...

  • Page 22: Appendix 1: Ddr Configurations

    SmartFusion2 SoC FPGA - Code Shadowing from eMMC Device to DDR Memory Appendix 1: DDR Configurations Figure Figure 19, and Figure 20 on page 23 show the DDR3 configuration settings. For more information, refer to SmartFusion2 SoC FPGA High Speed DDR Interfaces User Guide.
  • Page 23 SmartFusion2 SoC FPGA Code Shadowing from eMMC Device to DDR Memory - Libero SoC v11.4 Demo Guide Figure 20 • DDR Memory Timing Settings Revision 2...

  • Page 24: Appendix 2: Generating Executable Bin File

    SmartFusion2 SoC FPGA - Code Shadowing from eMMC Device to DDR Memory Appendix 2: Generating Executable Bin File The executable bin file is required to program the eMMC for running the code shadowing demo. To generate the executable bin file from SoftConsole, perform the following steps: 1.

  • Page 25: List Of Changes

    List of Changes The following table lists critical changes that were made in each revision of the chapter in the demo guide. Date Changes Page Revision 2 Updated the document for Libero v11.4 software release (SAR 60349). (August 2014) Revision 1 Initial release.

  • Page 26: Product Support

    Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creating application notes, answers to common design cycle questions, documentation of known issues, and various FAQs.

  • Page 27: My Cases

    For technical support on RH and RT FPGAs that are regulated by International Traffic in Arms Regulations (ITAR), contact us via soc_tech_itar@microsemi.com. Alternatively, within Cases, select Yes in the ITAR drop-down list. For a complete list of ITAR-regulated Microsemi FPGAs, visit the ITAR web page.
  • Page 28 Within the USA: +1 (949) 380-6100 Sales: +1 (949) 380-6136 © 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of Fax: +1 (949) 215-4996 Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.

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