Page 1 UG0331 User Guide SmartFusion2 Microcontroller Subsystem...
Page 2 Within the USA: +1 (800) 713-4113 with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this...
Page 3: Table Of Contents
Contents 1 Revision History ........... . . 1 Revision 15.0 .
Page 4 3.6.4 Memory Access Instructions ..........58 3.6.5 General Data processing instructions .
Page 5 Functional Description ............. 211 7.1.1 Architecture Overview .
Page 6 10.3.15 USB System Registers ........... . . 371 11 Ethernet MAC .
Page 7 13.1 Features ............... . 469 13.2 Functional Description .
Page 8 15.4 C Register Map ..............550 15.4.1 Control Register .
Page 9 18.3 How to Use RTC ..............605 18.3.1 Design Flow .
Page 10 21.2 Power-Up to Functional Time Data ........... 646 21.2.1 Parameters Used for Obtaining Power-Up to Functional Time Data .
Page 11 22.3.33 eSRAM PIPELINE Configuration Register ........701 22.3.34 RTC Wake Up Configuration Register .
Page 12 22.3.92 User Configuration Register 2 ..........728 22.3.93 User Configuration Register 3 .
Page 13 26 Error Detection and Correction Controllers ......792 26.1 Functional Description ............. 792 26.1.1 EDAC Checksum Bits Width .
Page 14 Figures Figure 1 Cortex-M3 Processor R2P1 Block Diagram as Implemented in the SmartFusion2 SoC FPGA ..7 Figure 2 Trace System Block Diagram ........... . . 14 Figure 3 CM3 Configurator .
Page 15 Figure 55 SRD Field ..............131 Figure 56 Cache Controller Interfaces to Cortex-M3 Processor, AHB Bus Matrix, and MDDR Bridge .
Page 16 USB OTG Controller in SmartFusion2 ........
Page 17 Figure 172 Extra Connection to Fabric and GPIO Options ........444 Figure 173 Enabling EDAC for the CAN from the SECDED Configurator .
Page 18 Reset Signals Distribution in SmartFusion2 Devices ........
Page 19 Figure 289 M3_SYS_RESET_N Generation ..........657 Figure 290 MDDR_AXI_RESET_N Generation .
Page 20 Figure 344 Master/AHB-Lite Master Access Configuration ........770 Figure 345 FIC Master/AHB-Lite Subsystem .
Page 21 Tables Table 1 Cortex-M3 Processor Exceptions ........... 8 Table 2 Cortex-M3 Processor Interrupts .
Page 22 Table 55 AIRCR Bit Assignments ............107 Table 56 Priority Grouping .
Page 23 Table 114 NV_FREQRNG Calculations at Different M3_CLK Frequencies for All SmartFusion2 Devices . . 185 Table 115 NV_PAGE_STATUS ............185 Table 116 INTEN[10:0] .
Page 24 ULPI Interface Signals at SmartFusion2 External I/Os ....... . .
Page 25 Table 232 TX_INTERVAL_REG ............328 Table 233 Polling Intervals for Transfer Types .
Page 26 Table 291 Turnaround Timeout Period Settings ..........354 Table 292 DMA_REGISTER Description .
Page 27 Table 350 HALF_DUPLEX ............. . 404 Table 351 MAX_FRAME_LENGTH .
Page 28 Table 409 TMCL ..............422 Table 410 TLCL .
Page 29 Table 468 RBR ............... 491 Table 469 THR .
Page 30 Table 527 STATUS Register – Slave-Transmitter Mode ........556 Table 528 STATUS Register –...
Page 31 Table 586 IOMUX CELL 51 ............. . 590 Table 587 IOMUX CELL 52 .
Page 32 Table 645 VDD Power-Up to Functional Time ..........648 Table 646 DEVRST_N Power-Up to Functional Time .
Page 33 Table 704 CC_SB_ERR_ADDR_SR ............711 Table 705 CC_IC_MISS_CNTR_SR .
Page 34 SmartFusion2 SoC FPGA FIIC Register Map ........
Page 35: Revision History
The test cases listed in Table 645, page 648 were updated for consistency with DS0128: IGLOO2 and SmartFusion2 Datasheet. The VDD power-up to functional time flow diagram (Figure 282, page 650) was updated to include the POWER_ON_RESET_N signal. For more information, see VDD Power-Up to Functional Time, page 648.
Page 36: Revision 11.0
Updated System Register Block, page 670 (SAR 62544). • Added a reference to SmartFusion2 SoC FPGA High Speed DDR Interfaces User Guide in the HPDMA Use Models, page 245 (SAR 60106). Revision 7.0 The following changes were made in revision 3.0 of this document.
Page 37: Revision 5.0
Revision History 1.10 Revision 6.0 The following changes were made in revision 3.0 of this document. • Added a note to Trace Port Interface Unit (TPIU) Configuration, page 17 (SAR 55243). • Updated Table 3, page 14 and Table 4, page 15 (SAR 51221).
Page 38: Revision 3.0
Revision History • Updated Table 611, page 612 (SAR 42472). • Updated Power-On Reset, page 654 (SAR 45905). • Updated Table 650, page 676, Table 693, page 704, and Table 715, page 714 (SAR 48598). • Updated details for CC_EDAC_EN in Table 669, page 691 (SAR 48194).
Page 39 Revision History • Added Figure 328, page 761 through Figure 336, page 766 (SAR 39058). UG0331 User Guide Revision 15.0...
Page 40: Cortex-M3 Processor Overview And Debug Features
A memory protection unit (MPU) is included. This facilitates the protected memory regions creation and setting access rights for the protected regions. • A Cortex-M3 processor, which is configured for SmartFusion2 MSS, and uses only little-endian. • An auxiliary control register is included.
Page 41: Functional Description
Functional Description The following figure shows the Cortex-M3 processor, core peripherals and debug subsystem implementations used in SmartFusion2. Figure 1 • Cortex-M3 Processor R2P1 Block Diagram as Implemented in the SmartFusion2 SoC FPGA Cortex- M 3 Processor Interrupts and Nested Vector...
Page 42: Cortex-M3 Processor Nvic
Cortex-M3 Processor Overview and Debug Features Cortex-M3 Processor NVIC The Cortex-M3 processor contains an NVIC, which is responsible for: • Facilitating low-latency exception and interrupt handling • Controlling power management The NVIC supports 11 exceptions as shown in Table 1, page 8.
Page 43 Cortex-M3 Processor Overview and Debug Features Table 2 • Cortex-M3 Processor Interrupts (continued) Cortex-M3 Interrupt Signal Source Description INTISR[1] RTC_WAKEUP_INTR RTC match/wake up interrupt from RTC block INTISR[2] SPIINT0 SPI_0 Interrupt from SPI 0 INTISR[3] SPIINT1 SPI_1 Interrupt from SPI 1 INTISR[4] I2C_INT0 I2C_0...
Page 44 Cortex-M3 Processor Overview and Debug Features Table 2 • Cortex-M3 Processor Interrupts (continued) Cortex-M3 Interrupt Signal Source Description INTISR[25] CACHE_ERRINTR SYSREG If asserted, indicates that the interrupt is coming from CACHE. This interrupt is generated in the SysReg by ORing of the various interrupts from the CACHE block: CC_HRESPERRINT0, CC_HRESPERRINT1, CC_HRESPERRINT2, CC_HRESPERRINT3.
Page 45 Cortex-M3 Processor Overview and Debug Features Table 2 • Cortex-M3 Processor Interrupts (continued) Cortex-M3 Interrupt Signal Source Description INTISR[33] FIC64_INT SYSREG This interrupt will be generated by FIC64 when one of the following conditions is true: Write error for HPDMA or switch WCBs (from DDR_AXI_INTF) Simultaneous read and write accesses by HPDMA and switch for same address...
Page 46: Cortex-M3 Processor Systick Timer
Cortex-M3 Processor Overview and Debug Features Table 2 • Cortex-M3 Processor Interrupts (continued) Cortex-M3 Interrupt Signal Source Description INTISR[66] GPIO_INT[16] GPIO Interrupt from GPIO INTISR[67] GPIO_INT[17] GPIO Interrupt from GPIO INTISR[68] GPIO_INT[18] GPIO Interrupt from GPIO INTISR[69] GPIO_INT[19] GPIO Interrupt from GPIO INTISR[70] GPIO_INT[20] GPIO Interrupt from GPIO...
Page 47: Cortex-M3 Processor Trace System
Cortex-M3 Processor Overview and Debug Features • DO: SWO (output pin for SWV, refer to the next section). • SWV: It provides real-time data trace information from various sources within the Cortex-M3 processor device. This is output via the single serial wire output (SWO) pin while your system processor continues running at full speed.
Page 48: Figure 2 Trace System Block Diagram
FPGA Fabric The following table shows pin multiplexing details for JTAG, SWD, and ETM modes of the debug section. For more details on pin information, refer to the DS0115: SmartFusion2 Pin Descriptions Datasheet. Table 3 • Signal Multiplexing FPGA Pin...
Page 49: Cortex-M3 Processor Port Descriptions
Cortex-M3 Processor Overview and Debug Features Table 3 • Signal Multiplexing (continued) JTAG_TDO/ M3_TDO/ M3_SWO JTAG_TDI/ TRACECLK M3_TDI TRACEDATA[3:0] 2.5.2.1 Data Watch Point (DWP) and Trace The DWT unit is able to provide either focused data trace or global data trace. It has four comparators used to compare the following conditions: •...
Page 50: How To Use The Cortex-M3 Processor And The Debug Subsystem
Cortex-M3 Processor Overview and Debug Features Table 4 • Port Details of the Cortex-M3-Subsystem (continued) Port Name Direction Description DEEPSLEEP Signal is asserted when the Cortex-M3 processor is in sleep now or sleep- on-exit mode when the SLEEPDEEP bit of the system control register is set.
Page 51: Table 5 Mpu Configuration Register
Cortex-M3 Processor Overview and Debug Features 2.7.1.1 Memory Protection Unit The MPU can be enabled by the selection option provided, as shown in the preceding figure. The following table lists all the registers that can be used to configure the MPU for the creation of the protected memory regions and setting the privileges for the created memory region in the firmware.
Page 52: Cortex-M3 Processor (Reference Material)
The NVIC includes a non-maskable interrupt (NMI), and provides up to 256 interrupt priority levels. NVIC in SmartFusion2 SoC FPGA MSS is set to have 83 interrupts (including non-maskable interrupt).The tight integration of the processor core and NVIC provides fast execution of interrupt service routines (ISRs), dramatically reducing the interrupt latency.
Page 53: System Level Interface
Cortex-M3 Processor (Reference Material) code overhead from the ISRs. A Tail-chain optimization also significantly reduces the overhead when switching from one ISR to another. To optimize low-power designs, the NVIC integrates with the sleep modes, that include a deep sleep function that enables the entire device to be rapidly powered down while still retaining program state.
Page 54: Cortex-M3 Processor Core Peripherals
Cortex-M3 Processor (Reference Material) Cortex-M3 Processor Core Peripherals 3.4.1 Nested Vectored Interrupt Controller The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low latency interrupt processing. 3.4.2 System Control Block The System control block (SCB) is the programmers model interface to the processor. It provides system implementation information and system control, including configuration, control, and reporting of system exceptions.
Page 55: Figure 5 Core Register Set
Cortex-M3 Processor (Reference Material) In Thread mode, the CONTROL register controls whether the processor uses the main stack or the process stack, see CONTROL Register, page 27. In Handler mode, the processor always uses the main stack. The options for processor operations are: Table 7 •...
Page 56: Figure 6 Program Status Register
Cortex-M3 Processor (Reference Material) Table 8 • Core Register Set Summary (continued) Required Name Type privilege Reset value Description R0-R12 Either Unknown General-Purpose Registers EPSR Privileged 0x01000000 Execution Program Status Register PRIMASK Privileged 0x00000000 Priority Mask Register FAULTMASK RW Privileged 0x00000000 Fault Mask Register BASEPRI...
Page 57: Table 11 Ipsr Bit Assignments
Cortex-M3 Processor (Reference Material) Access these registers individually or as a combination of any two or all three registers, using the register name as an argument to the MSR or MRS instructions. For example: • Read all of the registers using PSR with the MRS instruction. •...
Page 58: Table 12 Epsr Bit Assignments
Cortex-M3 Processor (Reference Material) Table 11 • IPSR Bit Assignments Bits Name Function [8:0] ISR_NUMBER This is the number of the current exception: 0 = Thread mode 1 = Reserved 2 = NMI 3 = HardFault 4 = MemManage 5 = BusFault 6 = UsageFault 7-10 = Reserved 11 = SVCall...
Page 59: Figure 7 Priority Mask Register
Cortex-M3 Processor (Reference Material) Interruptible-continuable Instructions When an interrupt occurs during the execution of an LDM, STM, PUSH, or POP instruction, the processor: • Stops the load multiple or store multiple instruction operation temporarily • Stores the next register operand in the multiple operation to EPSR bits[15:12] After servicing the interrupt, the processor: •...
Page 60: Figure 8 Fault Mask Register
Cortex-M3 Processor (Reference Material) Fault Mask Register The FAULTMASK register prevents activation of all exceptions except for Non-Maskable Interrupt (NMI). See the register summary in Table 8, page 21 for its attributes. Reserved FAULTMASK Figure 8 • Fault Mask Register The following table lists the big assignments for MSR or MRS access.
Page 61: Figure 10 Control Register
Cortex-M3 Processor (Reference Material) 3.5.1.3.10 CONTROL Register The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. Refer to the register summary in Table 8, page 21 for its attributes. The following figure shows the bit assignments for MSR or MRS access.
Page 62 Instruction memory and Private Peripheral Bus (PPB) accesses are always performed as little-endian. The Cortex-M3 processor configured for SmartFusion2 SoC FPGA MSS uses only little-endian. Refer to Memory Regions, Types and Attributes, page 29.
Page 63: Memory Model
Cortex-M3 Processor (Reference Material) 3.5.2 Memory Model This section describes the processor memory map, the behavior of memory accesses, and the bit-banding features. The processor has a fixed memory map that provides up to 4GB of addressable memory. The following illustration shows the processor memory map. Figure 11 •...
Page 64: Figure 12 Memory Ordering Restrictions
Cortex-M3 Processor (Reference Material) The additional memory attributes include: Shareable: For a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller. Strongly-ordered memory is always shareable. If multiple bus masters can access a non-shareable memory region, software must ensure data coherency between the bus masters.
Page 65: Table 18 Memory Region Shareability And Cache Policies
Cortex-M3 Processor (Reference Material) Table 17 • Memory Access Behavior (continued) Address range Memory region Memory Type Description 0xE0000000- Private Peripheral Strongly- This region includes the NVIC, System timer, and 0xE00FFFFF ordered system control block. 0xE0100000- Vendor specific Device Accesses to this region are to vendor-specific 0xFFFFFFFF peripherals.
Page 66: Table 19 Sram Memory Bit-Banding Regions
Cortex-M3 Processor (Reference Material) Memory System Ordering of Memory Accesses, page 30 describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions: DMB: The Data Memory Barrier (DMB) instruction ensures that outstanding memory transactions complete before subsequent memory transactions.
Page 67: Figure 13 Bit-Band Mapping
Cortex-M3 Processor (Reference Material) The following formula shows how the alias region maps onto the bit-band region: • bit_word_offset = (byte_offset x 32) + (bit_number x 4) • bit_word_addr = bit_band_base + bit_word_offset where: • Bit_word_offset is the position of the target bit in the bit-band memory region. •...
Page 68: Figure 14 Byte-Invariant Big-Endian Format
In little-endian format, the processor stores the least significant byte of a word at the lowest-numbered byte, and the most significant byte at the highest-numbered byte. Cortex-M3 processor configured for SmartFusion2 SoC FPGA MSS uses only little endian. The following figure illustrates the little-endian format.
Page 69 Cortex-M3 Processor (Reference Material) 3.5.2.7.1 A Load-Exclusive Instruction Used to read the value of a memory location, requesting exclusive access to that location. 3.5.2.7.2 A Store-Exclusive Instruction Used to attempt to write to the same memory location, returning a status bit to a register. If this bit is: 0: it indicates that the thread or process gained exclusive access to the memory, and the write succeeds.
Page 70: Exception Model
Cortex-M3 Processor (Reference Material) 3.5.2.8 Programming Hints for the Synchronization Primitives ISO/IEC C cannot directly generate the exclusive access instructions. Some CMSIS provides intrinsic functions for generation of these instructions. The following table lists the functions that CMSIS provides. Table 21 • CMSIS Functions for Exclusive Access Instructions Instruction Intrinsic Function...
Page 71 Cortex-M3 Processor (Reference Material) MemManage: A MemManage fault is an exception that occurs because of a memory protection related fault. The MPU or the fixed memory protection constraints determines this fault, for both instruction and data memory transactions. This fault is always used to abort instruction accesses to Execute Never (XN) memory regions.
Page 72: Table 22 Properties Of The Different Exception Types
Cortex-M3 Processor (Reference Material) For an asynchronous exception, other than reset, the processor can execute another instruction between when the exception is triggered and when the processor enters the exception handler. Table 22 • Properties of the Different Exception Types Exception Vector address or number...
Page 73: Figure 16 Vector Table
Cortex-M3 Processor (Reference Material) 3.5.3.4 Vector Table The vector table contains the reset value of the stack pointer, and the start addresses, also called exception vectors, for all exception handlers. Figure 5, page 21 shows the order of the exception vectors in the vector table.
Page 74 Cortex-M3 Processor (Reference Material) If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs.
Page 75: Figure 17 Exception Entry Stack Contents
Cortex-M3 Processor (Reference Material) Sufficient priority means the exception has greater priority than any limit set by the mask register, see Exception Mask Registers, page 25. An exception with less priority than this is pending but is not handled by the processor. When the processor takes an exception, unless the exception is a tail-chained or a late-arriving exception, the processor pushes information onto the current stack.
Page 76: Fault Handling
Cortex-M3 Processor (Reference Material) When the processor loads a value matching this pattern to the PC it detects that the operation is a not a normal branch operation and, instead, that the exception is complete. Therefore, it starts the exception return sequence.
Page 77 Cortex-M3 Processor (Reference Material) Table 24 • Faults (continued) Fault Handler Bit name Fault status register Bus error: BusFault during exception STKERR BusFault Status Register stacking during exception UNSTKERR unstacking during instruction IBUSERR prefetch Precise data bus error PRECISERR Imprecise data bus IMPRECISERR error Attempt to access a...
Page 78: Power Management
Cortex-M3 Processor (Reference Material) even though the stack push for the handler failed. The fault handler operates but the stack contents are corrupted. Only Reset and NMI can preempt the fixed priority HardFault. A HardFault can preempt any exception other than Reset, NMI, or another HardFault. 3.5.4.3 Fault Status Registers and Fault Address Registers The fault status registers indicate the cause of a fault.
Page 79 Cortex-M3 Processor (Reference Material) instruction it stops executing instructions and enters sleep mode. See Wakeup from WFE, page 46 for more information. 3.5.5.1.2 Wait for Event The wait for event instruction, WFE, causes entry to sleep mode dependent on the value of a one-bit event register.
Page 80: Instruction Set Summary
Cortex-M3 Processor (Reference Material) 3.5.5.4 External Event Input The processor provides an external event input signal. Peripherals can drive this signal, either to wake the processor from WFE, or to set the internal WFE event register to one to indicate that the processor must not enter Sleep mode on a later WFE instruction.
Page 81: Cortex-M3 Processor Instruction Set
Cortex-M3 Processor (Reference Material) Table 26 • Cortex-M3 Processor Instructions (continued) Mnemonic Operands Brief description Flags Rd, Rm Count Leading Zeros Rn, Op2 Compare Negative N, Z, C, V Rn, Op2 Compare N, Z, C, V CPSID Change Processor State, Disable Interrupts CPSIE Change Processor State, Enable Interrupts Data Memory Barrier...
Page 82: Table 61 Table
Cortex-M3 Processor (Reference Material) Table 26 • Cortex-M3 Processor Instructions (continued) Mnemonic Operands Brief description Flags ORN, ORNS {Rd,} Rn, Op2 Logical OR NOT N, Z, C ORR, ORRS {Rd,} Rn, Op2 Logical OR N, Z, C reglist Pop registers from stack PUSH reglist Push registers onto stack...
Page 83: Table 352 Test
Cortex-M3 Processor (Reference Material) Table 26 • Cortex-M3 Processor Instructions (continued) Mnemonic Operands Brief description Flags [Rn, Rm, LSL #1] Table Branch Halfword Rn, Op2 Test Equivalence N, Z, C Rn, Op2 Test N, Z, C UBFX Rd, Rn, #lsb, #width Unsigned Bit Field Extract UDIV {Rd,} Rn, Rm...
Page 84: Cmsis Functions
Cortex-M3 Processor (Reference Material) The following table lists the functions that CMSIS provides for accessing the special registers using MRS and MSR instructions. Table 28 • CMSIS Functions to Access the Special Registers Special Register Access CMSIS function PRIMASK Read uint32_t __get_PRIMASK (void) Write void __set_PRIMASK (uint32_t value)
Page 85: About The Instruction Descriptions
Cortex-M3 Processor (Reference Material) • any constant of the form 0xXY00XY00 • any constant of the form 0xXYXYXYXY In the constants shown above, X and Y are hexadecimal digits. In addition, in a small number of instructions, constant can take a wider range of values. These are described in the individual instruction descriptions.
Page 86: Figure 18 Asr#3
Cortex-M3 Processor (Reference Material) You can use the ASR #n operation to divide the value in the register Rm by 2 , with the result being rounded towards negative-infinity. When the instruction is ASRS or when ASR #n is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to the last bit shifted out, bit[n-1], of the register Rm.
Page 87 Cortex-M3 Processor (Reference Material) 3.6.3.4.3 Logical shift left by n bits moves the right-hand 32-n bits of the register Rm, to the left by n places, into the left-hand 32-n bits of the result. And it sets the right-hand n bits of the result to 0. See Figure 20, page 54.
Page 88 Cortex-M3 Processor (Reference Material) 3.6.3.4.5 Rotate right with extend moves the bits of the register Rm to the right by one bit. And it copies the carry flag into bit[31] of the result. See the following figure. When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS, MVNS, ANDS, ORRS, ORNS, EORS, BICS, TEQ or TST, the carry flag is updated to bit[0] of the register Rm.
Page 89 Cortex-M3 Processor (Reference Material) You can execute an instruction conditionally, based on the condition flags set in another instruction, either: • Immediately after the instruction that updated the flags • After any number of intervening instructions that have not updated the flags. Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions.
Page 90: Table 29 Condition Code Suffixes
Cortex-M3 Processor (Reference Material) number of branch instructions in code. The table also shows the relationship between condition code suffixes and the N, Z, C, and V flags. Table 29 • Condition Code Suffixes Suffix Flags Meaning Z = 1 Equal Z = 0 Not equal...
Page 91: Memory Access Instructions
Cortex-M3 Processor (Reference Material) 3.6.3.8 Instruction Width Selection There are many instructions that can generate either a 16-bit encoding or a 32-bit encoding depending on the operands and destination register specified. For some of these instructions, you can force a specific instruction size by using an instruction width suffix.
Page 92 Cortex-M3 Processor (Reference Material) 3.6.4.1 Generate PC-relative address. 3.6.4.1.1 Syntax ADR{cond} Rd, label where: • cond is an optional condition code, see Conditional Execution, page • Rd is the destination register • label is a PC-relative expression. See PC-relative Expressions, page 55.
Page 93: Table 31 Offset Ranges
Cortex-M3 Processor (Reference Material) • Rt is the register to load or store. • Rn is the register on which the memory address is based. • offset is an offset from Rn. If offset is omitted, the address is the contents of Rn. •...
Page 94 Cortex-M3 Processor (Reference Material) • Rn must not be PC • Rn must be different from Rt and Rt2 in the pre-indexed or post-indexed forms. 3.6.4.2.4 Condition flags These instructions do not change the flags. Examples R8, [R10] ; Loads R8 from the address in R10. LDRNE R2, [R5, #960]! ;...
Page 95 Cortex-M3 Processor (Reference Material) 3.6.4.3.3 Restrictions In these instructions: • Rn must not be PC • Rm must not be SP and must not be PC • Rt can be SP only for word loads and word stores • Rt can be PC only for word loads. When Rt is PC in a word load instruction: •...
Page 96: Table 32 Offset Ranges
Cortex-M3 Processor (Reference Material) 3.6.4.4.3 Restrictions In these instructions: • Rn must not be PC. • Rt must not be SP and must not be PC. 3.6.4.4.4 Condition Flags These instructions do not change the flags. Examples STRBTEQ R4, [R7] ;...
Page 97 Cortex-M3 Processor (Reference Material) 3.6.4.5.3 Restrictions In these instructions: • Rt can be SP or PC only for word loads • Rt2 must not be SP and must not be PC • Rt must be different from Rt2. When Rt is PC in a word load instruction: •...
Page 98 Cortex-M3 Processor (Reference Material) happens in order of increasing register numbers, with the lowest numbered register using the lowest memory address and the highest number register using the highest memory address. If the writeback suffix is specified, the value of Rn + 4 * (n-1) is written back to Rn. For LDMDB, LDMEA, STMDB, and STMFD the memory addresses used for the accesses are at 4-byte intervals ranging from Rn to Rn - 4 * (n-1), where n is the number of registers in reglist.
Page 99 Cortex-M3 Processor (Reference Material) PUSH uses the value in the SP register minus four as the highest memory address, POP uses the value in the SP register as the lowest memory address, implementing a full-descending stack. On completion, PUSH updates the SP register to point to the location of the lowest stored value, POP updates the SP register to point to the location immediately above the highest location loaded.
Page 100 Cortex-M3 Processor (Reference Material) must also have the same data size as the value loaded by the preceding Load-exclusive instruction. This means software must always use a Load-exclusive instruction and a matching Store-Exclusive instruction to perform a synchronization operation, see Synchronization Primitives, page 35.
Page 101: General Data Processing Instructions
Cortex-M3 Processor (Reference Material) Examples CLREX 3.6.5 General Data processing instructions The following table shows the data processing instructions: Table 33 • Data Processing Instructions Mnemonic Brief Description Add with Carry "ADD, ADC, SUB, SBC, and RSB" section ADD, ADC, SUB, SBC, and RSB, page 69 ADDW ADD, ADC, SUB, SBC, and RSB,...
Page 102 Cortex-M3 Processor (Reference Material) 3.6.5.1 ADD, ADC, SUB, SBC, and RSB Add, Add with carry, Subtract, Subtract with carry, and Reverse Subtract. 3.6.5.1.1 Syntax op{S}{cond} {Rd,} Rn, Operand2 op{cond} {Rd,} Rn, #imm12 ; ADD and SUB only where: • op is one of: •...
Page 103 Cortex-M3 Processor (Reference Material) • If you want to generate the address of an instruction, you have to adjust the constant based on the value of the PC. ARM recommends that you use the ADR instruction instead of ADD or SUB with Rn equal to the PC, because your assembler automatically calculates the correct constant for the ADR instruction.
Page 104 Cortex-M3 Processor (Reference Material) • Rd is the destination register. • Rn is the register holding the first operand. • Operand2 is a flexible second operand. See Flexible Second Operand, page 51 for details of the options. 3.6.5.2.2 Operation The AND, EOR, and ORR instructions perform bitwise AND, Exclusive OR, and OR operations on the values in Rn and Operand2.
Page 105 Cortex-M3 Processor (Reference Material) • n is the shift length. The range of shift length depends on the instruction: • ASR shift length from 1 to 32 • LSL shift length from 0 to 31 • LSR shift length from 1 to 32 •...
Page 106 Cortex-M3 Processor (Reference Material) 3.6.5.4.4 Condition Flags This instruction does not change the flags. Examples R4,R9 CLZNE R2,R3 3.6.5.5 CMP and CMN Compare and Compare Negative. 3.6.5.5.1 Syntax CMP{cond} Rn, Operand2 CMN{cond} Rn, Operand2 where: cond is an optional condition code, see Conditional Execution, page 55.
Page 107 Cortex-M3 Processor (Reference Material) cond is an optional condition code, see Conditional Execution, page 55. Rd is the destination register. Operand2 is a flexible second operand. See Flexible Second Operand, page 51 for details of the options. imm16 is any value in the range 0-65535. 3.6.5.6.2 Operation The MOV instruction copies the value of Operand2 into Rd.
Page 108 Cortex-M3 Processor (Reference Material) 3.6.5.7 MOVT Move Top. 3.6.5.7.1 Syntax MOVT{cond} Rd, #imm16 where: cond is an optional condition code, see Conditional Execution, page 55. Rd is the destination register. imm16 is a 16-bit immediate constant. 3.6.5.7.2 Operation MOVT writes a 16-bit immediate value, imm16, to the top halfword, Rd[31:16], of its destination register. The write does not affect Rd[15:0].
Page 109 Cortex-M3 Processor (Reference Material) 3.6.5.8.4 Condition Flags These instructions do not change the flags. Examples R3, R7 ; Reverse byte order of value in R7 and write it to R3 REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0 REVSH R0, R5 ;...
Page 110: Table 34 Multiply And Divide Instructions
Cortex-M3 Processor (Reference Material) 3.6.6 Multiply and Divide Instructions The following table shows the multiply and divide instructions: Table 34 • Multiply and Divide Instructions Mnemonic Brief Description Multiply with Accumulate, 32-bit result "MUL, MLA, and MLS" on page 71 Multiply and Subtract, 32-bit result "MUL, MLA, and MLS"...
Page 111: Multiply And Divide Instructions
Cortex-M3 Processor (Reference Material) 3.6.6.1.3 Restrictions In these instructions, do not use SP and do not use PC. If you use the S suffix with the MUL instruction: • Rd, Rn, and Rm must all be in the range R0 to R7 •...
Page 112: Saturating Instructions
Cortex-M3 Processor (Reference Material) 3.6.6.2.3 Restrictions In these instructions: • do not use SP and do not use PC • RdHi and RdLo must be different registers. 3.6.6.2.4 Condition Flags These instructions do not affect the condition code flags. Examples UMULL R0, R4, R5, R6 ;...
Page 113 Cortex-M3 Processor (Reference Material) 3.6.7.1.1 Syntax op{cond} Rd, #n, Rm {, shift #s} where: • op is one of: • SSAT: Saturates a signed value to a signed range. • USAT: Saturates a signed value to an unsigned range. • cond is an optional condition code, see Conditional Execution, page 55.
Page 114: Bitfield Instructions
Cortex-M3 Processor (Reference Material) 3.6.8 Bitfield instructions The following table shows the instructions that operate on adjacent sets of bits in registers or bitfields: Table 35 • Packing and Unpacking Instructions Mnemonic Brief description BFC and BFI, page 81 Bit Field Clear BFC and BFI, page 81 Bit Field Insert...
Page 115 Cortex-M3 Processor (Reference Material) 3.6.8.2.1 Syntax SBFX{cond} Rd, Rn, #lsb, #width UBFX{cond} Rd, Rn, #lsb, #width where: cond is an optional condition code, see Conditional Execution, page 55. Rd is the destination register. Rn is the source register. lsb is the position of the least significant bit of the bitfield. lsb must be in the range 0 to 31. width is the width of the bitfield and must be in the range 1 to 32-lsb.
Page 116: Table 36 Branch And Control Instructions
Cortex-M3 Processor (Reference Material) 3.6.8.3.2 Operation These instructions do the following: Rotate the value from Rm right by 0, 8, 16 or 24 bits. Extract bits from the resulting value: • SXTB extracts bits [7:0] and sign extends to 32 bits. •...
Page 117: Branch And Control Instructions
Cortex-M3 Processor (Reference Material) BL is branch with link (immediate). BX is branch indirect (register). BLX is branch indirect with link (register). cond is an optional condition code, see Conditional Execution, page 55. label is a PC-relative expression. See PC-relative Expressions, page 55.
Page 118 Cortex-M3 Processor (Reference Material) funC ; Branch with link (Call) to function funC, return address ; stored in LR ; Return from function call BXNE ; Conditionally branch to address stored in R0 ; Branch with link and exchange (Call) to a address stored ;...
Page 119 Cortex-M3 Processor (Reference Material) y specifies the condition switch for the third instruction in the IT block. z specifies the condition switch for the fourth instruction in the IT block. cond specifies the condition for the first instruction in the IT block. The condition switch for the second, third and fourth instruction in the IT block can be either: •...
Page 120 Cortex-M3 Processor (Reference Material) 3.6.9.3.4 Condition Flags This instruction does not change the flags. Example ITTE ; Next 3 instructions are conditional ANDNE R0, R0, R1 ; ANDNE does not update condition flags ADDSNE R2, R2, #1 ; ADDSNE updates condition flags MOVEQ R2, R3 ;...
Page 121 Cortex-M3 Processor (Reference Material) 3.6.9.4.3 Restrictions The restrictions are: • Rn must not be SP • Rm must not be SP and must not be PC • when any of these instructions is used inside an IT block, it must be the last instruction of the IT block.
Page 122: Miscellaneous Instructions
Cortex-M3 Processor (Reference Material) 3.6.10 Miscellaneous Instructions The following table lists the remaining Cortex-M3 processor instructions: Table 38 • Miscellaneous Instructions Mnemonic Brief Description BKPT Breakpoint BKPT, page 89 CPSID Change Processor State, Disable Interrupts CPS, page 89 CPSIE Change Processor State, Enable Interrupts CPS, page 89 Data Memory Barrier...
Page 123 Cortex-M3 Processor (Reference Material) 3.6.10.2.1 Syntax CPSeffect iflags where: • effect is one of: • IE: Clears the special purpose register. • ID: Sets the special purpose register. • iflags is a sequence of one or more flags: • i: Set or clear PRIMASK. •...
Page 124 Cortex-M3 Processor (Reference Material) 3.6.10.4 DSB Data Synchronization Barrier. 3.6.10.4.1 Syntax DSB{cond} where: cond is an optional condition code, see Conditional Execution, page 55. 3.6.10.4.2 Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes.
Page 125 Cortex-M3 Processor (Reference Material) 3.6.10.6.2 Operation Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the Q flag. Note: BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction. See MSR, page 92.
Page 126 Cortex-M3 Processor (Reference Material) 3.6.10.8.2 Operation NOP does nothing. NOP is not necessarily a time-consuming NOP. The processor might remove it from the pipeline before it reaches the execution stage. Use NOP for padding, for example to adjust the alignment of a following instruction. 3.6.10.8.3 Condition Flags This instruction does not change the flags.
Page 127 Cortex-M3 Processor (Reference Material) 3.6.10.11.1 Syntax WFE{cond} where: cond is an optional condition code, see Conditional Execution, page 55. 3.6.10.11.2 Operation WFE is a hint instruction. If the event register is 0, WFE suspends execution until one of the following events occurs: •...
Page 128: Cortex-M3 Processor Peripherals
Cortex-M3 Processor (Reference Material) Cortex-M3 Processor Peripherals The following sections are the reference material for the Cortex-M3 processor core peripherals descriptions in this user guide. 3.7.1 About the Cortex-M3 Processor Peripherals The following table provides the address map of the Private peripheral bus (PPB). Table 39 •...
Page 129: Figure 23 Iser Register Bit Assignments
Cortex-M3 Processor (Reference Material) Table 40 • NVIC Register Summary (continued) Required Reset Address Name Type privilege value 0XE000E180- NVIC_ICER0- Privileged 0x00000000 Interrupt Clear-enable Registers, page 97 0xE000E19C NVIC_ICER7 0XE000E200- NVIC_ISPR0- Privileged 0x00000000 Interrupt Set-pending Registers, page 97 0xE000E21C NVIC_ISPR7 0XE000E280- NVIC_ICPR0- Privileged...
Page 130: Figure 24 Icer Register Bit Assignments
Cortex-M3 Processor (Reference Material) Table 42 • NVIC_ISER Bit Assignments Bits Name Function [31:0] SETENA Interrupt set-enable bits. Write: 0: no effect 1: enable interrupt. Read: 0: interrupt disabled 1: interrupt enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
Page 131: Figure 26 Icpr Register Bit Assignments
Cortex-M3 Processor (Reference Material) Table 44 • NVIC_ISPR Bit Assignments Bits Name Function [31:0] SETPEND Interrupt set-pending bits. Write: 0: No effect 1: Changes interrupt state to pending. Read: 0: Interrupt is not pending 1: Interrupt is pending. Note: Writing 1 to the NVIC_ISPR bit corresponding to: •...
Page 132: Figure 28 Ipr Register Bit Assignments
Cortex-M3 Processor (Reference Material) Table 46 • NVIC_IABR Bit Assignments Bits Name Function [31:0] ACTIVE Interrupt active flags: 0: interrupt not active 1: interrupt active. A bit reads as one if the status of the corresponding interrupt is active or active and pending. 3.7.1.8 Interrupt Priority Registers The NVIC_IPR0-NVIC_IPR59 registers provide an 8-bit priority field for each interrupt.
Page 133: Figure 29 Iabr Register Bit Assignments
Cortex-M3 Processor (Reference Material) 3.7.1.9 Software Trigger Interrupt Register Write to the STIR to generate an interrupt from software. See the register summary in Table 40, page 95 for the STIR attributes. When the USERSETMPEND bit in the SCR is set to 1, unprivileged software can access the STIR, see System Control Register, page 108.
Page 134: Table 49 Cmsis Functions For Nvic Control
Cortex-M3 Processor (Reference Material) • For a pulse interrupt, the NVIC continues to monitor the interrupt signal, and if this is pulsed the state of the interrupt changes to pending and active. In this case, when the processor returns from the ISR the state of the interrupt changes to pending, which might cause the processor to immediately re-enter the ISR.
Page 135: System Control Block
Cortex-M3 Processor (Reference Material) 3.7.2 System Control Block The System control block (SCB) provides system implementation information, and system control. This includes configuration, control, and reporting of the system exceptions. The following table lists the SCB registers. Table 50 • Summary of the System Control Block Registers Required Reset...
Page 136: Figure 30 Actlr Bit Assignments
Cortex-M3 Processor (Reference Material) See the register summary in the preceding table for the ACTLR attributes. The bit assignments are: Figure 30 • ACTLR Bit Assignments 3 2 1 0 Reserved DISFOLD DISDEFWBUF DISMCYCINT Table 51 • ACTLR Bit Assignments Bits Name Function...
Page 137: Figure 32 Icsr Bit Assignments
Cortex-M3 Processor (Reference Material) Table 52 • CPUID register Bit Assignments (continued) Bits Name Function [3:0] Revision Revision number, the p value in the rnpn product revision identifier: 0x0 = Patch 0 3.7.2.3 Interrupt Control and State Register The ICSR: •...
Page 138 Cortex-M3 Processor (Reference Material) Table 53 • ICSR Bit Assignments (continued) Bits Name Type Function [28] PENDSVSET PendSV set-pending bit. Write: 0: no effect 1: changes PendSV exception state to pending. Read: 0: PendSV exception is not pending 1: PendSV exception is pending. Writing 1 to this bit is the only way to set the PendSV exception state to pending.
Page 139: Figure 33 Vtor Bit Assignments
Cortex-M3 Processor (Reference Material) This is the same value as IPSR bits[8:0], see Interrupt Program Status Register, page 23. When you write to the ICSR, the effect is Unpredictable if you: • write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit •...
Page 140: Figure 34 Aircr Bit Assignments
Cortex-M3 Processor (Reference Material) The bit assignments are: Figure 34 • AIRCR Bit Assignments 16 15 14 11 10 3 2 1 0 On read: VECTKEYSTAT Reserved Reserved On write: VECTKEY ENDIANNESS PRIGROUP SYSRESETREQ VECTCLRACTIVE Reserved for Debug use VECTRESET Table 55 •...
Page 141: Figure 35 Scr Bit Assignments
Cortex-M3 Processor (Reference Material) Table 56 • Priority Grouping (continued) Interrupt priority level value, PRI_N[7:0] Number of PRIGROUP Binary point Group priority bits Subpriority bits Group priorities Subpriorities b001 bxxxxxx.yy [7:2] [1:0] b010 bxxxxx.yyy [7:3] [2:0] b011 bxxxx.yyyy [7:4] [3:0] b100 bxxx.yyyyy [7:5]...
Page 142: Figure 36 Ccr Bit Assignments
Cortex-M3 Processor (Reference Material) Table 57 • SCR Bit Assignments (continued) Bits Name Function SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode: 0: do not sleep when returning to Thread mode. 1: enter sleep, or deep sleep, on return from an ISR. Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
Page 143: Table 58 Ccr Bit Assignments
Cortex-M3 Processor (Reference Material) Table 58 • CCR Bit Assignments (continued) Bits Name Function [7:5] Reserved. DIV_0_TRP Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0: 0: do not trap divide by 0 1: trap divide by 0.
Page 144: Figure 37 Shpr1 Bit Assignments
Cortex-M3 Processor (Reference Material) 3.7.2.8.1 System Handler Priority Register 1 The bit assignments are: Figure 37 • SHPR1 Bit Assignments 24 23 16 15 Reserved PRI_6 PRI_5 PRI_4 Table 60 • SHPR1 Bit Assignments Bits Name Function [31:24] PRI_7 Reserved [23:16] PRI_6 Priority of system handler 6, UsageFault...
Page 145: Figure 40 Shcsr Bit Assignments
Cortex-M3 Processor (Reference Material) 3.7.2.9 System Handler Control and State Register The SHCSR enables the system handlers, and indicates: • the pending status of the BusFault, MemManage fault, and SVC exceptions • the active status of the system handlers. See the register summary in Table 50, page 102 for the SHCSR attributes.
Page 146: Figure 41 Cfsr Bit Assignments
Cortex-M3 Processor (Reference Material) Table 63 • SHCSR Bit Assignments (continued) Bits Name Function MEMFAULTACT MemManage exception active bit, reads as 1 if exception is active Enable bits, set to 1 to enable the exception, or set to 0 to disable the exception. Pending bits, read as 1 if the exception is pending, or as 0 if it is not pending.
Page 147: Figure 42 Mmfsr Bit Assignments
Cortex-M3 Processor (Reference Material) 3.7.2.11 MemManage Fault Status Register The flags in the MMFSR indicate the cause of memory access faults. The bit assignments are: Figure 42 • MMFSR Bit Assignments 7 6 5 4 3 2 1 0 MMARVALID Reserved MSTKERR MUNSTKERR...
Page 148: Figure 43 Mmfsr Bit Assignments
Cortex-M3 Processor (Reference Material) Table 64 • MMFSR Bit Assignments (continued) Bits Name Function IACCVIOL Instruction access violation flag: 0: no instruction access violation fault 1: the processor attempted an instruction fetch from a location that does not permit execution. This fault occurs on any access to an XN region, even when the MPU is disabled or not present.
Page 149: Figure 44 Ufsr Bit Assignments
Cortex-M3 Processor (Reference Material) Table 65 • BFSR Bit Assignments (continued) Bits Name Function IMPRECISERR Imprecise data bus error: 0: no imprecise data bus error 1: a data bus error has occurred, but the return address in the stack frame is not related to the instruction that caused the error.
Page 150: Figure 45 Hfsr Bit Assignments
Cortex-M3 Processor (Reference Material) Table 66 • UFSR Bit Assignments (continued) Bits Name Function UNALIGNED Unaligned access UsageFault: 0: no unaligned access fault, or unaligned access trapping not enabled 1: the processor has made an unaligned memory access. Enable trapping of unaligned accesses by setting the UNALIGN_TRP bit in the CCR to 1, see Configuration and Control Register, page 109.
Page 151: Table 67 Hfsr Bit Assignments
Cortex-M3 Processor (Reference Material) Table 67 • HFSR Bit Assignments Bits Name Function [31] DEBUGEVT Reserved for Debug use. When writing to the register you must write 0 to this bit, otherwise behavior is Unpredictable. [30] FORCED Indicates a forced HardFault, generated by escalation of a fault with configurable priority that cannot be handles, either because of priority or because it is disabled: 0: no forced HardFault 1: forced HardFault.
Page 152: Table 71 System Timer Registers Summary
Cortex-M3 Processor (Reference Material) Flags in the BFSR indicate the cause of the fault, and whether the value in the BFAR is valid. See BusFault Status Register, page 115. 3.7.2.17 Auxiliary Fault Status Register The AFSR contains additional system fault information. See the register summary in Table 50, page 102 for its attributes.
Page 153: System Timer, Systick
Cortex-M3 Processor (Reference Material) SysTick calibration value. 3.7.3.1 SysTick Control and Status Register The SYST_CTRL register enables the SysTick features. See the register summary in the preceding table for its attributes. The bit assignments are: Figure 46 • SYST_CTRL Register Bit Assignments 17 16 15 3 2 1 0 Reserved...
Page 154: Figure 48 Syst_Cvr Register Bit Assignments
Cortex-M3 Processor (Reference Material) Table 73 • SYST_RVR Register Bit Assignments (continued) Bits Name Function [23:0] RELOAD Value to load into the SYST_CVR register when the counter is enabled and when it reaches 0, see Calculating the RELOAD Value, page 121. 3.7.3.2.1 Calculating the RELOAD Value The RELOAD value can be any value in the range 0x00000001-0x00FFFFFF.
Page 155: Memory Protection Unit
Cortex-M3 Processor (Reference Material) Table 75 • SYST_CALIB Register Bit Assignments (continued) Bits Name Function [29:24] Reserved. [23:0] TENMS Reads as zero. Indicates calibration value is not known. If calibration information is not known, calculate the calibration value required from the frequency of the processor clock or external clock.
Page 156: Table 76 Memory Attributes Summary
Cortex-M3 Processor (Reference Material) The following table shows the possible MPU region attributes. These include shareability and cache behavior attributes that are not relevant to most microcontroller implementations. See MPU Configuration for a Microcontroller, page 132 for guidelines for programming such an implementation. Table 76 •...
Page 157: Figure 50 Mpu_Type Register Bit Assignments
Cortex-M3 Processor (Reference Material) 3.7.4.1 MPU Type Register The MPU_TYPE register indicates whether the MPU is present, and if so, how many regions it supports. See the register summary in Table 77, page 123 for its attributes. The bit assignments are: Figure 50 •...
Page 158: Figure 52 Syst_Cvr Register Bit Assignments
Cortex-M3 Processor (Reference Material) Table 79 • MPU_CTRL Register Bit Assignments (continued) Bits Name Function PRIVDEFENA Enables privileged software access to the default memory map: 0: If the MPU is enabled, disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault.
Page 159: Figure 53 Mpu_Rbar Bit Assignments
Cortex-M3 Processor (Reference Material) Table 80 • MPU_RNR Bit Assignments Bits Name Function [31:8] Reserved. [7:0] REGION Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers. The MPU supports 8 memory regions, so the permitted values of this field are 0-7. Normally, you write the required region number to this register before accessing the MPU_RBAR or MPU_RASR.
Page 160: Figure 54 Mpu_Rasr Bit Assignments
Cortex-M3 Processor (Reference Material) If the region size is configured to 4GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000. The base address is aligned to the size of the region. For example, a 64KB region must be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000.
Page 161: Table 84 Tex, C, B, And S Encoding
Cortex-M3 Processor (Reference Material) 3.7.4.5.1 SIZE Field Values The SIZE field defines the size of the MPU memory region specified by the MPU_RNR. as follows: (Region size in bytes) = 2(SIZE+1) The smallest permitted region size is 32B, corresponding to a SIZE value of 4. The following table provides example SIZE values, with the corresponding region size and value of N in the MPU_RBAR.
Page 162: Table 86 Ap Encoding
Cortex-M3 Processor (Reference Material) The following table describes the cache policy for memory attribute encodings with a TEX value is in the range 4-7. Table 85 • Cache Policy for Memory Attribute Encoding Encoding, AA or BB Corresponding cache policy Non-cacheable Write back, write and read allocate...
Page 163 Cortex-M3 Processor (Reference Material) STRH R2, [R0, #0x8] ; Region Size and Enable STRH R3, [R0, #0xA] ; Region Attribute Disable a region before writing new region settings to the MPU if you have previously enabled the region being changed. For example: ;...
Page 164: Figure 55 Srd Field
Cortex-M3 Processor (Reference Material) ; R1 = address and region number in one ; R2 = size and attributes in one LDR R0, =MPU_MPU_RBAR ; 0xE000ED9C, MPU Region Base register STR R1, [R0, #0x0] ; Region base address and ; region number combined with VALID (bit 4) set to 1 STR R2, [R0, #0x4] ;...
Page 165: Table 87 Memory Region Attributes For A Microcontroller
Cortex-M3 Processor (Reference Material) 3.7.4.9.1 MPU Configuration for a Microcontroller Usually, a microcontroller system has only a single processor and no caches. In such a system, program the MPU as indicated in the following table. Table 87 • Memory Region Attributes for a Microcontroller Memory region Memory type and attributes Flash memory...
Page 166 Cortex-M3 Processor (Reference Material) UG0331 User Guide Revision 15.0...
Page 167: Cache Controller
Supports Cache locked mode • Cache is constructed of latches The following figure depicts the connectivity of the Cache Controller in a SmartFusion2 device. Figure 56 • Cache Controller Interfaces to Cortex-M3 Processor, AHB Bus Matrix, and MDDR Bridge ARM Cortex-M3...
Page 168: Functional Description
Cache Controller Functional Description The following figure depicts all sub-blocks in the Cache Controller block. Figure 57 • Cache Controller Block Diagram Cortex-M3 Microcontroller To cache memory MM 0 MM 1 MM 2 MM 3 Cache Matrix (4 x 7) D(W)/ I(R) D(R)
Page 169: Table 88 Default (Envm Remapped Mode)
This allows multiple firmware images to be stored in eNVM. Note: Not all devices fully populate either or both eNVM address spaces. Please refer to the SmartFusion2 data sheet for the available eNVM for the device.
Page 170: Memory Maps And Transaction Mapping
Cache Controller Table 89 • eSRAM Remapped Mode (Memory Map) (continued) Data/Code Region Space Address CM3 Code Region DDR_SPACE 0 (256 MB) 0x1000_0000 to 0x1FFF_FFFF Reserved 0x0018_0000 to 0x0FFF_FFFF eNVM (Remap View) [512 KB] 0x0010_0000 to 0x0017_FFFF Reserved 0x0001_0000 to 0x000F_FFFF eSRAM0 &...
Page 171: Mode
Cache Controller DNC: DCODE Non Cacheable (W): Write (R): Read Table 91 • Data Path for Various Maps Memory Map Supported Destination Mode Buses Trans Region Slave Routed Through Default Memory Map - eNVM Remapped ICODE eNVM AHB Bus Matrix eNVM AHB Bus Matrix DCODE...
Page 172 The cache matrix supports locked transactions from the SBUS towards the eSRAM AHB controller, through the switch, by monitoring HMASTLOCK. The cache matrix initiates IDLE on the AHB bus after every LOCKED transfer. SmartFusion2 SoC FPGA - Cache Controller Configuration Application Note •...
Page 173: Figure 58 General Cache Architecture And Addressing
Cache Controller 4.2.3.3 Cache Engine The Cache Engine takes care of address generation logic using a four-way set associative, hit and miss generation logic, cache line filling/replacement, a temporary local buffer for cache line while writing, and arbitration logic for ICode and DCode buses. The Cache Controller has a four-way set associative cache subsystem with 32-byte cache lines organized as 64 sets of 4 cache lines.
Page 174: Figure 59 Iar Compiler Options
Cache Controller b. Supports hit/miss generation mechanism for Cache Memory and local buffer c. One of the following types of transaction will come to the Cache Engine: • Transaction for cacheable region in DDR • Transaction for non-cacheable region in DDR •...
Page 175: Cache Locked Mode
Cache Controller Figure 60 • IAR Assembler Options 4.2.4 Cache Locked Mode Cache Locked mode is a special mode that provides predictable execution required for some specific applications like avionics and certain security applications. Before enabling Cache Locked mode, the software should ensure that the code is copied to the Cache Memory by simulating a sequential location cache miss through DCode or writes through SBUS by enabling SBUS Write mode.
Page 176: Interfaces
Cache Controller 4.2.5 Interfaces The following figure shows the Cache Controller interface in the MSS subsystem. There are two interfaces through which the Cache Controller is connected to the main memories: Interface towards MDDR bridge: 128-bit AHB-Lite, this interface is read only for instruction/data reads and 32-bit AHB-Lite to access DDR memory through DDR bridge and system bus (read and write access) Interface towards AHB bus matrix: There are three 32-bit AHB-Lite modes:...
Page 177: How To Use Cache Controller
Cache Controller How to Use Cache Controller Cache Controller can be configured statically by using the Libero design software. The following figure shows the Cache Controller enable option, cache region size selection. Figure 62 • MSS Configurator with Cache Controller Configuration Options The following figure shows how to select the main memory from memory blocks eNVM, eSRAM, and DDR SDRAM.
Page 178: System Registers Used For Cache Operations
AC389: SmartFusion2 SoC FPGA - Cache Controller Configuration Application Note • AC390: SmartFusion2 SoC FPGA – Remapping eNVM, eSRAM, and DDR/SDR SDRAM Memories Application Note Note: Create or modify the linker scripts/linker settings of the application in such a way that all read and write data sections are in non-cacheable memory regions or accessed through the system bus address space.
Page 179: Embedded Nvm (Envm) Controllers
• Single error correction and dual error detection (SECDED) protected • Based on the selected SmartFusion2 device, the total size of eNVM memory ranges from 128 KB, 256 KB, and 512 KB. • M2S005 has a single block of 128 KB.
Page 180: Functional Description
AHB Controller Figure 66 • eNVM Controller Block Diagram M3_CLK is used within the MSS to clock the AHB bus matrix. Refer to UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide for more information on M3_CLK. UG0331 User Guide Revision 15.0...
Page 181: Memory Organization
Embedded NVM (eNVM) Controllers eNVM Array: The eNVM array is connected to a 25 MHz internal oscillator. This 25 MHz internal oscillator is used during device start up to initialize the NVM controller. It is also used for eNVM program operation.
Page 182: Data Retention Time
Data Retention Time The following table shows the retention time of the eNVM with respect to the number of programming cycles. The same values are applicable for both commercial and industrial SmartFusion2 product grades. Refer to DS0128: IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet for more information on Programming cycles and retention time.
Page 183: Figure 67 Write Path
Embedded NVM (eNVM) Controllers Figure 67 • Write Path 5.2.4.2 Read Control The following steps describe eNVM read control. • The read transaction from the eNVM user array to AHBL bus uses the read data buffer as a mini cache. •...
Page 184: Figure 68 Read Path
Embedded NVM (eNVM) Controllers The following figure shows the eNVM array read path. The AHB Controller also supports WRAP4 burst operations, which are initiated by the cache controller. In this case, the AHB eNVM controller will automatically perform four 64-bit read operations (critical word first) and fill the read data buffer in advance to the AHB read transactions to increase system throughput.
Page 185: Envm Command Register
Embedded NVM (eNVM) Controllers 5.2.5 eNVM Command Register The following table shows the Command register bit definitions. Table 97 • Command (CMD) Register Description 31:24 Command code 23:0 Address field; to supply address for NVM operation, refer to Table 98, page 151.
Page 186 Embedded NVM (eNVM) Controllers Table 98 • Command Table (continued) HADDR HWDATA Transaction Name 17:0 31:24 23:0 Type Description ProgramADS ACMD Write Start whole program page procedure, includes sending page address, sending entire content of write data buffer to assembly buffer, then starting the NVM operation.
Page 187 Embedded NVM (eNVM) Controllers If the command ProgramDa is not issued after the ProgramAd operation, the current data in the assembly buffer will be programmed to the NVM array. 5.2.5.2.1 Program Page with a Single AHBL Write ProgramADS: During the command ProgramADS, a single AHBL write transaction can be used to start and complete the program page procedure.
Page 188: Figure 69 Timing Diagram Showing Single Word Read Operation
Embedded NVM (eNVM) Controllers 5.2.5.5 eNVM Read Operations with Timing Diagrams The following are the example eNVM read operations with the Cortex-M3 processor operating at 166 MHz. The eNVM NV_FREQRNG is set to 6. 5.2.5.5.1 Single Word Read The following figure shows the AHB read command to 0x60001000 starting at the first cursor, and data being returned at the second cursor 9 clock cycles later.
Page 189: Figure 71 Timing Diagram Showing Cache Fill Read Operations Utilizing Bursts
Embedded NVM (eNVM) Controllers 5.2.5.5.3 Cache Fill Operation Utilizing Bursts The internal cache fill operations using AHB wrapping can utilize bursts to optimize the cache fill operations. The AHB-NVM controller always returns 8 words in a burst. The first word returns after 9 clock cycles, and second word in the following cycle as shown in the preceding figure.
Page 190: Figure 72 Envm Program (Programads) And Verify (Verifyads) Operations
Embedded NVM (eNVM) Controllers The following figure shows the complete eNVM program (ProgramADS) and eNVM verify (VerifyADS) operations. Figure 72 • eNVM Program (ProgramADS) and Verify (VerifyADS) Operations At cursor 1, steps 1 and 2 in the sequence are performed. At cursor 2, the eNVM Program operation gets completed and Verify operation gets started.
Page 191: Figure 75 Completion Of Programads And Issue Of Verifyads Command
Embedded NVM (eNVM) Controllers The following figure shows completion of ProgramADS and issue of VerifyADS command. Figure 75 • Completion of ProgramADS and Issue of VerifyADS Command The ProgramADS command completion can be confirmed by polling Status register response. The following figure shows the completion of eNVM verify operation.
Page 192: Figure 77 Complete Envm Program And Verify Operations Waveform
Embedded NVM (eNVM) Controllers The following figure shows the complete eNVM program and eNVM verify operations. Figure 77 • Complete eNVM Program and Verify Operations Waveform At cursor 1,steps 1 and 2 in the sequence are performed. At cursor 2, the eNVM ProgramStart operation is completed and VerifyAD operation is started.
Page 193: Error Response
Embedded NVM (eNVM) Controllers The following figure shows the completion of the ProgramDA command and the issuance of the ProgramStart command. Figure 81 • ProgramStart Command The completion of the eNVM command is confirmed by monitoring the eNVM status register for eNVM ready and the next command in sequence is sent.
Page 194: User Protectable 4K Regions
Embedded NVM (eNVM) Controllers • Using AHB bus master access control, the eNVM can be protected from different masters connected on the AHB bus matrix. Refer to the AHB Bus Matrix, page 210. • User-defined regions can be protected from the FPGA fabric. 5.3.1 User Protectable 4K Regions Figure 82 •...
Page 195: Figure 84 Envm Special Sectors For The M2S010Ts, M2S025Ts Devices With 256 Kb Envm_0
Embedded NVM (eNVM) Controllers Figure 84 • eNVM Special Sectors for the M2S010TS, M2S025TS Devices with 256 KB eNVM_0 Figure 85 • eNVM Special Sectors for the M2S060TS Devices with 256 KB eNVM_0 UG0331 User Guide Revision 15.0...
Page 196: Figure 86 Envm Special Sectors For The M2S090Ts, M2S150Ts Devices With 512 Kb
Embedded NVM (eNVM) Controllers Figure 86 • eNVM Special Sectors for the M2S090TS, M2S150TS Devices with 512 KB The security configuration is provided as input to the eNVM Controller from system registers as per the ENVM_PROTECT_USER register described in Table 103, page 174 for configuration of upper and lower regions of NVM.
Page 197: Envm Pages For Special Purpose Storage
Some special purpose pages are reserved and protected. Refer below tables for more information on eNVM special purpose storage based on SmartFusion2 device density. The system controller performs read/write operations on unreserved eNVM pages using system controller services.
Page 198: Table 101 Special Purpose Storage Regions For M2S060, M2S090, And M2S150 Devices
Embedded NVM (eNVM) Controllers M2S060 device has 2 private regions in eNVM_0 and M2S090/M2S150 device has 2 private regions in eNVM_1. Table 101 • Special Purpose Storage Regions for M2S060, M2S090, and M2S150 Devices Offset in Sector page Range in eNVM Page Type Usage (Bytes)
Page 199: How To Use Envm
It only reads data from reserved eNVM pages. How to Use eNVM This section describes how to use the eNVM in the SmartFusion2 devices. To configure the SmartFusion2 device features and then build a complete system, use the System Builder graphical design wizard in the Libero SoC software.
Page 200: Figure 87 System Builder Window
Embedded NVM (eNVM) Controllers Figure 87 • System Builder Window UG0331 User Guide Revision 15.0...
Page 201: Figure 88 System Builder - Device Features Tab
Embedded NVM (eNVM) Controllers The following steps describe how to generate a programming file with the eNVM client in an application using System Builder. Check the MSS On-chip Flash Memory (eNVM) check box under the Device Features tab and leave the other check boxes unchecked. The following figure shows the System Builder - Device Features tab.
Page 202: Figure 89 System Builder - Memories Tab
Intel-Hex • Motorola-S • Microsemi-Hex • Microsemi-Binary Create the memory file in any one of the above formats with the executable code or data. Memory file can be created for the code using the SoftConsole 3.4 or later with the linker script "production- execute-in-place.ld".
Page 203: Figure 90 Add Data Storage Client Dialog
Embedded NVM (eNVM) Controllers Enter the Client name, navigate to the memory file location using Browse, and select it. Give the rest of the parameters according to the requirements and click OK to add the eNVM client. For more information on Use absolute addressing, Use as ROM and other options, click Help. Figure 90 •...
Page 204: Figure 91 System Builder - Memories Tab With Two Envm Clients
Embedded NVM (eNVM) Controllers The eNVM client data is populated in the System Builder - Memories tab. The following figure shows the System Builder - Memories tab with two eNVM clients. Figure 91 • System Builder - Memories Tab with Two eNVM Clients UG0331 User Guide Revision 15.0...
Page 205: Figure 92 System Builder - Microcontroller Tab
Click Help and select AHB Bus Matrix to access the help document for more information on eNVM Remap Region Size and Base Address, as shown in the following figure. Refer AC390: SmartFusion2 SoC FPGA – Remapping eNVM, eSRAM, and DDR/SDR SDRAM Memories Application Note.
Page 206: Reading The Envm Block
• Refer to the AC429: SmartFusion2 and IGLOO2 - Accessing eNVM and eSRAM from FPGA Fabric Application Note for information on how to access the eNVM using FPGA fabric logic. •...
Page 207: Writing To The Envm Block
Firmware Catalog. The eNVM firmware driver provides APIs to unlock and write to eNVM features. Refer to the SmartFusion2 eNVM Driver User Guide from Open Documentation for the list of APIs and their descriptions.
Page 208: Sysreg Control Registers
Embedded NVM (eNVM) Controllers The following table lists the available APIs for eNVM in the eNVM firmware drivers Table 102 • Available APIs for eNVM Description NVM_unlock Unlock the eNVM Block NVM_write The function NVM_write() is used to program data in to the eNVM. This function treats the two eNVM blocks contiguously, hence 512 KB of memory can be accessed linearly.
Page 209 Embedded NVM (eNVM) Controllers Table 104 • ENVM_CR Reset Number Name Value Description [31:17] Reserved ENVM_SENSE_ON Turns on or off the sense amps for both NVM0 and NVM1. The sense amp switching feature is useful to decrease the eNVM access time. 0: Normal Operation -The sense amp switches off after every read cycle if an idle cycle follows.
Page 210: Table 104 Envm_Cr
Embedded NVM (eNVM) Controllers Table 104 • ENVM_CR (continued) Reset Number Name Value Description [12:5] NV_FREQRNG Setting of NV_FREQRNG[8:5] or NV_FREQRNG[12:9] determines the behavior of eNVM BUSY_B with respect to the AHB Bus interface clock. It can be used to accommodate various frequencies of the external interface clock, M3_CLK, or it can be used to advance or delay the data capture due to variation of read access time of the NVM core.
Page 211 Embedded NVM (eNVM) Controllers Table 105 • SW_ENVMREMAPSIZE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Remap Size Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB, reset value Table 106 •...
Page 212: Table 107 Envm_Remap_Fab_Cr
Embedded NVM (eNVM) Controllers Table 107 • ENVM_REMAP_FAB_CR Reset Number Name Value Description [31:19] Reserved [18:1] SW_ENVMFABREMAPBASE Offset within eNVM address space of the base address of the segment in eNVM, which is to be remapped to location 0x00000000 for use by a soft processor in the FPGA fabric. The base address of the remapped segment of eNVM is determined by the value of this register.
Page 213: Table 109 Envm_Status
Embedded NVM (eNVM) Controllers Table 108 • ENVM_PROTECT_USER (continued) Reset Number Name Value Description NVM1_LOWER_M3ACCESS When this bit is set, it indicates that the M3 can access the lower protection region of eNVM1. This will be set by the user flash row bit. NVM0_UPPER_WRITE_ALLOWED When set indicates that the masters who have read access can have write access to the upper protection region of...
Page 214: Envm Control Registers
Embedded NVM (eNVM) Controllers Table 110 • ENVM_SR Reset Number Name Value Description [31:2] Reserved [1:0] ENVM_BUSY Active high signals indicate a busy state per eNVM for CLK-driven operations and for internal operations triggered by the write/program/erase/transfer command. ENVM_BUSY[1] = Busy indication from ENVM1 ENVM_BUSY[0] = Busy indication from ENVM0 eNVM Control Registers To perform any transaction with the NVM array, the Control registers must be configured appropriately as...
Page 215 NVM1 wait states. Refer to Table 114 on page 185 NV_FREQRNG calculations at different M3_CLK frequencies for all SmartFusion2 devices. Bits [7:4] are unused with the AHB-NVM block when the device has only eNVM_0. This controls the NV_FREQRNG[3:0] input on the NVMCTRL function...
Page 216: Inten[10:0]
Embedded NVM (eNVM) Controllers Table 112 • Control Registers Description (continued) OFFSET HADDR[8:0] Register Name Width Type Default Access Rights Description 0x134 NV_CE 2-bit Exclusive access NV_CE[0] = 0: NVM to the requested disabled master NV_CE[0] = 1: NVM enabled NV_CE [1] = 1;...
Page 217 Embedded NVM (eNVM) Controllers Table 112 • Control Registers Description (continued) OFFSET HADDR[8:0] Register Name Width Type Default Access Rights Description 0x1FC REQACCESS Any master on Request register access AHB bus matrix. When written with 0x01, it This register can will request exclusive only be accessed access.
Page 218: Status Register Bit Definitions
Asserted when write count is over threshold. Valid after program, verify and read page status. The threshold value per eNVM page is 1000 or 10000 depending on the data retention period. See DS0128: IGLOO2 FPGA and SmartFusion2 SoC FPGA Datasheet for more information on programming cycles and retention time.
Page 219: Table 114 Nv_Freqrng Calculations At Different M3_Clk Frequencies For All Smartfusion2 Devices
Embedded NVM (eNVM) Controllers Table 113 • Status Register Bit Definitions (continued) Description NVM Ready/busy 0: Busy 1: Ready Table 114 • NV_FREQRNG Calculations at Different M3_CLK Frequencies for All SmartFusion2 Devices Standard MSS Frequencies M3_CLK in MHz NV_FREQRNG[3:0] 0x 5 0x 4...
Page 220: Table 117 Clrhint[2:0]
Embedded NVM (eNVM) Controllers Table 117 • CLRHINT[2:0] Description Clear the internal command when busy bit Clear the internal access denied flag Clear HINTERRUPT output UG0331 User Guide Revision 15.0...
Page 221: Embedded Sram (Esram) Controllers
Embedded SRAM (eSRAM) Controllers Embedded SRAM (eSRAM) Controllers SmartFusion2 SoC FPGAs have two embedded SRAM (eSRAM) blocks of 32 KB each for data read and write operations. These eSRAM blocks are interfaced through eSRAM controllers to the AHB bus matrix.
Page 222: Functional Description
Embedded SRAM (eSRAM) Controllers The following figure depicts the connectivity of eSRAM_0 and eSRAM_1 to the AHB bus matrix. Figure 95 • eSRAM_0 and eSRAM_1 Connection to AHB Bus Matrix ARM Cortex-M3 MDDR Processor Cache System MSS DDR Controller eNVM_0 eNVM_1 eSRAM_0 eSRAM_1...
Page 223: Figure 96 Esram Controller Block Diagram
Embedded SRAM (eSRAM) Controllers The following figure shows the eSRAM controller blocks and their connectivity in SmartFusion2 FPGAs. Both eSRAMs and eSRAM controllers are identical in all design aspects. Figure 96 • eSRAM Controller Block Diagram DI_0 ESRAM_PIPELI HWDATA GENERATOR NE_ENABLE &...
Page 224: Memory Organization
Embedded SRAM (eSRAM) Controllers ECC Checker and AHB Read Data Bus (HRDATA) Generator: In SECDED-ON mode, the ECC Checker takes data (DO) from the memory as the input during the read or read-modify-write cycle and checks for errors. One-bit errors detected are corrected. If errors of more than one bit are detected, they are not corrected.
Page 225: Modes Of Operation
The actual frequency at which this is possible is specified in the AC characteristics table of DS0451: IGLOO2 and SmartFusion2 Datasheet. When the pipeline is disabled, the number of wait states is less, increasing throughput of read operations.
Page 226: Table 121 Wait States In Different Operation Modes
Embedded SRAM (eSRAM) Controllers The following table describes the wait states in different operation modes. These values indicate the number of wait states inserted by eSRAM controllers and apply to the reads and writes from masters within the MSS. Accessing eSRAM blocks from the FPGA fabric is performed through the fabric interface controller (FIC) interfaces.
Page 227 Embedded SRAM (eSRAM) Controllers Table 121 • Wait States in Different Operation Modes (continued) SECDED Number of Wait Number of Wait States Pipeline eSRAM Mode Operation Size States (Reads following a Write) Disabled 32 KB SECDED- Write 32-Bit 0 ON Mode 16-Bit 1 8-Bit Read...
Page 228: How To Use Esram
Embedded SRAM (eSRAM) Controllers How to Use eSRAM This section describes how to use the eSRAM in the SmartFusion2 devices. To configure the SmartFusion2 device features and then build a complete system, use the System Builder graphical design wizard in the Libero SoC software.
Page 229: Figure 98 System Builder - Microcontroller Tab
System Builder - Microcontroller tab. For more information on the Programmable Slave Maximum Latency configuration and remapping eSRAM to Cortex-M3 code space, click Help and select AHB Bus Matrix document as shown in the figure. Refer to AC390: SmartFusion2 SoC FPGA – Remapping eNVM, eSRAM, and DDR/SDR SDRAM Memories Application Note.
Page 230: Figure 99 System Builder - Secded Tab
The following figure shows the System Builder - SECDED tab. For more information on SECDED, click Help and select SECDED document. Refer to UG0388: SmartFusion2 SoC FPGA Error Detection and Correction of eSRAM Memory Demo User Guide.
Page 231: Figure 100 System Builder - Security Tab
The read and write permission for different masters are available for data and design security enabled devices like M2S050TS only. For more information on configuring the security options, refer to SmartFusion2 MSS Security Configuration. Figure 100 • System Builder - Security Tab Navigate to the Memory Map tab giving the required data in the rest of the System Builder tabs and click Finish to proceed with creating the MSS Subsystem.
Page 232: Sysreg Control Registers
Embedded SRAM (eSRAM) Controllers SYSREG Control Registers The registers listed in the following table control the behavior of the eSRAM. These registers are detailed SYSREG and are listed here for clarity. Refer to the System Register Block, page 670 for a detailed description of each register and bit.
Page 233: Table 595 Status
Embedded SRAM (eSRAM) Controllers Table 122 • SYSREG Control Registers (continued) Register Flash Write Register Name Type Protect Reset Source Description MM9_SECURITY RO-U SYSRESET_N Read and Write security for Mirrored (0x40038130) Master (MM) 9 to eSRAM_0 and eSRAM_1. This register gets updated by flash bit configuration set during device programming.
Page 234: Table 123 Esram_Cr
Embedded SRAM (eSRAM) Controllers Table 123 • ESRAM_CR (continued) SW_CC_ESRAMFWREMAP This bit indicates that eSRAM_0 and eSRAM_1 are remapped to lCODE/DCODE space of the Cortex-M3 processor. If this bit is 1 and SW_CC_ESRAM1FWREMAP is 0, then eSRAM_0 is at location 0x00000000 and eSRAM_1 is always remapped to be just above eSRAM_0 (the two eSRAMs are adjacent in ICODE/DCODE space).
Page 235: Table 126 Esram_Pipeline_Cr
Embedded SRAM (eSRAM) Controllers Table 126 • ESRAM_PIPELINE_CR Reset Number Name Value Description [31:1] Reserved Reserved ESRAM_PIPELINE_ENABLE 0x1 Controls the pipeline present in the read path of eSRAM memory. Allowed values: 0: Pipeline will be bypassed. 1: Pipeline will be present in the memory read path. Table 127 •...
Page 236: Table 130 Esram1_Edac_Adr
Embedded SRAM (eSRAM) Controllers Table 130 • ESRAM1_EDAC_ADR Reset Number Name Value Description [31:25] Reserved Reserved [25:13] ESRAM1_EDAC_2E_AD Stores the address from eSRAM1 on which a 2-bit SECDED error has occurred. [12:0] ESRAM1_EDAC_1E_AD Stores the address from eSRAM1 on which a 1-bit SECDED error has occurred.
Page 237: Table 132 Mm4_5_Ddr_Fic_Security/Mm4_5_Fic64_Security
Embedded SRAM (eSRAM) Controllers Table 132 • MM4_5_DDR_FIC_SECURITY/MM4_5_FIC64_SECURITY Reset Number Name Value Description [31:10] Reserved Reserved MM4_5_DDR_FIC_MS6_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to slave 6 (MSS DDR bridge). If not set, masters 4, 5 and DDR_FIC will not have write access to slave 6.
Page 238 Embedded SRAM (eSRAM) Controllers Table 133 • MM3_6_7_8_SECURITY Reset Number Name Value Description [31:10] Reserved Reserved MM3_6_7_8_MS6_ALLOWED_W Write security bits for masters 3, 6, 7, and 8 to slave 6 (MSS DDR bridge). If not set, masters 3, 6, 7, and 8 will not have write access to slave 6.
Page 239: Table 134 Mm9_Security
Embedded SRAM (eSRAM) Controllers Table 134 • MM9_SECURITY (continued) Reset Number Name Value Description MM9_MS3_ALLOWED_W Write security bits for master 9 to slave 3 (eNVM1). If not set, master 9 will not have write access to slave 3. MM9_MS3_ALLOWED_R Read security bits for master 9 to slave 3 (eNVM1). If not set, master 9 will not have read access to slave 3.
Page 240: Table 135 Edac_Sr
Embedded SRAM (eSRAM) Controllers Table 135 • EDAC_SR (continued) Reset Number Name Value Description ESRAM1_EDAC_2E Updated by the eSRAM_1 controller when a 2-bit SECDED error has been detected for eSRAM1 memory. ESRAM1_EDAC_1E Updated by the eSRAM_1 Controller when a 1-bit SECDED error has been detected and is corrected for eSRAM1 memory.
Page 241: Table 136 Clr_Edac_Counters
Embedded SRAM (eSRAM) Controllers Table 136 • CLR_EDAC_COUNTERS (continued) Reset Number Name Value Description ESRAM1_EDAC_CNTCLR_2E Generated to clear the 16-bit counter value in ESRAM1 corresponding to the count value of EDAC 2-bit errors. This in turn clears the upper 16 bits of the ESRAM1_EDAC_CNT register.
Page 242: Table 137 Edac_Irq_Enable_Cr
Embedded SRAM (eSRAM) Controllers Table 137 • EDAC_IRQ_ENABLE_CR (continued) Reset Number Name Value Description MAC_EDAC_RX_1E_EN Allows the 1-bit error EDAC for Ethernet Rx RAM status update to be disabled. Allowed values: 0: MAC_EDAC_RX_1E_EN is disabled. 1: MAC_EDAC_RX_1E_EN is enabled. MAC_EDAC_TX_2E_EN Allows the 2-bit error EDAC for Ethernet Tx RAM status update to be disabled.
Page 243: Table 138 Edac_Cr
Embedded SRAM (eSRAM) Controllers Table 138 • EDAC_CR (continued) MAC_EDAC_TX_EN Allows the EDAC for Ethernet Tx RAM to be disabled. Allowed values: 0: Tx RAM EDAC disabled 1: Tx RAM EDAC enabled Reserved Reserved ESRAM1_EDAC_EN Allows the EDAC for eSRAM1 to be disabled. Allowed values: 0: EDAC disabled 1: EDAC enabled ESRAM0_EDAC_EN...
Page 244: Ahb Bus Matrix
The AHB bus matrix is a multi-layer AHB matrix. It is not a full crossbar switch, but a customized subset of a full switch. It works purely as an AHB-Lite matrix. The SmartFusion2 SoC FPGA AHB bus matrix has ten masters and seven direct slaves as depicted in the following figure. One master is permitted to access a slave at the same time another master is accessing a different slave.
Page 245: Functional Description
Exercise caution when commanding the eNVM to program or erase data. Other masters in the system may not be aware that the eNVM is unavailable if it is in a program or erase cycle. Microsemi recommends you use some form of software semaphore to control access.
Page 246: Figure 102 Master Stage And Slave Stage Interconnection
AHB Bus Matrix • Read by an enabled master to any slave that is not R or RW • Read by an enabled master to addresses not corresponding to a slave • Read by the fabric master to the protected region •...
Page 247: Figure 103 Block Diagram Of Apb Destinations Connected To Ahb Bus Matrix
AHB Bus Matrix The following figure shows the block diagram of all the APB peripherals connected to AHB bus matrix using the AHB-to-AHB bridge. The MSS APB peripherals are connected through the AHB to APB bus. Figure 103 • Block Diagram of APB Destinations Connected to AHB Bus Matrix AHB BUS AHB Bus Matrix 10X7...
Page 248: Timing Diagrams
AHB Bus Matrix 7.1.2 Timing Diagrams The following figures are the functional timing diagrams for AHBL read/write transactions through the AHB bus matrix and AHB-to-AHB bridge. Signals to/from a master are denoted by X in the signal name, and signals to/from a slave are denoted with Y in the signal name. For example, if Cortex-M3 processor master initiates the transactions of read/write to the eSRAM slave then the signals with X in the signal name indicates the signals of the Cortex-M3 processor and signals with Y indicate slave eSRAM signals.
Page 249: Figure 105 Ahb-Lite Read Transactions
AHB Bus Matrix Figure 105 • AHB-Lite Read Transactions HCLK X_HADDR X_HTRANS X_HWRITE X_HREADY X_HRDATA X_HRESP 0 X_HMASTLOCK 0 Y_HADDR Y_HSEL Y_HTRANS Y_HWRITE Y_HREADY Y_HRDATA Y_HRESP 0 Y_HMASTLOCK 0 UG0331 User Guide Revision 15.0...
Page 250: Figure 106 Ahb-To-Ahb Write Transactions
AHB Bus Matrix Figure 106 • AHB-to-AHB Write Transactions HCLK Y_HRESET Y_HADDR Y_HMASTLOCK Y_HSIZE Y_HSEL Y_HTRANS1 Y_HWRITE Y_HWDATA Y_HREADY Y_HRESP Y_HREADYOUT X_HREADYOUT X_HRESP X_HADDR X_HSIZE X_HTRANS1 X_HWRITE X_HWDATA X_HREADY X_HMASTLOCK UG0331 User Guide Revision 15.0...
Page 251: Figure 107 Ahb-To-Ahb Read Transactions
AHB Bus Matrix Figure 107 • AHB-to-AHB Read Transactions HCLK Y_HADDR Y_HMASTLOCK Y_HSIZE Y_HSEL Y_HTRANS1 Y_HWRITE Y_HWDATA Y_HREADY Y_HRESP Y_HRDATA Y_HREADYOUT X_HRDATA X_HREADYOUT X_HRESP X_HADDR X_HSIZE X_HTRANS1 X_HWRITE X_HREADY X_HMASTLOCK UG0331 User Guide Revision 15.0...
Page 252: Details Of Operation
AHB Bus Matrix 7.1.3 Details of Operation 7.1.3.1 Slave Arbitration Each of the slave devices on the AHB bus matrix contains an arbiter. Arbitration is done at two levels. At the first level, the fixed higher priority masters are evaluated for any access request to the slave. At the second level, the remaining busses are evaluated in round robin fashion for any access request to the slave.
Page 253: Figure 108 Pure Round Robin And Fixed Priority Slave Arbitration Scheme
AHB Bus Matrix 7.1.3.1.2 Pure Round Robin Arbitration This is the default arbitration mode after reset. The programmable weight value of each master is set to 1, and ESRAM_MAX_LAT = 1. The arbitration scheme for each slave port is identical in pure round robin arbitration, as shown in the following figure.
Page 254: Table 142 Pure Round Robin And Fixed Priority Arbitration Scenario For Esram1
AHB Bus Matrix The following table gives an example of a pure round robin and fixed priority arbitration scenario for eSRAM1. This example illustrates default AHB bus matrix behavior. Table 142 • Pure Round Robin and Fixed Priority Arbitration Scenario for eSRAM1 HCLK Master M3-I: M0...
Page 255: Figure 109 Wrr And Fixed Priority Slave Arbitration Scheme
AHB Bus Matrix Figure 109 • WRR and Fixed Priority Slave Arbitration Scheme Dcode Icode S-Bus HMASTLOCK System HMASTLOCK Controller Fixed Priority Masters Round Robin Masters HPDMA PrgWeight PrgWeight PrgWeight FIC_0 PDMA PrgWeight HMASTLOCK PrgWeight PrgWeight FIC_1 HMASTLOCK WRR with fixed priority arbitration allows more efficient usage of slave bandwidth in cases where the slaves have a penalty when transitioning from one master to another.
Page 256: Table 143 Wrr And Fixed Priority Arbitration Scenario For Envm_0
AHB Bus Matrix high priority master is requesting access to the slave. Only after completing 8 transfers, the high priority master will gain access to the slave. The following table gives an arbitration scenario for a non-eSRAM slave. In this scenario, master M5 (FIC_1) starts a burst of twelve transfers (reads typically for accesses to eNVM) to slave S2 (eNVM_0) in the first clock cycle.
Page 257: Figure 110 Slave Arbitration Flow Diagram
AHB Bus Matrix 7.1.3.1.5 Slave Arbitration Flow Diagram The following figure shows the slave arbitration flow diagram depicting the grant of access to master requesting for slave access. At each stage the arbiter checks whether that master is requesting for an access.
Page 258: Figure 111 Ahb Bus Matrix To Fabric Interface Controller
(HM) and fabric master (FM). These interfaces may be configured to operate as AHB32 or APB32. Configure FIC_0 and FIC_1 interfaces in bypass mode to perform weighted round robin arbitration. For more information, refer to the AC388: SmartFusion2 SoC FPGA - Dynamic Configuration of AHB Bus Matrix Application Note.
Page 259: System Memory Map
The AHB bus matrix is responsible for implementing the address decoding of all masters to all slaves, so it defines the system memory map. The following figure depicts the default system memory map for SmartFusion2 devices. Figure 112 • Default System Memory Map...
Page 260: Figure 113 Memory Map After Esram Remap (64 Kb Esram)
AHB Bus Matrix 7.1.4.1 eSRAM Remap The AHB bus matrix supports remapping the eSRAM address space into code space that Cortex-M3 processor can use. Both eSRAM blocks can be remapped to appear at the bottom of Cortex-M3 processor code space as shown in the preceding figure. The amount of space available to Cortex-M3 processor as code space depends on ECC as indicated below: •...
Page 261: Figure 114 Use Case For Esram Execution
AHB Bus Matrix A master in the FPGA fabric must extend the assertion of reset to the Cortex-M3 processor until the system reset to the remainder of the MSS is negated. This master must then copy the appropriate code from eNVM to eSRAM and release the reset of the Cortex-M3 processor. 7.1.4.1.1 Executing from eSRAM The eSRAM remap is actually performed by aliasing the eSRAM blocks so they appear in the Cortex-M3...
Page 262: Figure 115 Virtual Envm View (After Chip Boot)
AHB bus for accesses in the range from 0x00000000 to 0x1FFFFFFF. Of all masters in a SmartFusion2 device, only the Cortex-M3 processor ICode and DCode AHB busses access the eNVM in this range, which corresponds to its code space.
Page 263: Figure 116 Virtual Envm View For Soft Processor
AHB Bus Matrix supports remapping of an eNVM segment to location 0x00000000 in the memory map seen by masters in the FPGA fabric with the ENVM_REMAP_FAB_CR control register. The ENVM_REMAP_FAB_CR control register configures where ENVM is mapped in fabric space.There is no eSRAM remap for fabric masters.
Page 264: Figure 117 Ddr Memory Remap
AHB Bus Matrix The cache controller generates the appropriate DDR address as per remap before putting the access request to the MSS DDR bridge. A soft SDRAM memory controller implemented in the fabric can be remapped to address 0 just like the MDDR so that external code located in SDRAM is cacheable. Figure 117 •...
Page 265 AHB Bus Matrix 7.1.4.5 Unimplemented Address Space The AHB bus matrix performs address decoding based on the memory map defined in Figure 112, page 225 and Figure 113, page 226, to decide which slave, if any, is being addressed. Any access to memory space outside of these regions is considered unimplemented from the point of view of the AHB bus matrix.
Page 266: Table 146 Pairing Of Masters And Slaves
AHB Bus Matrix (SBus). Microsemi recommends that the Cortex-M3 processor firmware is stored in a separate eSRAM from the data storage of other services. 7.1.4.11 Memory Security After reset, all master ports on the AHB bus matrix are enabled. There are separate user-defined flash configuration bits that control read and write access for each memory slave from various masters, which are organized in groups.
Page 267: How To Use Ahb Bus Matrix
AHB Bus Matrix How to Use AHB Bus Matrix This section describes how to use the AHB bus matrix in an application. 7.2.1 Design Flow The following steps are used to configure the AHB bus matrix in the application: Configure the AHB bus matrix by using the MSS configurator in the application, as shown in the following figure.
Page 268: Figure 119 Ahb Bus Matrix Configuration Window
AHB Bus Matrix Click on AHB Bus Matrix to configure it. The AHB Bus Matrix configuration window is shown in the following figure. • The AHB bus matrix provides support to remap eNVM, eSRAM and DDR memory regions to location 0x000000000 of the Cortex-M3 ID code space. It also provides an option to remap eNVM for a Soft Processor eNVM Remap.To enable remapping for eNVM, eSRAM and DDR select appropriate option from remapping section of AHB Bus Matrix configurator.
Page 269: Register Map
Libero SoC User Guide. Click Generate Bitstream under Program Design to complete *.fdb file generation. Note: The MSS AHB Bus Matrix supports full behavioral simulation models. Refer to the SmartFusion2 MSS BFM Simulation User Guide for information. Register Map The following table lists the AHB bus matrix control registers in the SYSREG block.
Page 270: High Performance Dma Controller
High Performance DMA Controller High Performance DMA Controller The high performance DMA Controller (HPDMA) provides fast data transfer between the MSS DDR bridge and MSS memories. The MSS memories are eSRAM0, eSRAM1, eNVM0, and eNVM1. The DDR bridge connects to External DDR memory. The following figure shows HPDMA interfacing with AHB Bus Matrix and MSS DDR bridge.
Page 271: Features
High Performance DMA Controller Features • Faster read/write operations with two concurrent AHB masters • 32-bit AHB operation at 200 MHz • 32-bit APB slave interface for control and status registers at 25/50/100/200 MHz • Internal 32-bit control, status, and debug registers •...
Page 272: Figure 122 Hpdma Registers
High Performance DMA Controller 8.2.0.1 Interfaces There are two types of interfaces used for communicating with HPDMA: • 32-bit APB slave interface for configuration • Two AHB master interfaces (AHB-M1, AHB-M2) for data transfers: • AHB Master 1 does the read/write transfers at the AHB bus matrix end •...
Page 273: Figure 123 Dma Controller Flow Chart
High Performance DMA Controller 8.2.0.3 DMA Controller The DMA controller controls and monitors transactions on the source and destination AHB master interfaces. When a descriptor is configured, the DMA controller enables the write buffer controller to read data from the appropriate source memory (AHB bus matrix or MSS DDR bridge) and transfer it into the internal data buffer.
Page 274: Initialization
High Performance DMA Controller 8.2.0.5 Read Buffer Controller The read buffer controller places the address and asserts the ready signal to the AHB master (AHB-M1 or AHB-M2). Depending on the transfer direction, AHB-M1 or AHB-M2 initiates the data transfers from internal data buffer to destination memory.
Page 275: Details Of Operation
High Performance DMA Controller 8.2.2 Details of Operation After initialization, the HPDMA is ready to function in one of the two following data transfer modes: • AHB bus matrix to MSS DDR bridge • MSS DDR bridge to AHB bus matrix For initiation of the above data transfer modes, a descriptor valid bit has to be set (that is, bit 16 of the Descriptor control register is asserted).
Page 276: Figure 124 Enable Hpdma In The Libero Soc Design Mss Configurator
High Performance DMA Controller Enable HPDMA by using MDDR in the application, as shown in the following figure. Figure 124 • Enable HPDMA in the Libero SOC Design MSS Configurator UG0331 User Guide Revision 15.0...
Page 277: Figure 125 Hpdma Transfers Data Between Ddr Memory And Mss Internal Memory
High Performance DMA Controller To configure the HPDMA to transfer data between DDR memory and MSS internal memory, make the selection in the MSS external memory configurator as shown in the following figure. Figure 125 • HPDMA Transfers Data Between DDR Memory and MSS Internal Memory To configure the HPDMA to transfer data between SDR memory and MSS internal memory, make the selection in the MSS external memory configurator as shown in the following figure.
Page 278: Figure 127 Hpdma Driver User Guide
MSS HPDMA transfers. The mss_hpdma firmware driver can also be downloaded from the Microsemi firmware catalog. The following table shows the list of APIs for HPDMA. For more information on the APIs, refer to the SmartFusion2_MSS_HPDMA_Driver_UG shown in the preceding figure.
Page 279: Hpdma Use Models
This section explains the use models and gives directions for using HPDMA in an application. The SmartFusion2 soft memory controller fabric interface controller (SMC_FIC) is used to access external bulk memories other than DDR through the FPGA fabric. The SMC_FIC can be used with a soft memory controller for the MSS to access memories such as SDRAM, flash, and SRAM.
Page 280: Hpdma Controller Register Map
High Performance DMA Controller HPDMA Controller Register Map The following table summarizes the HPDMA controller register map. The sections that follow detail register bit descriptions of status, configuration, and debug registers. All the register bits are active high; on reset they assume default values. Register R/W corresponds to external processor accessibility. The address range of the HPDMA APB registers is x40014000 to x40014FFF.
Page 281: Hpdma Register Bit Definitions
High Performance DMA Controller 8.4.1 HPDMA Register Bit Definitions 8.4.1.1 HPDMA Empty Descriptor Register Table 150 • HPDMAEDR_REG Reset Number Name Value Description HPDMAEDR_DCP_EMPTY[0] Descriptor 0 is empty and ready for software configuration. 1: Descriptor 0 is empty and ready to configure. 0: Descriptor 0 is already configured and descriptor transfer is in progress/queue.
Page 282: Table 150 Hpdmaedr_Reg
High Performance DMA Controller Table 150 • HPDMAEDR_REG (continued) Reset Number Name Value Description HPDMAEDR_DCP_CMPLET[1] Descriptor 1 transfer complete. 1: Descriptor 1 transfer completed successfully. 0: Descriptor 1 transfer not completed. When the descriptor 1 transfer is completed, either with transfer error or transfer done, the HPDMA controller asserts this bit High.
Page 283 High Performance DMA Controller Table 150 • HPDMAEDR_REG (continued) Reset Number Name Value Description HPDMAEDR_DCP_ERR[1] Descriptor 1 transfer error. 1: Descriptor 1 transfer error 0: No descriptor 1 transfer error This bit is asserted High, if an error occurs during the descriptor 1 transfer at either source or destination end.
Page 284 High Performance DMA Controller Table 150 • HPDMAEDR_REG (continued) Reset Number Name Value Description HPDMAEDR_DCP_NON_WORD_ERR[1] 0 Descriptor 1 non-word aligned transfer size error. 1: Descriptor 1 non-word aligned transfer size error 0: No non-word aligned transfer size error This bit is asserted High if a non-word aligned value is configured in the descriptor 1 transfer size field.
Page 285: Table 151 Hpdmad0Sar_Reg
High Performance DMA Controller 8.4.1.2 Descriptor 0 Source Address Register Table 151 • HPDMAD0SAR_REG Bit Number Name Reset Value Description 31:0 HPDMASAR_DCP0_SRC_ADRS 0x00 Descriptor 0 source end memory start address 8.4.1.3 Descriptor 1 Source Address Register Table 152 • HPDMAD1SAR_REG Bit Number Name Reset Value Description 31:0...
Page 286: Table 155 Hpdmad0Dar_Reg
High Performance DMA Controller 8.4.1.6 Descriptor 0 Destination Address Register Table 155 • HPDMAD0DAR_REG Bit Number Name Reset Value Description 31:0 HPDMADAR_DCP0_DST_ADRS 0x00 Descriptor 0 destination end memory start address 8.4.1.7 Descriptor 1 Destination Address Register Table 156 • HPDMAD1DAR_REG Bit Number Name Reset Value Description 31:0...
Page 287: Table 159 Hpdmad0Cr_Reg
High Performance DMA Controller 8.4.1.10 Descriptor 0 Control Register Table 159 • HPDMAD0CR_REG Reset Number Name Value Description 15:0 HPDMACR_DCP0_XFR_SIZE Descriptor 0 transfer size in bytes. Defines number of bytes to be transferred in a descriptor 0 transfer. All zeros in this field indicates 64-KB transfers. As all the transfers are word aligned, 2 LSBs 1:0 are ignored.
Page 288: Table 160 Hpdmad1Cr_Reg
High Performance DMA Controller 8.4.1.11 Descriptor 1 Control Register Table 160 • HPDMAD1CR_REG Reset Number Name Value Description 15:0 HPDMACR_DCP1_XFR_SIZE Descriptor 1 transfer size in bytes. Defines number of bytes to be transferred in a descriptor 1 transfer. All zeroes in this field indicates 64-KB transfers. As all the transfers are word aligned, the 2 LSBs 1:0 are ignored.
Page 289: Table 161 Hpdmad2Cr_Reg
High Performance DMA Controller 8.4.1.12 Descriptor 2 Control Register Table 161 • HPDMAD2CR_REG Reset Number Name Value Description 15:0 HPDMACR_DCP2_XFR_SIZE Descriptor 2 transfer size in bytes. Defines number of bytes to be transferred in a Descriptor 2 transfer. All zeroes in this field indicates 64 KB transfers. As all the transfers are word aligned, 2 LSBs 1:0 are ignored.
Page 290: Table 162 Hpdmad3Cr_Reg
High Performance DMA Controller 8.4.1.13 Descriptor 3 Control Register Table 162 • HPDMAD3CR_REG Reset Number Name Value Description 15:0 HPDMACR_DCP3_XFR_SIZE Descriptor 3 transfer size in bytes. Defines number of bytes to be transferred in a descriptor 3 transfer. All zeroes in this field indicates 64-KB transfers. As all the transfers are word aligned, 2 LSBs, 1:0, are ignored.
Page 291: Table 163 Hpdmad0Sr_Reg
High Performance DMA Controller 8.4.1.14 Descriptor 0 Status Register Table 163 • HPDMAD0SR_REG Reset Number Name Value Description HPDMASR_DCP_ACTIVE[0] Descriptor 0 transfer in progress. 1: Descriptor 0 transfer in progress. 0: Descriptor 0 is in queue when HPDMACR_DCP_VALID[0] bit is set in descriptor 0 Control register. HPDMASR_DCP_CMPLET[0] Descriptor 0 transfer complete.
Page 292: Table 165 Hpdmad2Sr_Reg
High Performance DMA Controller Table 164 • HPDMAD1SR_REG (continued) Reset Number Name Value Description HPDMASR_DCP_DERR[1] Descriptor 1 destination transfer error. 1: Descriptor 1 transfer error 0: No error at destination end during descriptor 1 transfer This bit clears on writing ‘1’ to HPDMAICR_CLR_XFR_INT[1] of the descriptor 1 Interrupt Clear register.
Page 293: Table 166 Hpdmad3Sr_Reg
High Performance DMA Controller 8.4.1.17 Descriptor 3 Status Register Table 166 • HPDMAD3SR_REG Reset Number Name Value Description HPDMASR_DCP_ACTIVE[3] Descriptor 3 transfer in progress. 1: Descriptor 3 transfer in progress. 0: Descriptor 3 is in queue when HPDMACR_DCP_VALID[3] bit is set in descriptor 3 Control register. HPDMASR_DCP_CMPLET[3] Descriptor 2 transfer complete.
Page 294: Table 168 Hpdmad1Ptr_Reg
High Performance DMA Controller 8.4.1.19 Descriptor 1 Pending Transfers Register Table 168 • HPDMAD1PTR_REG Reset Number Name Value Description 15:0 HPDMAPTR_D1_SRC_PNDNG 0 Descriptor 1 source pending transfers in words. This register indicates the internal transfer size counter corresponding to the source end of descriptor 1. At the end of the transfer, zero in this register indicates the successful transfer, and a non-zero value indicates error occurrence at the source during descriptor 1 transfer.
Page 295: Table 170 Hpdmad3Ptr_Reg
High Performance DMA Controller 8.4.1.21 Descriptor 3 Pending Transfers Register Table 170 • HPDMAD3PTR_REG Reset Number Name Value Description 15:0 HPDMAPTR_D3_SRC_PNDNG Descriptor 3 source pending transfers in words. This register indicates the internal transfer size counter corresponding to the source end of descriptor 3. At the end of the transfer, zero in this register indicates the successful transfer, and a non-zero value indicates error occurrence at the source during descriptor 0 transfer.
Page 296: Table 171 Hpdmaicr_Reg
High Performance DMA Controller Table 171 • HPDMAICR_REG (continued) Reset Number Name Value Description HPDMAICR_NON_WORD_INT[0] When this bit is set, HPDMA clears the HPDMAEDR_DCP_NON_WORD_ERR[0] bit in the Empty Descriptor register. These bits always read back as 0. HPDMAICR_NON_WORD_INT[1] When this bit is set, HPDMA clears the HPDMAEDR_DCP_NON_WORD_ERR[1] bit in the Empty Descriptor Register.
Page 297: Sysreg Control Register
High Performance DMA Controller Table 172 • HPDMADR_REG (continued) Reset Number Name Value Description 18:16 HPDMADR_WBC_CST_DBG[2:0] Write buffer controller current state 001 – IDLE 010 – RUN 100 – WAIT 21:19 HPDMADR_RBC_CST_DBG[2:0] Read buffer controller current state 001 – IDLE 010 –...
Page 298: Peripheral Dma
Peripheral DMA Peripheral DMA The peripheral direct memory access (PDMA) is an AHB master associated with the AHB bus matrix, as shown in the following figure. The PDMA allows data transfers from various MSS peripherals to memory, memory to various peripherals, and memory to memory. The peripheral can be MSS peripheral (MMUART, CAN, SPI, and COMM_BLK) or fabric peripheral (FIC_0 and FIC_1).
Page 299: Functional Description
Peripheral DMA Functional Description This section provides the detailed description of the PDMA. 9.2.1 Architecture Overview The PDMA controller mainly consists of the following blocks, as shown in the following figure. • AHB and APB Interfaces • 8-Channel DMA Controller •...
Page 300 Peripheral DMA 9.2.1.2 8-Channel DMA Controller The 8-channel DMA controller consists of eight instances of a single DMA channel, as shown in the preceding figure. Each channel can be configured to perform 8-bit, 16-bit, or 32-bit data transfers from the peripheral to memory, memory to peripheral, and memory to memory. Each DMA channel supports Ping-pong mode for continuous data transfer.
Page 301: Figure 131 Flow Of Ping-Pong Operation On Dma Channel
Peripheral DMA Figure 131 • Flow of Ping-Pong Operation on DMA Channel Write to the following PDMA registers: a. Channel_0_BUFFER_A_SRC_ADDR b. Channel_0_BUFFER_A_DST_ADDR c. Channel_0_BUFFER_B_SRC_ADDR d. Channel_0_BUFFER_B_DST_ADDR Write to Channel_0_BUFFER_A_TRANSFER_COUNT (DMA starts using buffer A) Write to Channel_0_BUFFER_B_TRANSFER_COUNT (DMA will use a buffer B when channel0 buffer A transfer count reaches 0) If interrupt on the DMA...
Page 302: Port List
Peripheral DMA 9.2.1.3 Timing and Control The peripheral ready signals (for example, RxRDY and TxRDY in MMUART) from the SPI, MMUART, COMM_BLK, and CAN are directly connected to the PDMA. The ready signals from the CAN are not used and are tied to logic 1 internally. The PDMA takes care of writing or reading the receive or transmit holding registers within each peripheral using the APB interface.
Page 303: Initialization
Peripheral DMA 9.2.3 Initialization To initiate and setup DMA transactions, PDMA has to be initialized. The initialization process starts with a reset sequence followed by Channel configuration and interrupt configuration. 9.2.3.1 Reset The PDMA registers are reset on power-up. The PDMA can be reset by configuring the following •...
Page 304 9.2.4.2 Posted APB Writes The AHB to APB bridges in the SmartFusion2 device implement posted writes (also known as dump and run) for write accesses to peripherals. PDMA performs a write operation to a peripheral but the data is not written to the peripheral immediately. Therefore, the PDMA block should not start another DMA on this channel based on the state of the ready signal from that peripheral until the write is complete.
Page 305: How To Use The Pdma
Peripheral DMA How to Use the PDMA This following sections describe how to use the PDMA in an application. 9.3.1 Design Flow The following steps are used to enable the PDMA in the application: Enable PDMA by using the MSS configurator in the application, as shown in the following figure. Figure 132 •...
Page 306: Figure 133 Pdma Ahb Bus Master Matrix Configuration
Peripheral DMA Configure the AHB bus matrix master to provide weights to PDMA, as shown in the following figure. Figure 133 • PDMA AHB Bus Master Matrix Configuration To configure the PDMA to transfer data between fabric peripherals (associated on FIC_0 and FIC_1) and MSS memories, select the PDMA configurator, as shown in the following figure.
Page 307: Figure 135 Pdma Signals
MSS PDMA transfers, can also be downloaded from the Microsemi firmware catalog. the following table lists the APIs for PDMA. For more information on the APIs, refer to the Smartfusion2_MSS_PDMA_Driver_UG as shown in the preceding figure.
Page 308: Pdma Use Models
Peripheral DMA Table 176 • MSS PDMA APIs (continued) DMA transfer and control PDMA_start() Starts PDMA transfer PDMA_load_next_buffer() Loads with next buffer of data PDMA_status() Gets the status of PDMA transfer Interrupt control functions PDMA_set_irq_handler() Register PDMA channel interrupt handler functions with the driver PDMA_enable_irq() Enables interrupt for Cortex-M3 processor and channel...
Page 309: Pdma Register Map
Simulation User Guide for more information. PDMA Register Map The following table summarizes each of the registers covered by this document. The base address is 0x40003000. Table 177 • SmartFusion2 SoC FPGA PDMA Register Map Address Register Reset Register Name...
Page 310 Peripheral DMA Table 177 • SmartFusion2 SoC FPGA PDMA Register Map (continued) Address Register Reset Register Name Offset Type Value Description CHANNEL_1_BUFFER_B_TRANSFER_COUNT 0x5C Channel 1 buffer B transfer count CHANNEL_2_CONTROL 0x60 Channel 2 Control register CHANNEL_2_STATUS 0x64 Channel 2 Status register...
Page 311 Peripheral DMA Table 177 • SmartFusion2 SoC FPGA PDMA Register Map (continued) Address Register Reset Register Name Offset Type Value Description CHANNEL_5_CONTROL 0xC0 Channel 5 Control register CHANNEL_5_STATUS 0xC4 Channel 5 Status register CHANNEL_5_BUFFER_A_SRC_ADDR 0xC8 Channel 5 buffer A source...
Page 312: Pdma Configuration Register Bit Definitions
Peripheral DMA 9.4.1 PDMA Configuration Register Bit Definitions The following registers are present in the PDMA engine: 9.4.1.1 RATIO_HIGH_LOW Register Bit Definition Table 178 • Ratio_HIGH_LOW Bit Number Name Reset Value Description [31:8] Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 313: Table 179 Buffer_Status
Peripheral DMA Table 179 • BUFFER_STATUS (continued) Bit Number Name Reset Value Description CH1BUFB If CH_COMP_B for channel 1 is set and if BUF_B_SEL for channel 1 is clear, this bit is asserted. CH1BUFA If CH_COMP_A for channel 1 is set and if BUF_A_SEL for channel 1 is clear, this bit is asserted.
Page 314: Table 180 Channel_X_Control
Peripheral DMA Table 180 • CHANNEL_x_CONTROL (continued) Bit Number Name Reset Value Description CLR_COMP_A When asserted, clears the CH_COMP_A bit in the channel status register and the buffer status register for this buffer in this channel. This causes PDMAINTERRUPT to negate if not being held asserted by another channel.
Page 315: Table 182 Channel_X_Status
Peripheral DMA 9.4.1.4 CHANNEL_x_STATUS Register Bit Definition Table 182 • CHANNEL_x_STATUS Reset Bit Number Name Value Description [31:3] Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 316: Table 185 Channel_X_Buffer_A_Transfer_Count
Peripheral DMA 9.4.1.7 CHANNEL_x_BUFFER_A_TRANSFER_COUNT Register Bit Definition Table 185 • CHANNEL_x_BUFFER_A_TRANSFER_COUNT Reset Bit Number Name Value Description [31:16] Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 317: Sysreg Control Registers
Peripheral DMA SYSREG Control Registers In addition to the specific PDMA registers found in Table 177, page 275, the registers found in the following table also control the behavior of the PDMA peripheral. These registers are located in the SYSREG section of the user's guide and are listed here for convenience. Refer to System Register Block, page 670 for a detailed description of each register and associated bits.
Page 318: Universal Serial Bus Otg Controller
Universal serial bus (USB) is an industry standard that defines cables, connectors, and serial communication protocol used in a bus for connection, communications, and power supply between electronic devices. SmartFusion2 SoC FPGA device contains a USB On-The-Go (OTG) controller as part of the microcontroller subsystem (MSS). SmartFusion2 USB OTG controller provides a mechanism for the USB communication between the SmartFusion2 devices and external USB host/USB device/USB OTG protocol compliant devices.
Page 319: Functional Description
• An OTG device that can dynamically switch roles from the host and the device In all cases (USB host, USB device, or USB OTG), SmartFusion2 USB OTG supports control, bulk, ISO, and interrupt transactions in all 3 modes. Figure 138 • MSS Showing a USB OTG Controller...
Page 320: Figure 139 Usb Otg Controller In Smartfusion2
USB controller is 0x40043000-0x40043FFF. 10.2.1.2 CPU Interface USB OTG controller sends interrupts to the Cortex-M3 processor using the CPU interface. The SmartFusion2 USB OTG controller sends interrupts for the following events: • When packets are transmitted or received •...
Page 321: Usb Otg Controller Interface Signals
The role of the UTM synchronize block is to synchronize between the transceiver macrocell 60 MHz clock domain and the SmartFusion2 USB OTG controller's system clock. This allows the rest of the USB OTG controller to run at the desired system clock. This block also performs the high speed detection handshaking and handles the host negotiation protocol (HNP) and the session request protocol of the OTG specification in point-to-point communications with another USB OTG device.
Page 322: Figure 140 Block Diagram For Connections Between Usb Controller And Ulpi Phy Through Mss
10.2.2.2 UTMI+ (USB 2.0 Transceiver Macrocell Interface+) Interface This is the external interface connecting the SmartFusion2 USB OTG controller to an off-chip UTMI PHY device. For UTMI interface, all the interface signals are routed through the FPGA fabric on to the MSIOs.
Page 323 Universal Serial Bus OTG Controller Table 192 • UTMI+Interface Signals at Fabric Interface in SmartFusion2 Device (continued) Signal Name Direction Description UTMI_LINESTATE[1:0] Shows the current state of single-ended receivers. LINESTATE[0] reflects the state of D+; LINESTATE[1] reflects state of D-.
Page 324: Figure 141 Block Diagram For Connections Between Usb Controller And Utmi Phy Through Fpga Fabric
Universal Serial Bus OTG Controller Table 192 • UTMI+Interface Signals at Fabric Interface in SmartFusion2 Device (continued) Signal Name Direction Description UTMI_DISCHRGVBUS Discharges VBus (used by B devices to ensure that the VBus is low enough before starting a session request protocol (SRP)) UTMI_HOSTDISCON Host mode only;...
Page 325: Usb Otg Controller Operations
USB OTG Controller: Connect/Disconnect Operations 10.2.3.1 Modes of USB OTG Controller Operation The USB OTG Controller in SmartFusion2 device can be used in the following three modes: 10.2.3.1.1 USB Host Mode In this mode, the USB OTG controller acts in a USB host function. As the USB protocol is host driven, the USB host is completely responsible for all the transactions in the bus.
Page 326: Figure 142 Basic Usb Flow Diagram When Usb Controller Is In Host Mode
Universal Serial Bus OTG Controller Figure 142 • Basic USB Flow Diagram when USB Controller is in Host Mode START Initialization 1. Disable/initialize the Watchdog Timer 2. Configure the GPIO for keeping the PHY out of reset 3. Register the callback functions and ISRs 4.
Page 327: Figure 143 Basic Usb Flow Diagram When Usb Controller Is In Usb Device/Peripheral Mode
10.2.3.1.3 USB OTG Mode (Dual Role) In this mode, the SmartFusion2 USB OTG controller must be configured in OTG mode by using the USB controller register. Based on the type of the plug connected to the PHY through the USB OTG receptacle, the controller plays a role as either the USB device or the USB host.
Page 328 USB Cable end types: Each USB cable has an A / microA / miniA end and a B / microB / miniB end. • Entering into host mode: If the micro A end of the cable is plugged into the SmartFusion2 device through the external PHY, the USB controller will take the role of the host and go into Host mode.
Page 329: Figure 144 Basic Usb Flow Diagram When Usb Controller Is In Otg Mode
Universal Serial Bus OTG Controller The following figure shows the flow chart of the overall operation in the USB OTG (dual role) mode. Figure 144 • Basic USB Flow Diagram when USB Controller is in OTG Mode START START Initialization 1.
Page 330: Figure 145 Lpm State Transition Diagram
Universal Serial Bus OTG Controller Flushes all endpoint FIFOs Clears all control/status registers Enables all endpoint interrupts Generates a reset interrupt If the HS Enab bit in POWER_REG (0x40043001) is set, the USB controller tries to negotiate for high speed operation. Whether or not the high speed operation is selected, is indicated by the HS mode bit in POWER_REG.
Page 331: Table 193 Response To Lpm Transaction As Peripheral
Universal Serial Bus OTG Controller POWERDWN then remains asserted until power is removed from the bus (indicating that the device has been disconnected); or resume signaling; or reset signaling is detected on the bus. • Sending Resume Signaling: When resume signaling occurs on the bus, first CLK must be restarted, if necessary.
Page 332 Universal Serial Bus OTG Controller Table 193 • Response to LPM Transaction as Peripheral (continued) Data Pending (Data Resides in Response to the Next LPM LPMXMT LPMEN Transmit FIFOs) transaction 1'b0 Don't Care NYET 1'b1 NYET 1'b1 For all cases shown in the preceding table in which the USB controller responds (no timeout occurs), an LPM interrupt is generated in LPM_INTR_REG (Table 308, page 368).
Page 333 Universal Serial Bus OTG Controller • Initiating Remote Wake-Up: If the software wants to initiate a remote wake-up while the USB controller is in Suspend mode, it should write a 1 to the LPMRES bit in LPM_CTRL_REG (0x40043362)(Peripheral). This bit is self- clearing. Writing a 1 causes resume signaling to be driven on the bus for 50 µs.
Page 334: How To Use Usb Otg Controller
Using the USB macro settings options, the USB controller interface can be configured to either ULPI or UTMI interface. For external USB PHY (ULPI or UTMI) reset, Microsemi recommends to configure GPIO using the GPIO macro in the Libero SoC design software. The following figure highlights these two mandatory blocks for the USB controller configuration in the applications.
Page 335: Figure 147 Mss Usb Configurator With Ulpi Interface Settings
I/O. In the M2S050 devices, only the USBD I/O group is available. Where in the M2S025 and the M2S010, only the USBA, USBB, and USBC I/O groups are available. Based on the SmartFusion2 device selected, the I/O groups can be selected from the USB configurator.
Page 336: Figure 148 Mss Usb Configurator With Utmi Interface Settings
For interfacing the USB OTG controller with UTMI PHY, the interface signals are routed through the FPGA fabric onto the MSIOs. There is no separate I/O grouping like the ULPI interface has, for the SmartFusion2 device variants to use with UTMI PHY.
Page 337: Software: Firmware, Usb Class Specific Code, And Application Code
USB Device mode: As per the device mode functionality, Microsemi recommends that the USB Protocol descriptors are required to be created in the low level drivers. These descriptors are sent to the USB host which the SmartFusion2 is connected to at the time of the USB protocol enumeration processes. UG0331 User Guide Revision 15.0...
Page 338: Figure 151 Firmware Catalog With Mss Usb Firmware Drivers And Sample Class Drivers
Universal Serial Bus OTG Controller If the SmartFusion2 USB OTG controller is used in USB Device mode with the USB standard class like mass storage, human interface device (HID), communications device etc. and have implemented the class driver application, then the SmartFusion2 device will be connected automatically by the USB host (for example, PC), and will perform the data transfers as per the application protocol.
Page 339 Universal Serial Bus OTG Controller Table 194 • APIs available in USB Firmware Drivers and Description of CIL (continued) Description MSS_USB_core_enable_irq() Enables USB IRQ. IRQ is selected by the parameter value provided with this function. MSS_USB_core_disable_irq() Disables USB IRQ. IRQ is selected by the parameter value provided with this function.
Page 340: Table 195 Device Mode Class Driver Apis (Ldl)
Universal Serial Bus OTG Controller Table 195 • Device Mode Class Driver APIs (LDL) Description MSS_USB_device_set_desc_cb_handler() Provides the call-back functions for USB descriptors to this driver. MSS_USB_device_set_class_cb_handler() Provides the call-back functions for USB class implementation to this driver. MSS_USB_device_init() Initializes the MSS USB to operate in Device mode at desired USB speed.
Page 341 Refer to the SmartFusion2 MSS USB Device Core Driver’s User Guide for more information on the API detailed description and parameters to the APIs. UG0331 User Guide Revision 15.0...
Page 342: Usb Otg Controller Clocks And Resets
10.3.4 Programmability 10.3.4.1 Memory Map The address space of the USB OTG controller in SmartFusion2 is from 0x40043000 to 0x40043FFF. All the USB OTG FIFO registers are residing in this address space. 10.3.4.2 USB OTG Controller Registers Map This section describes the register map; bit description of various categories of registers in the USB controller.
Page 343: Common Registers
Universal Serial Bus OTG Controller 10.3.5 Common Registers This section covers all registers in this category along with the address offset, functionality, and per bit details. Table 198 • Common Register Set Description Reset Register Name Address Width Type Value Description FADDR_REG(0x400 0x40043000 8 Write with the 7-bit address of the peripheral part of the...
Page 344: Table 199 Faddr_Reg(0X40043000)
Universal Serial Bus OTG Controller Table 198 • Common Register Set Description (continued) Reset Register Name Address Width Type Value Description TEST_MODE_REG 0x4004300F 8 Puts the USB controller in one of the four test modes for (0x4004300F) high speed operation described in the USB 2.0 specification.
Page 345: Table 201 Tx_Irq_Reg (0X40043002)
Universal Serial Bus OTG Controller Table 200 • POWER_REG (0x40043001) (continued) Reset Number Name Value Function Resume Set by the Cortex-M3 processor (or fabric master) to generate resume signaling when the device is in Suspend mode. In Peripheral mode, the Cortex-M3 processor (or fabric master) should clear this bit after 10 ms (a maximum of 15 ms), to end resume signaling.
Page 346: Table 203 Tx_Irq_En_Reg (0X40043006)
Universal Serial Bus OTG Controller 10.3.5.5 TX_IRQ_EN_REG Bit Definitions Table 203 • TX_IRQ_EN_REG (0x40043006) Reset Number Name Value Function [15:5] Reserved EP4 TxEn Transmit endpoint 4 interrupt enable EP3 TxEn Transmit endpoint 3 interrupt enable EP2 TxEn Transmit endpoint 2 interrupt enable EP1 TxEn Transmit endpoint 1 interrupt enable Endpoint0 interrupt enable...
Page 347: Table 206 Usb_Irq_En_Reg (0X4004300B)
Universal Serial Bus OTG Controller Table 205 • USB_IRQ_REG (0x4004300A) Reset Number Name Value Function Suspend Set when suspend signaling is detected on the bus. Only valid in Peripheral mode. 10.3.5.8 USB_IRQ_EN_REG Bit Definitions Table 206 • USB_IRQ_EN_REG (0x4004300B) Reset Number Name Value...
Page 348: Table 209 Test_Mode_Reg (0X4004300F)
Universal Serial Bus OTG Controller 10.3.5.11 TEST_MODE_REG Bit Definitions Table 209 • TEST_MODE_REG (0x4004300F) Reset Bit Number Name Value Function Force_Host The Cortex-M3 processor (or fabric master) sets this bit to instruct the core to enter Host mode when the session bit is set, regardless of whether it is connected to any peripheral.
Page 349: Indexed Registers
Universal Serial Bus OTG Controller 10.3.6 Indexed Registers This section covers all the registers in this category along with the address offset, functionality, and per- bit details. The registers mapped into this section depend on whether the core is in Peripheral mode (DEV_CTRL_REG.Bit2 = 0) or in Host mode (DEV_CTRL_REG.Bit2 = 1) and the value of the Index register (INDEX_REG).
Page 350: Count0_Reg
Universal Serial Bus OTG Controller Table 211 • Indexed Register Set Description (continued) Reset Register Name Address Width Type Value Description COUNT0_REG 0x40043018 Indicates the number of received data bytes in the endpoint 0 FIFO. The value returned changes as the contents of the FIFO change and is only valid while RxPktRdy (CSR0L_REG.bit0) is set.
Page 351: Table 213 Csr0L_Reg (Peripheral)
Universal Serial Bus OTG Controller 10.3.6.1 TX_MAX_P_REG Bit Definitions Table 212 • TX_MAX_P_REG Reset Number Name Value Function [15:11] If the core is configured with high-bandwidth ISO/interrupt endpoints or packet splitting on bulk endpoints, the register includes 2 or 5 further bits that define a multiplier m which is equal to one more than the value recorded.
Page 352: Table 214 Csr0L_Reg (Host)
Universal Serial Bus OTG Controller Table 213 • CSR0L_REG (Peripheral) (continued) Reset Number Name Value Function SendStall The Cortex-M3 processor (or fabric master) writes a 1 to this bit to terminate the current transaction. The STALL handshake will be transmitted and then this bit will be cleared automatically.
Page 353: Table 215 Csr0H_Reg (Peripheral)
Universal Serial Bus OTG Controller Table 214 • CSR0L_REG (Host) (continued) Reset Number Name Value Function TxPktRdy The Cortex-M3 processor (or fabric master) sets this bit after loading a data packet into the FIFO. It is cleared automatically when a data packet has been transmitted. An interrupt is also generated at this point (if enabled).
Page 354: Table 217 Tx_Csrl_Reg (Peripheral)
Universal Serial Bus OTG Controller 10.3.6.6 TX_CSRL_REG (in Peripheral mode) Bit Definitions Table 217 • TX_CSRL_REG (Peripheral) Reset Number Name Value Function IncompTx When the endpoint is being used for high-bandwidth ISO transfers, this bit is set to indicate where a large packet has been split into 2 or 3 packets for transmission but insufficient IN tokens have been received to send all the parts.
Page 355: Table 218 Tx_Csrl_Reg (Host)
Universal Serial Bus OTG Controller Table 218 • TX_CSRL_REG (Host) (continued) Reset Number Name Value Function RxStall This bit is set when a STALL handshake is received. When this bit is set, any DMA request that is in progress is stopped, the FIFO is completely flushed and the TxPktRdy bit (bit 0 of this register) is cleared.
Page 356 Universal Serial Bus OTG Controller Table 219 • TX_CSRH_REG (Peripheral) (continued) Reset Number Name Value Function DMAReqEnab The Cortex-M3 processor (or fabric master) sets this bit to enable the DMA request for the transmit endpoint. FrcDataTog The Cortex-M3 processor (or fabric master) sets this bit to force the endpoint data toggle to switch and the data packet to be cleared from the FIFO, regardless of whether an ACK was received.
Page 357: Table 220 Tx_Csrh_Reg (Host)
Universal Serial Bus OTG Controller Table 220 • TX_CSRH_REG (Host) (continued) Reset Number Name Value Function Data Toggle When read, this bit indicates the current state of the endpoint 0 data toggle. If Data Toggle Write Enable (bit 1 of this register) is High, this bit may be written with the required setting of the data toggle.
Page 358: Table 222 Rx_Csrl_Reg (Peripheral)
Universal Serial Bus OTG Controller 10.3.6.11 RX_CSRL_REG (in Peripheral mode) Bit Definitions Table 222 • RX_CSRL_REG (Peripheral) Reset Number Name Value Function ClrDataTog 0 The Cortex-M3 processor (or fabric master) writes a 1 to this bit to reset the endpoint data toggle to 0. SentStall This bit is set when a STALL handshake is transmitted.
Page 359: Table 223 Rx_Csrl_Reg (Host)
Universal Serial Bus OTG Controller Table 223 • RX_CSRL_REG (Host) (continued) Reset Number Name Value Function FlushFIFO The Cortex-M3 processor (or fabric master) writes a 1 to this bit to flush the latest packet from the endpoint receive FIFO. The FIFO pointer is reset and the RxPktRdy bit (bit 0 of this register) is cleared.
Page 360: Table 225 Rxpktready Bit Cleared
Universal Serial Bus OTG Controller Table 224 • RX_CSRH_REG (Peripheral) (continued) Reset Number Name Value Function DisNyet Bulk/interrupt transactions: the Cortex-M3 processor (or fabric master) sets this bit to disable the sending of NYET handshakes. When set, all successfully received packets are ACKed, including the point at which the FIFO becomes full.
Page 361: Table 226 Rx_Csrh_Reg (Host)
Universal Serial Bus OTG Controller Table 226 • RX_CSRH_REG (Host) (continued) Reset Number Name Value Function PID Error ISO transactions: The USB controller sets this bit to indicate a PID error in the received packet. Bulk/interrupt transactions: the setting of this bit is ignored.
Page 362: Nak_Limit0_Reg
Universal Serial Bus OTG Controller 10.3.6.19 TX_TYPE_REG Bit Definitions Table 230 • TX_TYPE_REG Reset Number Name Value Function [7:6] Speed Operating speed of the target device 00: Unused (If selected, the target is assumed to be using the same connection speed as the USB controller.) 01: High 10: Full 11: Low...
Page 363: Table 233 Polling Intervals For Transfer Types
Universal Serial Bus OTG Controller 10.3.6.22 Polling Intervals for Transfer Types Table 233 • Polling Intervals for Transfer Types Transfer Type Speed Valid Value (m) Interpretation Interrupt Low speed or full speed 1 – 255 Polling interval is m frames. High speed 1 –...
Page 364: Fifo Registers
Universal Serial Bus OTG Controller 10.3.6.25 CONFIG_DATA_REG Bit Definitions Table 236 • CONFIG_DATA_REG Reset Number Name Value Function MPRxE When set to 1, automatic amalgamation of bulk packets is selected. MPTxE When set to 1, automatic splitting of bulk packets is selected. BigEndian Always 0.
Page 365: Control And Status Registers (Otg, Dynamic Fifo And Version)
Universal Serial Bus OTG Controller Table 238 • FIFO Registers (continued) Address Offset from Reset Register Name 0x40043000 Width R/W Type Value Description EP2_FIFO_REG 0x0028 Writing to this address loads data into the endpoint2 transmit FIFO. Reading from this address unloads data from the endpoint2 transmit FIFO.
Page 366 Universal Serial Bus OTG Controller Table 240 • Additional Control and Status Registers (OTG, Dynamic FIFO, and Version) (continued) Address Offset from Reset Register Name 0x40043000 Width R/W Type Value Description RX_FIFO_SIZE_REG (0x40043063) 0x0063 Controls the size of the selected receive endpoint FIFO.
Page 367: Table 241 Dev_Ctrl_Reg (0X40043060)
Universal Serial Bus OTG Controller 10.3.8.1 DEV_CTRL_REG Bit Definitions Table 241 • DEV_CTRL_REG (0x40043060) Number Name Reset Value Function B-Device Indicates whether the USB controller is operating as the A device or the B device. 0: A device 1: B device Only valid while a session is in progress.
Page 368: Table 243 Misc_Reg (0X40043061)
Universal Serial Bus OTG Controller 10.3.8.3 MISC_REG Bit Definitions Table 243 • MISC_REG (0x40043061) Reset Number Name Value Function TX_EDMA 0: DMA_REQ signal for all IN endpoints is deasserted when MAXP (TX_MAX_P_REG) bytes have been written to an endpoint. This is late mode. 1: DMA_REQ signal for all IN endpoints is deasserted when MAXP-8 (TX_MAX_P_REG-8) bytes have been written to an endpoint.
Page 369: Table 245 Rx_Fifo_Size_Reg (0X40043063)
Universal Serial Bus OTG Controller 10.3.8.5 RX_FIFO_SIZE_REG Bit Definitions Table 245 • RX_FIFO_SIZE_REG (0x40043063) Reset Number Name Value Function Defines whether double-packet buffering is supported. When ‘1’, double-packet buffering is supported. When ‘0’, only single-packet buffering is supported. [3:0] SZ[3:0] Maximum packet size to be allowed for (before any splitting within the FIFO of bulk/high-bandwidth packets prior to transmission).
Page 370: Table 248 Rx_Fifo_Add_Reg (0X40043066)
Universal Serial Bus OTG Controller 10.3.8.8 RX_FIFO_ADD_REG Bit Definitions Table 248 • RX_FIFO_ADD_REG (0x40043066) Reset Number Name Value Function Reserved [12:0] AD[12:0] Start address of the receive endpoint FIFO in units of 8 bytes as given in Table 247, page 336. 10.3.8.9 VBUS_CSR_REG (write only control) Bit Definitions Table 249 •...
Page 371: Table 252 Ulpi And Configuration Registers
Universal Serial Bus OTG Controller 10.3.9 ULPI and Configuration Registers These registers correspond to the ULPI interface and link specific. This section covers all registers in this category along with the address offset, functionality, and per bit details. Table 252 • ULPI and Configuration Registers Reset Register Name Address...
Page 372: Ulpi And Configuration Registers
Universal Serial Bus OTG Controller Table 252 • ULPI and Configuration Registers (continued) Reset Register Name Address Width Type Value Description FS_EOF1_REG 0x4004307D 8 0x77 Sets the minimum time gap that is to be allowed (0x4004307D) between the start of the last transaction and the EOF for full speed transactions.
Page 373: Table 255 Ulpi_Irq_Mask_Reg (0X40043072)
Universal Serial Bus OTG Controller 10.3.9.3 ULPI_IRQ_MASK_REG Bit Definitions Table 255 • ULPI_IRQ_MASK_REG (0x40043072) Reset Number Name Value Function [7:4] Reserved RxCmdIntEn Assert MC_NINT if RxCmdInt (ULPI_IRQ_SRC_REG.bit3) is set. To clear MC_NINT, the software must clear RxCmdEvent (ULPI_CARKIT_CTRL_REG. bit4). ActiveEndIntEn Assert MC_NINT if ActiveEndInt (ULPI_IRQ_SRC_REG.bit2) is set.
Page 374: Table 259 Ulpi_Reg_Ctrl (0X40043076)
Universal Serial Bus OTG Controller 10.3.9.7 ULPI_REG_CTRL Bit Definitions Table 259 • ULPI_REG_CTRL (0x40043076) Reset Number Name Value Function [7:3] Reserved ULPIRdnWr Set by software for register read access. Cleared by software for register write access. ULPIRegCmplt 0 Set by link when register access is complete. This bit must be cleared by software.
Page 375: Table 262 Encoded Utmi Event Signals
Universal Serial Bus OTG Controller Table 261 • ULPI_RAW_DATA_REG (0x40043077) (Synchronous) (continued) Reset Number Name Value Function [1:0] LineState[1:0] UTMI+ LineState signals 10.3.9.10 Encoded UTMI Event Signals Table 262 • Encoded UTMI Event Signals Value RxActive RxError Host Disconnect 10.3.9.11 EP_INFO_REG Bit Definitions Table 263 •...
Page 376: Table 266 Vp_Len_Reg (0X4004307B)
Universal Serial Bus OTG Controller 10.3.9.14 VP_LEN_REG Bit Definitions Table 266 • VP_LEN_REG (0x4004307B) Reset Number Name Value Function [7:0] VPLEN 0x3C Sets the duration of the VBus pulsing charge in units of 546.1 μs. The default setting corresponds to 32.77 ms. 10.3.9.15 HS_EOF1_REG Bit Definitions Table 267 •...
Page 377: 10.3.10 Non-Indexed End Point Control/Status Registers
Universal Serial Bus OTG Controller 10.3.10 Non-Indexed End Point Control/Status Registers The registers available at 10h–1Fh are accessible independently of the setting of the Index register. 100h–10Fh for EP0 registers; 110h–11Fh for EP1 registers; 120h–12Fh for EP2; and so on until EP4. For each set, a separate table for registers is included.
Page 378: Table 272 Endpoint1 Control And Status Registers
Universal Serial Bus OTG Controller 10.3.10.2 Endpoint1 Control and Status Registers Table 272 • Endpoint1 Control and Status Registers Address Offset from Reset Register Name 0x40043000 Width Type Value Description EP1_TX_MAX_P_REG 0x0110 Maximum packet size for host transmit endpoint1. EP1_TX_CSR_REG 0x0112 Provides control and status bits for transmit endpoint1.
Page 379: Table 274 Endpoint3 Control And Status Registers
Universal Serial Bus OTG Controller Table 273 • Endpoint2 Control and Status Registers (continued) Address Offset from Reset Register Name 0x40043000 Width Type Value Description EP2_RX_CSR_REG 0x0126 Provides control and status bits for transfers through the receive endpoint2. EP2_RX_COUNT_REG 0x0128 Holds the number of data bytes in the packet currently in line to be read from the endpoint2 receive FIFO.
Page 380: Fifo_Size_Reg
Universal Serial Bus OTG Controller Table 274 • Endpoint3 Control and Status Registers (continued) Address Offset from Reset Register Name 0x40043000 Width Type Value Description EP3_TX_INTERVAL_REG 0x013B Sets the polling interval for interrupt/ISOC transactions or the NAK response timeout on bulk transactions for host transmit endpoint3.
Page 381: Epx_Rx_Count_Reg
Universal Serial Bus OTG Controller 10.3.10.6 EPx_TX_MAX_P_REG Bit Definitions Table 276 • EPx_TX_MAX_P_REG Reset Number Name Value Function [15:11] Reserved [10:0] EPx_TxMaxP Maximum payload/transaction Maximum payload in bytes transmitted in a single transaction. The value set can be up to 1,024 bytes but is subject to the constraints placed by the USB specification on packet sizes for bulk, interrupt, and ISO transfers in full speed and high speed operations.
Page 382 Universal Serial Bus OTG Controller 10.3.10.9 EPx_TX_TYPE_REG Bit Definitions Table 279 • EPx_TX_TYPE_REG Reset Number Name Value Function [7:6] EPx_Speed Operating speed of the target device: 00: Unused If selected, the target is assumed to be using the same connection speed as the USB controller.
Page 383: Table 281 Epx_Rx_Type_Reg
Universal Serial Bus OTG Controller Table 281 • EPx_RX_TYPE_REG (continued) Reset Number Name Value Function [5:4] EPx_Protocol The Cortex-M3 processor (or fabric master) should set this to select the required protocol for the receive endpoint:. 00: Control 01: ISO 10: Bulk 11: Interrupt [3:0] EPx_Target Endpoint...
Page 384: 10.3.11 Extended Registers
Universal Serial Bus OTG Controller 10.3.11 Extended Registers These registers correspond to extended register set. This section covers all registers in this category along with the address offset, functionality, and per bit details. Table 284 • Extended Registers Description Address Offset from 0x40043...
Page 385: Table 285 Epx_Rq_Pkt_Count_Reg (0X40043Xyz)
Universal Serial Bus OTG Controller Table 284 • Extended Registers Description (continued) Address Offset from 0x40043 Reset Register Name Width Type Value Description C_T_HSBT_REG 0x0348 Per USB 2.0, Section 7.1.19.2, a high speed (0x40043348) host or device expecting a response to a transmission must not timeout the transaction, if the inter packet delay is less than 736 bit times, and it must timeout the transaction if no...
Page 386: Table 287 Tx_Dpkt_Buf_Dis_Reg (0X40043342)
Universal Serial Bus OTG Controller 10.3.11.3 TX_DPKT_BUF_DIS_REG Bit Definitions Table 287 • TX_DPKT_BUF_DIS_REG (0x40043342) Reset Number Name Value Function [15:5] Reserved EP4 TxDPktBufDis Transmit Double Packet Buffer Disable for endpoint 4. EP3 TxDPktBufDis Transmit Double Packet Buffer Disable for endpoint 3. EP2 TxDPktBufDis Transmit Double Packet Buffer Disable for endpoint 2.
Page 387: 10.3.12 Direct Memory Access (Dma) Registers
Universal Serial Bus OTG Controller 10.3.11.7 Turnaround Timeout Period Settings Table 291 • Turnaround Timeout Period Settings Register Value HS Turnaround Timeout (HS bit times) HS Turnaround Timeout (µs) 1.534 1.667 1.801 1.934 2.067 1,056 2.201 1,120 2.334 1,184 2.467 1,248 2.601 1,312...
Page 388 Universal Serial Bus OTG Controller Table 292 • DMA_REGISTER Description (continued) Address Offset from 0x400430 Reset Register Name Width Type Value Description CH1_DMA_ADDR_REG 0x0208 Identifies the current memory address of the DMA channel 1. The initial memory address written to this register must have a value such that its modulo 4 value is equal to 0.
Page 389: Table 293 Dma_Int_Reg (0X40043200)
Universal Serial Bus OTG Controller Table 292 • DMA_REGISTER Description (continued) Address Offset from 0x400430 Reset Register Name Width Type Value Description CH4_DMA_CTRL_REG 0x0234 This register provides the DMA transfer control for Channel 4. The enabling, transfer direction, Transfer mode, and the DMA burst modes are controlled by this register.
Page 390: Table 295 Chx_Dma_Addr_Reg (0X40043208)
Universal Serial Bus OTG Controller Table 294 • CHx_DMA_CTRL_REG (0x40043204) (continued) Reset Number Name Value Function DMA_ERR Bus error bit. Indicates that a bus error has been observed on the input AHB_HRESPM[1:0] coming from the AHB bus matrix, originating from the Cortex-M3 processor (or fabric master).
Page 391: 10.3.13 Multipoint Control And Status Registers
Universal Serial Bus OTG Controller 10.3.12.5 CHx_DMA_COUNT_REG Bit Definitions Table 296 • CHx_DMA_COUNT_REG (0x4004320C) Reset Number Name Value Function [31:0] DMA_COUNT 0 The DMA memory address for the corresponding DMA channel. If DMA is enabled with a count of 0, the bus will not be requested and a DMA interrupt will be generated.
Page 392 Universal Serial Bus OTG Controller Table 297 • Additional Multipoint CSR Description (continued) Address Offset from 0x400430 Reset Register Name Width Type Value Description EP0_TX_HUB_PORT_REG 0x0083 This register only needs to be written where a full speed or low speed device is connected to the transmit endpoint0 via a high speed USB 2.0 hub which carries out the necessary transaction translation.
Page 393 Universal Serial Bus OTG Controller Table 297 • Additional Multipoint CSR Description (continued) Address Offset from 0x400430 Reset Register Name Width Type Value Description EP1_RX_HUB_ADDR_REG 0x008E Need to be written where a full speed or low speed device is connected to receive endpoint1 through a high speed USB 2.0 hub which carries out the necessary transaction translation to convert between high speed transmission and...
Page 394 Universal Serial Bus OTG Controller Table 297 • Additional Multipoint CSR Description (continued) Address Offset from 0x400430 Reset Register Name Width Type Value Description EP2_RX_FUNC_ADDR_REG 0x0094 Records the address of the target function that is to be accessed through endpoint2 for receive. Required in Host mode.
Page 395 Universal Serial Bus OTG Controller Table 297 • Additional Multipoint CSR Description (continued) Address Offset from 0x400430 Reset Register Name Width Type Value Description EP3_TX_HUB_PORT_REG 0x009B Needs to be written where a full speed or low speed device is connected to transmit endpoint3 through a high speed USB 2.0 hub which carries out the necessary transaction translation.
Page 396 Universal Serial Bus OTG Controller Table 297 • Additional Multipoint CSR Description (continued) Address Offset from 0x400430 Reset Register Name Width Type Value Description EP4_TX_HUB_ADDR_REG 0x00A2 Needs to be written where a full speed or low speed device is connected to transmit endpoint4 through a high speed USB 2.0 hub which carries out the necessary transaction translation to convert between high speed transmission and...
Page 397: Table 298 Epx_Tx_Func_Addr_Reg (0X40043080)
Universal Serial Bus OTG Controller 10.3.13.2 EPx_TX_FUNC_ADDR_REG Bit Definitions Table 298 • EPx_TX_FUNC_ADDR_REG (0x40043080) Reset Number Name Value Function [6:0] TxFuncAddr Address of target function for transmit endpointx Notes: • Allowed values of x are 0, 1, 2, 3, and 4, corresponding to endpoints 0, 1, 2, 3, and 4. •...
Page 398: Table 302 Epx_Tx_Hub_Port_Reg (0X40043083)
Universal Serial Bus OTG Controller 10.3.13.5 EPx_RX_HUB_ADDR_REG Bit Definitions Table 301 • EPx_RX_HUB_ADDR_REG Reset Number Name Value Function Multiple Translators Records whether the hub has multiple transaction translators (set to ‘0’ if single transaction translator; set to ‘1’ if multiple transaction translators). [6:0] Rx Hub Address Address of this USB 2.0 hub for receive...
Page 399: 10.3.14 Link Power Management Registers
Universal Serial Bus OTG Controller 10.3.14 Link Power Management Registers 10.3.14.1 Link Power Management Register Descriptions Table 304 • Link Power Management Register Descriptions Address Offset from 0x400430 Reset Register Name Width Type Value Description LPM_ATTR_REG 0x0360 Defines the attributes of an LPM transaction and sleep (0x40043360) cycle.
Page 400: Table 305 Lpm_Attr_Reg (0X40043360)
Universal Serial Bus OTG Controller 10.3.14.2 LPM_ATTR_REG Bit Definitions Table 305 • LPM_ATTR_REG (0x40043360) Reset Number Name Value Function [15:12] EndPnt This is the endpoint that is in the token packet of the LPM transaction. [11:9] Reserved RmtWak This bit is the remote wake-up enable bit. 0: Remote wake-up is not enabled.
Page 401: Table 307 Lpm_Ctrl_Reg (0X40043362) (Host)
Universal Serial Bus OTG Controller Table 306 • LPM_CTRL_REG (0x40043362)(Peripheral) (continued) Reset Number Name Value Function LPMXMT 0 Instructs the USB controller to transition to the L1 state upon the receipt of the next LPM transaction. This bit is only effective if LPMEN (bits[3:2] of this register) is set to 11.
Page 402: Table 310 Lpm_Intr_Reg (0X40043364) (Host Mode)
Universal Serial Bus OTG Controller 10.3.14.6 LPM_INTR_REG (Peripheral) Bit Definitions Table 309 • LPM_INTR_REG (0x40043364)(Peripheral Mode) Reset Number Name Value Function [7:6] Reserved LPMERR This bit is set if an LPM transaction is received that has a LinkState field (LINK_ATTR_REG.bits[3:0]) that is not supported. In this case, the response to the transaction is a STALL.
Page 403: Table 311 Lpm_Faddr_Reg (0X40043365)
Universal Serial Bus OTG Controller Table 310 • LPM_INTR_REG (0x40043364) (Host Mode) (continued) Reset Number Name Value Function LPMNY This bit is set when an LPM transaction is transmitted and the device responds with a NYET. LPMST This bit is set when an LPM transaction is transmitted and the device responds with a STALL.
Page 404: 10.3.15 Usb System Registers
Universal Serial Bus OTG Controller 10.3.15 USB System Registers These registers are in the System registers block for the SmartFusion2 devices. This subset of registers, and in some cases bit fields, control the configuration and behavior of the USB controller.
Page 405 Universal Serial Bus OTG Controller 10.3.15.2 USB_IO_INPUT_SEL_CR Register Bit Definitions Table 313 • USB_IO_INPUT_SEL_CR Reset Number Name Address Value Function USB_IO_INPUT_SEL 0x40038064 Selects one of the four USB data interfaces from IOMUXCELLs and I/O pads. Following are the allowed values: 00: USBA interface can be connected to USB controller 01: USBB interface can be connected to USB controller 10: USBC interface can be connected to USB controller...
Page 406 Universal Serial Bus OTG Controller 10.3.15.5 USB_EDAC_ADR Register Bit Definitions Table 316 • USB_EDAC_ADR Reset Number Name Address Value Function [10:0] USB_EDAC_1E_AD 0x40038120 Address from USB memory on which a 1-bit SECDED error is occurred [21:11] USB_EDAC_2E_AD Address from USB memory on which a 2-bit SECDED error is occurred 10.3.15.6 USB_SR Register Bit Definitions Table 317 •...
Page 407 Universal Serial Bus OTG Controller UG0331 User Guide Revision 15.0...
Page 408: Ethernet Mac
The tri-speed (10/100/1000 Mbps) Ethernet medium access controller (TSEMAC) is a medium access controller which can be configured to 10/100/1000 Mbps data transfer rate (line speed) between the host processor and Ethernet network. The SmartFusion2 SoC FPGA device has one instance of the TSEMAC peripheral as part of the microcontroller subsystem (MSS).
Page 409: Functional Description
The TSEMAC controller is interfaced through the advanced high-performance bus (AHB) matrix in the MSS. SmartFusion2 TSEMAC provides three interfaces (MII, GMII, and TBI) to connect to the external PHY. The following figure shows the block diagram for the connections between the EMAC and FPGA fabric.
Page 410 Ethernet MAC 11.2.1.1 AHB Engine The EMAC can be accessed from an AHB system bus using the AHB engine. The AHB engine module is positioned between the AHB system bus and the MAC TX and RX FIFO. The AHB Engine includes the following modules: •...
Page 411: Tsemac Phy Interfaces
Ethernet MAC 11.2.1.3.6 PEMGT MII Management The PEMGT sub-module drives the MII Management Interface where the control and status information is exchanged with the attached PHY. 11.2.1.4 MAC Statistics Module The MAC Statistics module is a register-based, statistics-gathering module. The MAC Statistics module offers 37 separate counters, which can be used either to count or to accumulate conditions (such as dropped frames which occur as packets), that are transmitted or received.
Page 412: Table 320 Mii Ports
Ethernet MAC The following tables list the port names, port groups, and direction information for the default supported MII, GMII and TBI PHY interfaces. Table 320 • MII Ports Port Name Port Group Direction Description MII_TXD[3:0] MAC_MII_FABRIC Indicates MII transmit data MII_TX_EN MAC_MII_FABRIC Indicates MII transmit data enable...
Page 413: Table 322 Tbi Ports
Ethernet MAC Table 321 • GMII Ports (continued) Port Name Port Group Direction Description GMII_TX_CLK MAC_GMII_FABRIC In Indicates GMII transmit clock. 25 MHz for 100-megabit mode and 2.5-megabit for 10-megabit mode. GMIII_TXD, GMII_TX_EN, GMII_TX_ER signals are synchronized to GMII_TX_CLK. GMII_GTX_CLK MAC_GMII_FABRIC In Indicates gigabit 125 MHz transmit clock input for 1000-megabit mode.
Page 414: Figure 154 Rmii, Rgmii, Rtbi, Revmii, Smii Derived From Available Protocols By Appropriate Wrapper In Fabric
Ethernet MAC Figure 154 • RMII, RGMII, RTBI, RevMII, SMII Derived from Available Protocols by Appropriate Wrapper in Fabric SmartFusion2 Ethernet Mux/ Demux Matrix MS_MAC FPGA Fabric Wrapper for GMII/MII to RMII/RGMII/ RevMII/SMII MSIO RMII/RGMII/ RevMII/SMII The following figure depicts TBI to SERDES (EPCS Mode) for SGMII Interface.
Page 415: Emac Operation
Ethernet MAC 11.4 EMAC Operation Before any DMA transfers can be carried out, two sets of descriptors are needed to be initialized in the host memory. One descriptor is for the transmit operations and the other is for the receive operations. Each set of descriptors takes the form of a linked list typically closed to form a ring buffer.
Page 416: Transmit Operation
Ethernet MAC Table 325 • Packet Size (continued) [20:16] FTPP Overrides The 5-bit field containing the FIFO transmit per-packet override flags signaled to the A-MCXFIFO during the packet transmission. The bits are encoded as follows: 20: FIFO transmit control frame flag. 19:18: FIFO transmit per-packet pad mode flag.
Page 417: Receive Operation
Ethernet MAC If the empty flag is ‘1’, the DMA terminates the transmit operation and then an interrupt is generated for TxUnderrun if enabled. The DMA interrupts register shows TxUnderrun as the source of this interrupt. Any further transfers require the DMA Tx descriptor register to be updated to record the start position in the ring buffer and to set the TxEnable bit to ‘1’...
Page 418: How To Use Tsemac
Ethernet MAC The software should respond to the RxPktReceived interrupt by reading the packet from its location in the ring buffer and then setting the Empty Flag in the descriptor to ‘1’ again to mark this segment of the ring buffer as available for storing further received packets. If a bus error occurs, the DMA controller terminates the sequence of the receive packet transfers, sets the Bus Error bit in the DMA_RX_STATUS register, and clears the RxEnable bit in the DMA_RX_CTRL register.
Page 419: Figure 157 Line Speed Selection In Mss Emac Configurator
Ethernet MAC The following figure shows how to select the line speed for the selected interface. Figure 157 • Line Speed Selection in MSS EMAC Configurator Using the MSS EMAC configurator, the management interface can be selected. The management interface is used to exchange the control and status information with the external PHY. UG0331 User Guide Revision 15.0...
Page 420: Figure 158 External Phy Management Interface Selections In Mss Emac Configurator
Ethernet MAC The following figure shows how to select the PHY management interface. Figure 158 • External PHY Management Interface Selections in MSS EMAC Configurator UG0331 User Guide Revision 15.0...
Page 421: Sgmii Interface Configuration
Ethernet MAC 11.5.1 SGMII Interface Configuration Select the interface as TBI, line speed as required. Enable the management interface check box as shown in the following figure. Figure 159 • MSS Ethernet Configurator with TBI interface Connect TBI signals to SERDES, which is configured for EPCS mode, as shown in the following figure.
Page 422: Figure 161 I/O Editor With Sgmii And Phy Ports
Ethernet MAC In design flow window of Libero SoC under compile option open Edit I/O attributes option and assign pin names to PHY interface as shown in the following figure. Figure 161 • I/O Editor With SGMII and PHY Ports UG0331 User Guide Revision 15.0...
Page 423: Secded Features For Tsemac Buffers
Figure 162 • SECDED Configurator with Ethernet TX RAM and Ethernet RX RAM Configuration Options Microsemi provides TSEMAC firmware drivers to use with the application development. The SmartFusion2 TSEMAC firmware drivers can be downloaded from the Firmware Catalog. The TSEMAC firmware drivers provides APIs-to-TSEMAC services. Refer to the SmartFusion2 TSEMAC Driver User Guide for the list of APIs and their descriptions.
Page 424: Figure 163 Firmware Catalog Showing The Generation Of Sample Project For Tsemac
Figure 163 • Firmware Catalog Showing the Generation of Sample Project for TSEMAC Microsemi provides the device drivers for the TSEMAC controller for SmartFusion2 device and recommends using these drivers for the application development.
Page 425: Table 327 Tsemac Firmware Drivers For Initialization And Configuration
Ethernet MAC The following table lists the APIs available in TSEMAC firmware drivers for initialization and configuration. Table 327 • TSEMAC Firmware Drivers for Initialization and Configuration Description MSS_MAC_cfg_struct_def_init The MSS_MAC_cfg_struct_def_init() function initializes a mss_mac_cfg_t configuration data structure to default values. The default configuration uses the MII interface connected to a PHY at address 0x00 which is set to auto-negotiate at all available speeds up to 1000Mbps.
Page 426: Sysreg Control Register For Emac
Refer to G4Main MSS Ethernet MAC driver User's Guide for more information on the API detailed description and parameters to the APIs. Note: The MSS Ethernet does not support full behavioral simulation models. Refer to SmartFusion2 MSS BFM Simulation User Guide for more information.
Page 427: Emac Configuration Register Summary
Ethernet MAC 11.7 EMAC Configuration Register Summary Each descriptor comprises a sequence of three 32-bit memory locations as shown in Table 323, page 381. The following table summarizes each of the registers covered in this document. The EMAC base address is 0x40041000.
Page 428: Table 334 Emac A-Mcxfifo Register Map
Ethernet MAC Table 333 • EMAC PE-MCXMAC Register Map (continued) Address Register Register Name Offset Type Reset Value Description MII_STATUS 0x30 Following an MII Mgmt read cycle, the 16-bit data can be read from this location. MII_INDICATORS 0x34 This indicates MII management block is currently performing an MII Mgmt read or write cycle.
Page 429: Table 335 Emac Pe-Mstat Transmit And Receive Counters Register Map
Ethernet MAC Table 334 • EMAC A-MCXFIFO Register Map (continued) Address Register Register Name Offset Type Reset Value Description FIFO_RAM_ACCESS6 0x78 The FIFO RAM access register 6 is intended for non-real-time RAM testing and debug. FIFO_RAM_ACCESS7 0x7C The FIFO RAM access register 7 is intended for non-real-time RAM testing and debug.
Page 430: Table 337 Emac Pe-Mstat Transmit Counters Register Map
Ethernet MAC Table 336 • EMAC PE-MSTAT Receive Counters Register Map (continued) Register Address Register Reset Name Offset Type Value Description RALN 0xBC This is incremented for each received frame from 64 to 1518, which contains an invalid FCS and is not an integral number of bytes.
Page 431: Table 338 Emac M-Sgmii Register Map
Ethernet MAC Table 337 • EMAC PE-MSTAT Transmit Counters Register Map (continued) Register Address Register Name Offset Type Reset Value Description TXCL 0x108 This is incremented for each frame that experiences 16 collisions during the transmission and is aborted. TNCL 0x10C This is incremented by the number of collisions experienced during the transmission of a frame.
Page 432 Ethernet MAC Table 338 • EMAC M-SGMII Register Map (continued) Address Register Register name Offset Type Reset Value Description RESERVED 0x03 Reserved AN SGMII 0x04 This indicates that the link is up when the M-SGMII is ADVERTISEMENT integrated into a PHY and is communicating with the SGMII module in a MAC.
Page 433: Emac Register Bit Definitions
Ethernet MAC Minimal configuration, required for MAC to make it functional in 1000 Mbps mode of operation, is given below: CFG1= 32'h0000_0035 //Rx/Tx flow control enable, Rx/Tx-Enable CFG2 = 32'h0000_7202 //Preamble=7, byteMode, CRC-enable STATION_ADDRESS1 = 32'hA5A4_A3A2 //Station Address 1-4 STATION_ADDRESS2 = 32'hA1A0_0000 //Station Address 5-6 FIFO_CFG0 = 32'h0000_FF00 //Enable FIFO transmit and receive modules...
Page 434: Table 342 Dma_Rx_Ctrl
Ethernet MAC Table 342 • DMA_RX_CTRL Bit Number Name Reset Value Description [31:1] Reserved Reserved Rx Enable Setting this bit enables DMA receive packet transfers. The bit is cleared by the built-in DMA controller whenever it encounters an Rx overflow or bus error state. Table 343 •...
Page 435: Table 345 Dma_Irq_Mask
Ethernet MAC Table 345 • DMA_IRQ_MASK (continued) Bit Number Name Reset Value Description RxPktReceived Setting this bit to ‘1’ enables the RxPktReceived bit in the Mask DMARxStatus register as an interrupt source. Bus Error Mask Setting this bit to ‘1’ enables the Bus Error bit in the DMATxStatus register as an interrupt source.
Page 436: Table 348 Cfg2
Ethernet MAC Table 347 • CFG1 (continued) Bit Number Name Reset Value Description RESET RX MAC Setting this bit puts the PERMC Receive MAC control in reset. CONTROL RESET TX MAC Setting this bit puts the PETMC Transmit MAC control in reset. CONTROL RESET RX Setting this bit puts the PERFN receive function block in reset.
Page 437: Table 349 Ifg
Ethernet MAC Table 348 • CFG2 (continued) Bit Number Name Reset Value Description [9:8] INTERFACE This field determines the type of interface the MAC is connected to. MODE The Interface mode settings are as follows. Interface mode Bit 9 Bit 8 Reserved Nibble mode (10/100 Mbps MII/RMII/SMII, …...
Page 438 Ethernet MAC Table 349 • IFG (continued) Reset Bit Number Name Value Description [15:8] MINIMUM IFG 0x50 This programmable field represents the minimum size of ENFORCEMENT management gap (IFG) to enforce between frames (expressed in bit times). A frame whose IFG is less than the programmed minimum IFG enforcement value is dropped.
Page 439: Table 350 Half_Duplex
Ethernet MAC Table 350 • HALF_DUPLEX (continued) Reset Bit Number Name Value Description [11:10] Reserved Reserved [9:0] COLLISION WINDOW 0x37 This programmable field represents the slot time or collision window during which collisions might occur in a properly configured network. Since the collision window starts at the beginning of the transmission, the preamble and start frame delimiter (SFD) are included.
Page 440: Table 353 Mii_Config
Ethernet MAC Table 353 • MII_CONFIG (continued) Bit Number Name Reset Value Description SCAN AUTO Setting this bit causes MII Mgmt to continually read from a INCREMENT set of PHYs of contiguous address space. The starting address of the PHY is specified by the content of the PHY address field, which is recorded in the MII Mgmt Address register.
Page 441: Table 355 Mii_Address
Ethernet MAC Table 355 • MII_ADDRESS Bit Number Name Reset Value Description [31:13] Reserved Reserved [12:8] PHY ADDRESS 0x00 This field represents the 5-bit PHY address field used in Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved).
Page 442: Table 359 Interface_Ctrl
Ethernet MAC Table 359 • INTERFACE_CTRL (continued) Bit Number Name Reset Value Description TBIMODE Setting this bit configures the A-RGMII module to expect TBI signals at the GMII interface. This bit should not be asserted unless this mode is being used. GHDMODE Setting this bit configures the A-RGMII module to expect half- duplex GMII at the GMII interface.
Page 443: Table 360 Interface_Status
Ethernet MAC Table 360 • INTERFACE_STATUS Bit Number Name Reset Value Description [31:11] Reserved Reserved Reserved Reserved EXCESS DEFER This bit sets when the MAC excessively defers a transmission. It clears when read. This bit latches high. CLASH When read as a ‘1’, the Serial MII module is in the MAC to MAC mode with the partner in 10 Mbps and/or half-duplex mode indicative of a configuration error.
Page 444: Table 362 Station_Address2
Ethernet MAC Table 362 • STATION_ADDRESS2 Bit Number Name Reset Value Description [31:24] STATION ADDRESS This field holds the fifth octet of the station address. [23:16] STATION ADDRESS This field holds the sixth octet of the station address. Table 363 • FIFO_CFG0 Bit Number Name Reset Value Description...
Page 445: Table 363 Fifo_Cfg0
Ethernet MAC Table 363 • FIFO_CFG0 (continued) Bit Number Name Reset Value Description frfenreq When asserted, this bit requests for enabling the FIFO fabric receive interface module. When de-asserted, this bit requests for disabling of the FIFO fabric receive interface module. srfenreq When asserted, this bit requests for enabling the FIFO PE-MCXMAC receive interface module.
Page 446: Table 365 Fifo_Cfg2
Ethernet MAC Table 365 • FIFO_CFG2 (continued) [15:13] Reserved Reserved [12:0] cfglwm 0x1FFF This bit represents the minimum number of 4 byte words that are simultaneously stored in the receive RAM before transmit flow control enables and pause value facilitates an XON pause control frame in response to a previously transmitted XOFF pause control frame.
Page 447: Table 367 Fifo_Cfg4
Ethernet MAC Table 367 • FIFO_CFG4 Bit Number Name Reset Value Description [31:18] Reserved Reserved [17:0] hstfltrfrm These configuration bits are used to signal the drop frame conditions internal to the A-MCXFIFO. The bits correspond to the receive statistics vector input to A- MCXFIFO on a one per one basis.
Page 448: Table 368 Fifo_Cfg5
Ethernet MAC Table 368 • FIFO_CFG5 (continued) hstsrfullclr This bit should be written when it is desired to clear the srfull indicator bit. After the hstfullclr assertion, the srfull should be read until it becomes unasserted. cfgbytmode This bit should be asserted when the PE-MCXMAC is configured for GMII mode.
Page 449: Table 371
Ethernet MAC Table 370 • FIFO_RAM_ACCESS1 Bit Number Name Reset Value Description [31:0] hsttramwdat Host transmit RAM write data Table 371 • FIFO_RAM_ACCESS2 Bit Number Name Reset Value Description hsttramrreq Host transmit RAM read request hsttramrack Host transmit RAM read acknowledge [29:24] Reserved Reserved...
Page 450: Table 377 Tr64
Ethernet MAC Table 375 • FIFO_RAM_ACCESS6 Bit Number Name Reset Value Description hstrramrreq Host receive RAM read request hstrramrack Host receive RAM read acknowledge [29:24] Reserved Reserved [23:16] hstrramrdat Host receive RAM read data [39:32] This is the upper byte of the receive FIFO RAM data that is read at the address of the hstrramwadx[10:0] if the hstrramwadx[13] is negated and the hstrramwreq is asserted.
Page 451: Table 380 Tr511
Ethernet MAC Table 380 • TR511 Reset Bit Number Name Value Description [31:18] Reserved Reserved [17:0] TR511 Transmit and receive 256 to 511 byte frame counter: Incremented for each good or bad, transmitted and received frame, which is 256 to 511 bytes in length inclusive (excluding framing bits but including FCS bytes).
Page 452: Table 387 Rmca
Ethernet MAC Table 385 • RPKT Bit Number Name Reset Value Description [31:18] Reserved Reserved [17:0] RPKT Receive packet counter: Incremented for each frame received packet (including bad packets, all the unicast, broadcast, and multicast packets). Table 386 • RFCS Bit Number Name Reset Value...
Page 453: Table 391 Rxuo
Ethernet MAC Table 391 • RXUO Bit Number Name Reset Value Description [31:12] Reserved Reserved [11:0] RXUO Receive unknown OP code counter: Incremented each time a MAC control frame containing an op code other than a PAUSE is received. Table 392 • RALN Bit Number Name Reset Value...
Page 454: Table 396 Rund
Ethernet MAC Table 396 • RUND Bit Number Name Reset Value Description [31:12] Reserved Reserved [11:0] RUND Receive undersize packet counter: Incremented each time a frame is received which is less than 64 bytes in length and contains a valid FCS. This does not look at Range, Length errors. Table 397 •...
Page 455: Table 401 Tbyt
Ethernet MAC Table 401 • TBYT Bit Number Name Reset Value Description [31:24] Reserved Reserved [23:0] TPKT Transmit byte counter: Incremented by the number of bytes that are transmitted including fragments of frames, which are involved in collisions. This count does not include preamble/SFD or jam bytes.
Page 456: Tscl
Ethernet MAC Table 406 • TDFR Bit Number Name Reset Value Description [31:12] Reserved Reserved [11:0] TDFR Transmit deferral packet counter: Incremented for each frame, which is deferred on its first transmission attempt. This does not include frames involved in collisions. Table 407 •...
Page 457: Tncl
Ethernet MAC Table 412 • TNCL Bit Number Name Reset Value Description [31:13] Reserved Reserved [12:0] TNCL Transmit total collision counter: Incremented by the number of collisions experienced during the transmission of a frame due to simultaneous transmitting and receiving. Table 413 •...
Page 458: Tovr
Ethernet MAC Table 418 • TOVR Bit Number Name Reset Value Description [31:12] Reserved Reserved [11:0] TOVR Transmit oversize frame counter: incremented for each oversized transmitted frame with a correct FCS value. Table 419 • TUND Bit Number Name Reset Value Description [31:12] Reserved...
Page 459: Table 422 Car2
Ethernet MAC Table 421 • CAR1 (continued) C1RCD Carry register 1 RCDE counter carry bit C1RCS Carry register 1 RCSE counter carry bit C1RUN Carry register 1 RUND counter carry bit C1ROV Carry register 1 ROVR counter carry bit C1RFR Carry register 1 RFRG counter carry bit C1RJB Carry register 1 RJBR counter carry bit...
Page 460: Table 423 Cam1
Ethernet MAC Table 423 • CAM1 Bit Number Name Reset Value Description M164 Mask register 1 TR64 counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit M1127 Mask register 1 TR127 counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit M1255...
Page 461: Table 424 Cam2
Ethernet MAC Table 423 • CAM1 (continued) Bit Number Name Reset Value Description M1RAL Mask register 1 RALN counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit M1RFL Mask register 1 RFLR counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit M1RCD...
Page 462 Ethernet MAC Table 424 • CAM2 (continued) Bit Number Name Reset Value Description M2TFG Mask register 2 TFRG counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit M2TBY Mask register 2 TBYT counter carry bit 0: Unmask the counter carry bit 1: Mask the counter carry bit M2TPK...
Page 463: Table 425 Sgmii Control
Ethernet MAC Table 425 • SGMII CONTROL Reset Bit Number Name Value Description PHY RESET Setting this bit causes the PETEX, PEREX, and PEANX sub-modules in the M-SGMII core to be reset. This bit is self-clearing. LOOP BACK Setting this bit causes the M-SGMII loopback. Clearing this bit results in normal operation.
Page 464: Table 427 An Sgmii Advertisement
Ethernet MAC Table 427 • AN SGMII ADVERTISEMENT Bit Number Name Reset Value Description LINK UP Assertion of this bit indicates that the link between M-SGMII and PHY is up. [14:13] Reserved Reserved. FULL DUPLEX 0x0 Assertion of this bit indicates that the link between M-SGMII and PHY is up and transferring data in Full-duplex mode.
Page 465: An Link Partner Base
Ethernet MAC Table 429 • AN EXPANSION Bit Number Name Reset Value Description [15:3] Reserved Reserved. NEXT PAGE ABLE Returns ‘1’ on read to indicate that the local device supports the next page function. PAGE RECEIVED Returns ‘1’ on read to indicates that a new page has been received and stored in the applicable AN LINK PARTNER BASE PAGE ABILITY...
Page 466: Table 431 An Next
Ethernet MAC Table 431 • AN NEXT PAGE TRANSMIT (continued) ACKNOWLEDGE Indicates link partner’s ability to comply with the message. When ‘1’, Link Partner complies with message. When ‘0’, link partner cannot comply with message. TOGGLE Used to ensure synchronization with the link partner during next page exchange.
Page 467: Table 433 Jitter Diagnostics
Ethernet MAC Table 433 • JITTER DIAGNOSTICS Bit Number Name Reset Value Description JITTER Set this bit to enable the M-SGMII to transmit the jitter test patterns DIAGNOSTIC defined in IEEE 802.3z 36A. Clear this bit to enable normal transmit ENABLE operation.
Page 468: Coremacfilter Overview
11.9 CoreMACFilter Overview CoreMACFilter provides a solution for SmartFusion2 integrated media access control (MAC) address filtering. The core provides an external filtering mechanism based on unicast (UCAD), multicast (MCAD), and broadcast (BCAD) flags. It implements the desired mechanism to pass the frames to upper layer.
Page 469: Figure 164 Coremacfilter Interaction With Mss Mac And Gmii Ethernet Phy
Ethernet MAC The following figure shows the CoreMACFilter interaction with MSS MAC and GMII Ethernet PHY. Figure 164 • CoreMACFilter Interaction with MSS MAC and GMII Ethernet PHY The following figure shows CoreMACFilter interaction with MSS MAC and SGMII Ethernet PHY. Figure 165 •...
Page 470: Can Controller
FPGA fabric configures the CAN controller through the APB slave. The CAN controller in the SmartFusion2 device supports the concept of mailboxes. It is compliant to the international CAN standard defined in ISO 11898-1. It contains 32 receive buffers. Each buffer has its own message filter and 32 transmit buffers with prioritized arbitration scheme.
Page 471: Transmit Path
ECC error if EDAC is enabled. To initialize the SRAM, you can put the CAN controller into SRAM Test mode, initialize the SRAM, and enable the EDAC. If SECDED is enabled, Microsemi recommends that the CAN controller be put into SRAM Test mode and the RAM initialized with user defined known data before operation so that a future read or an uninitialized address does not trigger a SECDED error.
Page 472: Transmit Procedures
CAN Controller When enabled, CAN ports are configured to connect to SmartFusion2 multi-standard I/Os (MSIOs) by default. CAN signals can also be configured to interface with the FPGA fabric and the MSS general purpose inputs/outputs (GPIOs). The CAN configurator within Libero SoC allows selection from among the fabric, MSIOs, and GPIOs.
Page 473: Receive Procedures
CAN Controller 12.2.2.2 Remove a Message from a Transmit Holding Register A message can be removed from the transmit holding buffer by asserting the TxAbort flag. The content of a particular transmit message buffer can be removed by setting TxAbort to 1 to request message removal.
Page 474 CAN Controller If the receive message handler finds a valid buffer that is empty, then the message is stored and the MsgAv flag of this buffer is set to 1. If the RxIntEbl flag is set, then the rx_msg flag of the interrupt controller is asserted.
Page 475: Interrupt Generation
CAN Controller 12.2.4 Interrupt Generation The interrupt int_n is asserted, if a particular interrupt status bit and the respective enable bit are set. The following figure shows how the system interrupt is generated. Figure 169 • Interrupt Generation INT_STATUS[2] arb_loss INT_ENABLE[2] RxIntEbI[RX_MSG0] INT_STATUS[3]...
Page 476: Can Test Modes
CAN Controller 12.2.5 CAN Test Modes Using the Command Register, page 455 loopback and the listen-only settings, the CAN controller can perform certain test operations as summarized in the following table. Table 436 • Test Modes Loop back Listen-only Comment Normal operation Listen-only mode The CAN controller receives all bus traffic but does not send any information to the bus.
Page 477: Peripheral Signals Assignment Table
CAN Controller 12.3.1 Peripheral Signals Assignment Table The CAN configurator window is divided into two main sections: • The Configuration window displays all the Assignment Options. • The Connectivity Preview window shows a graphical view based on the configurations and selections for the highlighted signal row.
Page 478: Edac Can Configuration
MSS CAN Configurator User Guide. The functional behavior of the CAN instance must be defined at the application level using the SmartFusion2 MSS CAN firmware driver provided by Microsemi. Refer to the CAN Firmware Driver User Guide for more details. 12.3.2...
Page 479: Figure 173 Enabling Edac For The Can From The Secded Configurator
Configuration User Guide for more information on the SECDED configurator options and ports descriptions. Note: The MSS CAN does not support full behavioral simulation models. Refer to SmartFusion2 MSS BFM Simulation User Guide for more information. UG0331 User Guide Revision 15.0...
Page 480: How To Use The Mss Can Controller
CAN Controller 12.4 How to Use the MSS CAN Controller Follow the below steps to use the CAN controller in an application. 12.4.1 Hardware Design Flow Enable the CAN controller in the MSS configurator for the Libero SoC design project, as shown in the following figure.
Page 481: Figure 176 Firmware Driver Enable And Generate
CAN Controller For firmware development, double-click Export Firmware under Handoff Design for Firmware Development in the Libero SoC design flow window to generate the SoftConsole Firmware Project. The SoftConsole folder contains the required mss_driver which provides a set of functions for controlling the MSS CAN peripheral.
Page 482: Use Cases
CAN Controller 12.5 Use Cases 12.5.1 Use Case 1: Automatic Bit Rate Detection It is possible to use the CAN in Listen-only test mode. Refer to the Command Register, page 455 and CAN Test Modes, page 442 for more information on how to enable Listen-only mode. In Listen-only mode, the CAN controller receives all bus traffic but does not send any information to the bus.
Page 483: Table 438 Apb To Sram Address Mapping
CAN Controller exclusive. Thus SRAM test mode can only be enabled when CAN controller is stopped and the CAN controller can only be started when the SRAM test mode is stopped. In the SRAM test mode: • Transparent read and write access to all SRAM memory locations is supported •...
Page 484 CAN Controller Table 438 • APB to SRAM Address Mapping (continued) APB Address SRAM Address Description 0x1C0-0x1CC 0x068-0x06B TxObject26 0x1D0-0x1DC 0x06C-0x06F TxObject27 0x1E0-0x1EC 0x070-0x073 TxObject28 0x1F0-0x1FC 0x074-0x077 TxObject29 0x200-0x20C 0x078-0x07B TxObject30 0x210-0x21C 0x07C-0x07F TxObject31 0x220 0x080 RxObject0:Control Bits 0x224 0x081 RxObject0:Identifier Bits 0x228 0x082...
Page 485: Can Controller Register Map
CAN Controller Table 438 • APB to SRAM Address Mapping (continued) APB Address SRAM Address Description 0x540-0x55C 0x148-0x14F Receive Message Object 25 0x560-0x57C 0x150-0x157 Receive Message Object 26 0x580-0x59C 0x158-0x15F Receive Message Object 27 0x5A0-0x5BC 0x160-0x167 Receive Message Object 28 0x5C0-0x5DC 0x168-0x16F Receive Message Object 29...
Page 486: Can Controller Registers
This section describes the register and bit description of various categories of registers in the CAN controller. In addition, system registers which are applicable to CAN are described in this section. This provides programmers the view for firmware development. Microsemi recommends using drivers provided in the tool set for application development.
Page 487: Can_Command
CAN Controller Table 441 • Summary of CAN Controller Registers (continued) Register Name Address Reset Value Description CAN_COMMAND 0x014 The CAN controller can be used in different operating modes. By disabling transmitting data, it is possible to use the CAN in Listen-only mode, enabling features such as automatic bit rate detection.
Page 488: Configuration Register
CAN Controller Table 441 • Summary of CAN Controller Registers (continued) Register Name Address Reset Value Description INT_STATUS 0x00 0x00 Interrupt status register Writing 1 to a particular bit sets the corresponding interrupt source. The associated enable bit in INT_ENABLE must also be set for this interrupt to be generated.
Page 489: Command Register
CAN Controller Table 442 • CAN_CONFIG (continued) Bit Number Name Description [3:2] CFG_SJW Synchronization Jump Width 1 sjw ≤ tseg1 and sjw ≤ tseg2 SAMPLING_MODE CAN bus bit sampling 0: One sampling point is used in the receiver path. 1: Three sampling points with majority decision are used. EDGE_MODE CAN bus synchronization logic 0: Edge from ‘R’...
Page 490: Transmit Message Control And Command Register
CAN Controller 12.6.5 Transmit Message Control and Command Register Each transmit buffer can be configured through a set of registers. Those registers are broken down into a Control/Command register, Identifier register, Data high register, and Data low register. In the Command/Control register, some bits are setting a control flag and others are setting a command flag.
Page 491: Table 444 Tx_Msg0_Ctrl_Cmd
CAN Controller Table 444 • TX_MSG0_CTRL_CMD (continued) Reset Bit Number Name Value Description TxReq Transmit request; Command flag bit Write: 0: Idle. No message transmit request. 1: Message transmit request The Tx message buffer must not be changed while TxReq is 1. Read: 0: TxReq completed 1: TxReq pending...
Page 492: Table 448 Transmit Message1 To Transmit Message31 Registers Description
CAN Controller The following table lists the address offsets for the TX_MSG1 to TX_MSG31 registers. Table 448 • Transmit Message1 to Transmit Message31 Registers Description Address Reset Register Name Offset Value Description TX_MSG1 Buffer 0x030-0x03C Transmit Message1 buffer registers TX_MSG2 Buffer 0x0040-0x04C Transmit Message2 buffer registers TX_MSG3 Buffer...
Page 493: Transmit Buffer Status Register
CAN Controller 12.6.6 Transmit Buffer Status Register The following table lists the transmit buffer status indicator register TX_BUF_STATUS bits descriptions of the register. For transmit, the status indicates if a message is ready to be sent out. This register consolidate the status of all transmit message buffers. Table 449 •...
Page 494: Receive Message Control And Command Register
CAN Controller 12.6.7 Receive Message Control and Command Register Each receive buffer can be configured through a set of registers. Those registers are broken down into a Command/Control register, Identifier register, Data high register, and Data low register, Acceptance mask register (AMR), Acceptance code register (ACR), AMR data, and ACR data.
Page 495: Table 450 Rx_Msg0_Ctrl_Cmd
CAN Controller Table 450 • RX_MSG0_CTRL_CMD (continued) Bit Number Name Reset Value Description RTRabort RTR abort request; Command bit 0: Idle 1: Requests removal of a pending RTR message reply. The flag is cleared when the message was removed or when the message won arbitration. The TxReq flag is cleared at the same time RTRP RTReply pending;...
Page 496: Rx_Msg0_Data_Low
CAN Controller Table 453 • RX_MSG0_DATA_LOW Bit Number Name Reset Value Description [31:0] RX_MSG0_DATA_LOW [31:24]: CAN data byte 5 The byte mapping can be set using the CAN [23:16]: CAN data byte 6 swap_endian [15:8]: CAN data byte 7 configuration bit. [7:0]: CAN data byte 8 swap_endian = 0, default: [31:24]: CAN data byte 5...
Page 497: Table 450
CAN Controller The rest of the receive message buffers (RX_MSG1 to RX_MSG31) and register bits have the same descriptions as the RX_MSG0 registers shown above. The following table lists the address offset for the RX_MSG1 to RX_MSG31 registers. Table 458 • Receive Message1 to Receive Message 31 and ECR Registers Description Register Name Address Offset Reset Value...
Page 498: Receive Buffer Status Register
CAN Controller 12.6.8 Receive Buffer Status Register The following table lists the receive buffer status indicator register RX_BUF_STATUS and the bits descriptions of the register. For receive buffer, the status indicates if a message arrived. This register consolidates the status of all receive message buffers. Table 459 •...
Page 499: Error Capture Register
CAN Controller 12.6.9 Error Capture Register The CAN controller contains a dedicated error capture register (ECR) that can be used to perform additional CAN bus diagnostics. The ECR supports two different modes. • Free-running mode: In Free-running mode, the ECR displays the field and bit position within the current CAN frame •...
Page 500: 12.6.10 Error Status Register
CAN Controller 12.6.10 Error Status Register Status indicators are provided to report the CAN controller error state, receive error count, and transmit error count. Special flags to report error counter values equal to or in excess of 96 errors are available to indicate heavily disturbed bus situations.
Page 501: Table 462 Int_Enable
CAN Controller Table 462 • INT_ENABLE (continued) Bit Number Name Reset Value Description stuff_err_enbl Bit stuffing error interrupt enable. bit_err_enbl Bit error interrupt enable. ovr_load_enbl Overload message detected interrupt enable. arb_loss_enbl Arbitration loss interrupt enable. Reserved Reserved Int_enbl Global interrupt enable flag. 0: All interrupts are disabled 1: Enabled interrupt sources are available 12.6.11.2 Interrupt Status Register...
Page 502: Table 463 Int_Status
CAN Controller Table 463 • INT_STATUS (continued) Bit Number Name Reset Value Description CRC_ERR CRC error 0: Normal operation 1: Indicates that a CAN CRC error is detected. FORM_ERR Format error 0: Normal operation 1: Indicates that a CAN format error is detected. ACK_ERR Acknowledge error 0: Normal operation...
Page 503: Mmuart Peripherals
Cortex-M3 processor or fabric master to these devices. SmartFusion2 SoC FPGAs contain two identical MMUART peripherals in the microcontroller subsystem (MSS MMUART_0 and MSS MMUART_1), that provide software compatibility with the popular 16550 UART device.
Page 504: Figure 178 Mss Showing Mmuart Peripherals
MMUART Peripherals The following figure shows the MMUART peripherals within the MSS. The MMUART peripherals are interfaced to the AHB bus matrix through APB interfaces (APB_0 and APB_1). Figure 178 • MSS Showing MMUART Peripherals ARM Cortex-M3 MDDR Processor Cache System MSS DDR Controller...
Page 505: Figure 179 Mmuart Block Diagram
MMUART Peripherals Figure 179 • MMUART Block Diagram LIN Header Detect RX BLOCK and Auto Buad Rate Calc Regs MMUART_X_TXD Filter Demod Timeout UART_REG and MMUART_X_RXD MMUART_X_RXD FIFO CTRL MMUART_X_ESWM MMUART_X_RTS 16 Byte RWCONTROL RX_FIFO Interupt MMUART_X_INTR MMUART_X_DTR APB_X Control MMUART MMUART_X_CTS MMUART_X_E_MST_SCK...
Page 506 MMUART Peripherals Table 464 • MMUART I/O Signal Descriptions (continued) Name Type Polarity Description MMUART_X_RI Input Ring indicator. This signal is used in the modem interface. The active Low signal is an input showing when the attached device (modem) senses a ring signal on the telephone line.
Page 507: Initialization
MMUART Peripherals Table 464 • MMUART I/O Signal Descriptions (continued) Name Type Polarity Description MMUART_X_E_MST_SCK Output High Enable master clock. This active High signal is used as a bi-directional enable for the SCK_IN and SCK_OUT signals. If these signals are taken from a single bi-directional pad, E_MST_SCK active High designates Master mode and forces the bi-directional pad as an output, otherwise (in case of...
Page 508: Table 465 Soft Reset Bit Definition For The Mmuart_X
APB_1_CLK on APB bus 1. These clocks are derived from the main MSS clock M3_CLK. Each APB clock can be programmed individually as M3_CLK divided by 1, 2, 4, or 8. Refer to the UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide for more information on clocks.
Page 509: Figure 180 Synchronous And Asynchronous Mode Topologies
Figure 180 • Synchronous and Asynchronous Mode Topologies MMUART UART MMUART_X_RXD MMUART_X_TXD Full-Duplex Async MMUART USART MMUART_X_RXD MMUART_X_SCK_IN CLK_OUT MMUART_X_TXD Full-Duplex Sync-Slave MMUART MMUART_X_SCK_OUT CLK_IN MMUART_X_RXD MMUART_X_TXD Full-Duplex Sync-Master MMUART SMART CARD MMUART_X_RXD S_IN_OUT MMUART_X_TXD MMUART_X_TE SMARTFUSION2 Half-Duplex Sync-Master UG0331 User Guide Revision 15.0...
Page 510: Figure 181 Sample Time Correction With Fractional Baud Rate
MMUART Peripherals 13.2.4.1.1 Fractional Baud Rate Generation–Asynchronous Mode The following figure depicts accumulative baud rate difference error in the Asynchronous mode. It also describes how fractional baud rate generation reduces this error by adding wait times, in the essence of forming a new average baud rate value that is between two given integer baud rate values.
Page 511: Figure 182 Example With Fractional Baud Rate Of 4.5
MMUART Peripherals The following figure describes the timing for a fractional baud rate value of 4.5. Exact averaging is accomplished in one Tbit (bit time) cycle. Figure 182 • Example with Fractional Baud Rate of 4.5 Bit Rate Modulation with Tbit Times BR = 4 = 64 CCC per count Integer Tbit Integer Tbit...
Page 512: Figure 184 Synchronous Input And Adaptation To Internal Baud Clocking
MMUART Peripherals positive-edge or negative-edge; the first edge that detects a start bit aligns the state machine to sample data on the next same edge, as shown in the following figure. In the synchronous Slave mode, the Tx block does not output a clock or baud rate signal as it is assumed that the master provides clocking for any other slave peripherals.
Page 513: Figure 185 Bi-Directional Synchronous Clock Configuration Options
MMUART Peripherals Figure 185 • Bi-Directional Synchronous Clock Configuration Options MMUART_X_SCK_IN MMUART_X_E_MST_SCK MMUART_X_SCK_OUT FABRIC I/F 13.2.4.2 Input Filters MMUART provides input filters for general purposes and suppression of noise and spikes. After resynchronization, the input filters utilize all-zero/all-one unanimous sampling technique based on the system clock with a configurable filter length of N FFs, set by the GLR bits of the Register.
Page 514: Figure 186 Input Filtering Circuit And Timing For Glr=4 (Pulses Less Than 4 Apb Clock Cycles Filtered Out)
MMUART Peripherals Figure 186 • Input Filtering Circuit and Timing for GLR=4 (Pulses Less than 4 APB Clock Cycles Filtered Out) MMUART_X_ SCK_IN_filt Resync GLR=4 Reset MMUART_X_ SCK_IN APB_X_CLK MMUART_X_ SCK_IN MMUART_X_SCK _IN_resync MMUART_X_SCK _IN_filt MMUART_X_SCK _IN_negedge MMUART_X_SCK _IN_posedge 13.2.4.3 LIN Header Detection and Auto Baud Rate Calculation The LIN is a serial communications protocol, which efficiently supports the control of mechatronics nodes in distributed automotive applications.
Page 515: Figure 188 Lin Break Field Width => 11 Tbit Count Interrupt
MMUART Peripherals This serves as a start-of-frame notice to all nodes on the bus. The break field signals the start of a new frame, as shown in the following figure. Figure 188 • LIN Break Field Width => 11 Tbit Count Interrupt MMUART_X Break Field=13 Tbit Length _RXD...
Page 516: Figure 190 Lin Receive Fsm
MMUART Peripherals 13.2.4.3.2 Auto Baud Rate Update FSM The following figure describes the receiving LIN FSM. The FSM simply follows through by parsing the break and sync fields, and then auto-updating the integer and fractional baud rate divisor register before returning to idle.
Page 517: Figure 192 Rx Rzi-To-Nrz Demodulation
MMUART Peripherals After input filtering, the demodulator waits for a positive edge and sets a down counter based on the internal 16 samples per bit time baud rate clock. The output NRZ signal is set Low until the counter reaches 0, then automatically it goes High. When back-to-back pulses occur, the incoming pulse may not be aligned with the internal baud count enable and as such may generate a 1/16 NRZ 1 level.
Page 518: Figure 194 9-Bit Format
MMUART Peripherals 13.2.4.6 Receiver Timeout In the Receiver timeout block (Rx timeout), a counter looks for the post filtered serial input to remain High until the counter expires. Once the timeout occurs, an RTOII interrupt is generated that is cleared when register is rewritten.
Page 519: Figure 195 Single Wire Error Signal Timing When Eerr=1
MMUART Peripherals 13.2.4.10 ISO7816-3 Modes The ISO7816 is an international standard related to electronic identification cards. The ISO7816-3 utilizes a half-duplex, bi-directional bus for data transfers. The MMUART provides the clock to the smart card IC and is therefore considered the master in the system and smart card is the slave. MMUART supports T0/T1 addressing modes.
Page 520: Figure 197 Receive Mode Te Output Enable And Nack Timing When Eerr=1
MMUART Peripherals Figure 197 • Receive Mode TE Output Enable and NACK Timing when EERR=1 2 Stops Bits Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Tbit Rx Data Parity ACK/NACK 10.5 Parity Error Tx (sout) NACK Transmit Enable Output enabled during Rx ACK/NACK window when there is a parity error.
Page 521: Figure 199 Mss Mmuart Configurator
MMUART Peripherals Configure Duplex Mode to Full Duplex and Async/Sync Mode to Asynchronous by using MSS MMUART_0 Configurator as shown in the following figure. Use the Main Connection drop-down list to connect the ports of enabled MMUART_0 instance to an I/O. Click the highlighted Users Guide button to find more information on MMUART configuration details.
Page 522: Figure 201 Mmuart Driver User Guide
Microsemi Firmware Catalog. The following table lists main APIs for MMUART. For complete information on the APIs, refer to the SmartFusion2 MSS UART Driver User Guide as shown in the preceding figure. Table 466 • MSS MMUART APIs...
Page 523: Figure 202 Mmuart Sample Project
For more information on MMUART usage, the sample projects are available and can be generated as shown in the following figure. Figure 202 • MMUART Sample Project Note: The MSS MMUART does not support full behavioral simulation models. Refer to SmartFusion2 MSS BFM Simulation User Guide for more information. 13.3.2 MMUART Use Models 13.3.2.1 Use Model: Communicating with Host PC through MMUART Peripheral...
Page 524: Table 467 Mmuart Register Definitions
MMUART Peripherals 13.3.2.1.1 Software Design Flow This section explains MMUART initialization and data transfers between MMUART peripheral and Host Initialization of MMUART Peripheral Initialize the MMUART instance MMUART_0 by using MSS_UART_init API. Specify the baud rate and line configuration information like bit length, parity, and stop bits to configure the MMUART instance.The same baud rate and line information should be used to configure the Host PC HyperTerminal program.
Page 525: Table 470 Fcr
MMUART Peripherals The following tables provide the register bit descriptions in detail. 13.4.1 Receiver Buffer Register (RBR) Table 468 • RBR Reset Number Name Value Description [7:0] This register holds the receive data bits for MMUART_x. The default value is unknown since the register is loaded with data in the receive FIFO.
Page 526: Baud Rate Divisor Registers
MMUART Peripherals Table 470 • FCR (continued) Default Number Name State Description CLEAR_RX_FIFO Clears all bytes in Rx FIFO and resets counter logic. This shift register is not cleared. 0: Disabled (default) 1: Enabled ENABLE_TX_RX_FIFO It enables both the Tx and Rx FIFOs and is hardwired to 1, which means it is always enabled and cannot be changed.
Page 527: Dlr
MMUART Peripherals The special case of the integer divisor value (DLR+DMR) equal to one is not allowed in fractional mode as maximum error comes when the value is one. Therefore use integer divisor values of two or more when using fractional mode. Baud Rate Registers (DLR, DMR, and DFR) Table 471 •...
Page 528: Table 474 Baud Rates And Divisor Values For The 18.432 Mhz Reference Clock
MMUART Peripherals The following table contains the list of baud rates and corresponding values of DFR and DMR+DLR registers. Table 474 • Baud Rates and Divisor Values for the 18.432 MHz Reference Clock DLR + DMR DFR Fractional Baud Rate Divisor Integer Divisor Divisor in 64...
Page 529: Iir
MMUART Peripherals Table 476 • IEM (continued) ELINBI Enables LIN break interrupt 0: Disabled (default) 1: Enabled EPID_PEI Enables PID parity error interrupt 0: Disabled (default) 1: Enabled ENACKI Enables NACK interrupt 0: Disabled (default) 1: Enabled ERTOI Enables receiver timeout interrupt 0: Disabled (default) 1: Enabled 13.4.7...
Page 530: Iim
MMUART Peripherals Table 478 • Interrupt Identification Bit Values (continued) 0100 Second Received data Receiver data available Reading the receiver buffer available register or the FIFO drops below the trigger level. 1100 Second Character timeout No characters have been read from Reading the receiver buffer indication the Rx FIFO during the last four...
Page 531: Table 481 Mcr
MMUART Peripherals Table 480 • LCR (continued) Reset Number Name Value Description Set break. Enabling this bit sets MMUART_x_TXD to 0. This does not have any effect on transmitter logic. The break is disabled by setting the bit to 0. 0: Disabled (default) 1: Set break Stick parity...
Page 532: Table 482 Lsr
MMUART Peripherals Table 481 • MCR (continued) Reset Number Name Value Description Loop In the Loopback mode, MMUART_x_TXD is set to 1. The MMUART_x_RXD, MMUART_x_DSR, MMUART_x_CTS, MMUART_x_RI, and MMUART_x_DCD inputs are disconnected. The output of the transmitter shift register is looped back into the receiver shift register.
Page 533: Table 483 Msr
MMUART Peripherals Table 482 • LSR (continued) Reset Number Name Value Description Framing error (FE). Indicates that the receive byte did not have a valid stop bit. FE is cleared when Cortex-M3 processor reads the LSR. The MMUART_x tries to resynchronize after a framing error. To do this, it assumes that the framing error was due to the next start bit, so it samples this start bit twice, and then starts receiving the data.
Page 534: Table 484 Sr
MMUART Peripherals Table 483 • MSR (continued) Reset Number Name Value Description DDSR Delta data set ready (DDSR) indicator. Indicates that the DSRn input has changed state since the last time it was read by the Cortex-M3 processor. Whenever bit 0, 1, 2, or 3 is set to 1, a modem status interrupt is generated.
Page 535: Table 486 Mm1
MMUART Peripherals 13.4.15 Multi-Mode Control Register 1 (MM1) Table 486 • MM1 Default Number Name State Description [7:6] Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read- modify-write operation.
Page 536: Table 488 Gfr
MMUART Peripherals Table 487 • MM2 (continued) Reset Number Name Value Description EAFM Enable automatic 9-bit address flag mode (EAFM). It should be noted that for enabling this bit it requires, the LCR should be in an 8-bit and stick parity (SP) bit configured to 0.
Page 537: Table 489 Ttg
MMUART Peripherals 13.4.18 Transmitter Time Guard Register (TTG) Table 489 • TTG Reset Number Name Value Description [7:0] If the transmitter time guard is enabled from the multi-mode control register 0 (MM0), the transmitter time guard value determines the amount of system clock cycles to wait between transmissions.
Page 538: Figure 204 Microcontroller Subsystem Showing Spi Peripherals
The SPI controller is an APB slave in the SmartFusion2 device that provides a serial interface compliant with the Motorola SPI, Texas Instruments synchronous serial, and National Semiconductor MICROWIRE™ formats. In addition, SPI supports interfacing with large SPI flash and EEPROM devices and a hardware-based slave protocol engine.
Page 539: Figure 205 Spi Controller Block Diagram
Serial Peripheral Interface Controller 14.2 Functional Description This section provides the detailed description of SPI peripherals. 14.2.1 Architecture Overview The SPI controller supports master and slave modes of an operation. • In master mode, the SPI generates SPI_X_CLK, selects a slave using SPI_X_SS[x], transmits the data on SPI_X_DO, and receives the data on SPI_X_DI.
Page 540: Table 492 Spi Interface Signals
SPI ready to transmit. Used only by MSS PDMA engine SPI_X_RXAVAIL Output High SPI received data. Used only by MSS PDMA engine. 14.2.2.2 Data Transfer Protocol Details The SmartFusion2 SPI controller supports the following data transfer protocols: • Motorola SPI Protocol • National Semiconductor MICROWIRE Protocol •...
Page 541: Table 493 Data Transfer Modes
Serial Peripheral Interface Controller 14.2.2.3 Motorola SPI Protocol The Motorola SPI is a full duplex, four-wire synchronous transfer protocol which supports programmable clock polarity (SPO) and clock phase (SPH). The state of SPO and SPH control bits decides the data transfer modes as detailed in the following table.
Page 542: Figure 206 Motorola Spi Mode 0
Serial Peripheral Interface Controller Table 494 • Summary of Master SPI Modes (continued) Clock in Sample Shift Select in Mode SPS SPO SPH Idle Edge Edge Idle Select Between Frames National Rising Falling High Normal operation Semiconductor SPI_X_CLK only generated with Microwire select and data bits.
Page 543: Figure 208 Motorola Spi Mode 1
Serial Peripheral Interface Controller Single Frame Transfer – Mode 1: SPO = 0, SPH = 1 Figure 208 • Motorola SPI Mode 1 SPI_CLK SPI_SS[x] SPI_DI 4 to 32 Bits SPI_DOE_N SPI_DO Single Frame Transfer – Mode 2: SPO = 1, SPH = 0 Figure 209 •...
Page 544: Table 495 Behavior Of The Output Enable Signal
Serial Peripheral Interface Controller falling edge at the end of the transmission. This means that SPI_X_DOE_N must be held High for at least one half SPI_X_CLK after the last falling edge to satisfy the hold time requirement. Table 495 • Behavior of the Output Enable Signal Mode Master Slave...
Page 545: Figure 211 Write Operation Timing
Serial Peripheral Interface Controller The following figure shows the write operation timing for Atmel 25010/020/040 devices. The SPI controller selects the devices using the slave select signal. The data frame size is set to 24 bits. The SPI is configured with SPO = 0, SPH = 0. The first byte is the instruction. Bit 5 of the instruction is part of the address (the 9th bit as required by the Atmel part).
Page 546: Figure 213 Page Program Timing
In slave operation, it is possible for TXRXDFCOUNT to miscount actual transmitted and received frames if the transmit FIFO under-run condition occurs. If this is likely in an application, Microsemi recommends that TXRXDFCOUNT not be used and that it be disabled. Instead use the CMDINT and SSEND bits in the raw interrupt status (RIS) register to monitor operation, or simply count how many frames it is received.
Page 547: Figure 214 National Semiconductor Microwave Single Frame Transfer
Serial Peripheral Interface Controller 14.2.2.4 National Semiconductor MICROWIRE Protocol The National Semiconductor MICROWIRE serial interface is a half-duplex protocol using a master/slave message passing technique. Each serial transmission begins with an 8-bit control word, during which time no incoming data is received. After the control word is sent, the external slave decodes it, and after waiting one serial clock cycle from the end of the control word, responds with the required data, which may be 4 to 16 bits in length.
Page 548: Figure 216 Ti Synchronous Serial Single Frame Transfer
SPI master to the SPI slave. The SPE controller logically sits between the SPI transmit/receive logic and the FIFOs. The SPE controller removes the command bytes and inserts status bytes from the data stream. Only one command byte is defined by Microsemi UG0331 User Guide Revision 15.0...
Page 549: Figure 218 Spe Command/Data Format
Serial Peripheral Interface Controller (POLL command). All other command bytes are user defined. To use the SPE, the BIGFIFO, AUTOSTATUS, AUTOPOLL, FRAMEURUN, and bits should be set (refer to the SPI CONTROL register for bit definitions). The descriptions below assume that the frame size (TXRXDF_SIZE[TXRXDFS] field) is set to 8 bits, although other frame size settings are acceptable (up to 32 bits).
Page 550: Initialization
Serial Peripheral Interface Controller 14.2.2.6.3 Hardware Status Frame A hardware status frame is automatically sent back by the SPE in response to every command. It provides status information back to the master. The byte contains the contents of the HWSTATUS register.
Page 551: Table 496 Soft Reset Bit Definitions For Spi Peripheral
1. These clocks are derived from the main MSS clock, M3_CLK. Each APB clock can be programmed individually as M3_CLK is divided by 1, 2, 4, or 8. Refer to the UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide for more information.
Page 552 Serial Peripheral Interface Controller For large data transfers, the full depth of transmit FIFO can be used by setting the number of data frames (more than one) in a burst (maximum is 64 k frames). When the interrupts are enabled, the TXDONE bit of the register is asserted after all the data frames in the burst are sent.
Page 553 Serial Peripheral Interface Controller 14.2.4.3 Interrupts Interrupts can be set up to signal the completion of a data frame transmission or reception. There is one interrupt signal from each SPI peripheral. The SPI_0_INT signal is generated by SPI_0 and is mapped to INTISR [2] in the Cortex-M3 processor nested vectored interrupt controller (NVIC).
Page 554: Figure 219 Enable Spi
Serial Peripheral Interface Controller 14.3.1 Design Flow The following steps are used to enable the SPI in the application by using Libero SoC. Enable SPI_0 and/or SPI_1 instance by using the MSS configurator in the application, as shown in the following figure. Figure 219 •...
Page 555: Figure 220 Mss Spi Configurator - Connection Type Io
Serial Peripheral Interface Controller Configure the number of Slaves to 1 and the ports of enabled SPI_0 instance to an IO or Fabric by using MSS SPI_0 Configurator as shown in the following figures. Click the highlighted Users Guide button to find more information on SPI configuration details. Figure 220 •...
Page 556: Figure 221 Mss Spi Configurator - Connection Type Fabric
Serial Peripheral Interface Controller Figure 221 • MSS SPI Configurator - Connection Type Fabric The SPI_0 interface signals in the MSS component are shown in the following figure. Figure 222 • SPI Interface Signals - Connection Type IO UG0331 User Guide Revision 15.0...
Page 557: Figure 223 Spi Interface Signals - Connection Type Fabric
SoC design flow window to generate the SoftConsole Firmware Project. The SoftConsole folder contains the mss_spi firmware driver. The firmware driver, mss_spi ( mss_spi.c mss_spi.h which provides a set of functions for controlling the MSS SPIs can also be downloaded from the Microsemi Firmware Catalog. UG0331 User Guide Revision 15.0...
Page 558: Figure 225 Spi Sample Project
For more information on SPI usage, the sample projects are available and can be generated, as shown in the following figure. Figure 225 • SPI Sample Project Note: The MSS SPI does not support full behavioral simulation models. Refer to SmartFusion2 MSS BFM Simulation User Guide for more information. UG0331 User Guide Revision 15.0...
Page 559: Figure 226 Interfacing External Spi Flash To Mss Spi_0-Block Diagram
The external SPI flash can be interfaced to either the MSS SPI_0 or SPI_1 peripherals of the SmartFusion2 MSS. In this example, the external SPI flash is interfaced to MSS SPI_0. The MSS SPI_0 is configured as a master with the slave select line connected to the chip select of the external SPI Flash.
Page 560: Figure 227 Interfacing External Spi Slave Device Using Mss Spi Routing Through Fabric Block Diagram
14.3.2.2 Use Model 2: Interfacing Any SPI Slave Device Using MSS SPI Routing Through Fabric The external SPI slave devices like serial display device can be interfaced using SmartFusion2 MSS SPI routing through fabric ports. The fabric ports can be brought out to the GPIO header to interface the SPI slave device with SmartFusion2 device.
Page 561: Table 498 Sysreg Control Registers
Serial Peripheral Interface Controller Refer to the In-Application Programming chapter of UG0451: IGLOO2 and SmartFusion2 Programming User Guide for more information on usage of SPI_0 peripheral in IAP. 14.4 SPI Register Map This section provides SPI registers along with the address offset, functionality, and bit definitions.
Page 562: Spi Register Details
Serial Peripheral Interface Controller Table 499 • SPI Register Summary (continued) Register Name Address Offset R/W Reset Value Description CTRL1 0x44 0x01 Aliased CONTROL register bits 15:8. This register allows byte operations from an 8-bit processor in the fabric. It is not intended for access from internal MSS masters.
Page 563: Table 501 Txrxdf_Size
Serial Peripheral Interface Controller Table 500 • CONTROL (continued) Reset Number Name Value Description INTTXTURUN Interrupt on transmit the under-run 0: Interrupt disabled 1: Interrupt enabled INTRXOVRFLO R/W Interrupt on receive overflow 0: Interrupt disable 1: Interrupt enabled INTTXDATA Interrupt on transmit data 0: Interrupt disabled 1: Interrupt enabled INTRXDATA...
Page 564: Table 502 Status
Serial Peripheral Interface Controller 14.4.3.3 SPI Status Register (STATUS) The following table provides the SPI Status register details. This register indicates the state of SPI such as Tx/Rx FIFO, Tx under-run, and Rx overflow. Table 502 • Status Reset Number Name Value Description [31:15]...
Page 565: Table 503 Int_Clear
Serial Peripheral Interface Controller 14.4.3.4 SPI Interrupt Clear Register (INT_CLEAR) The following table describes the Interrupt Clear register. A read to this register has no effect. It returns all zeroes. Table 503 • INT_CLEAR Reset Number Name Value Description [31:6] Reserved Software should not rely on the value of a reserved bit.
Page 566: Table 506 Clk_Gen
Serial Peripheral Interface Controller Table 506 • CLK_GEN (continued) [7:0] CLK_GEN Specifies the methodology used to calculate the SPICLK divider. CLK_MODE = 0: CLK_GEN + 1 SPICLK = 1 / (2 ) where CLK_GEN = 0 to 15. CLK_MODE = 1: SPICLK = 1 / (2 ×...
Page 567: Slave_Select
Serial Peripheral Interface Controller Table 508 • SLAVE_SELECT (continued) SLAVE SELECT Specifies the slave selected. Writing one to a bit position selects the corresponding slave. SLAVESELECT[7:1] are available at the FPGA fabric interface, while SLAVESELECT[0] is available at the SPI_X_SS[0] pin. The slave select output polarity is active low.
Page 568: Table 511 Control2
Serial Peripheral Interface Controller Table 510 • RIS Reset Number Name Value Description CMDINT Indicates that the number of frames set by the CMDSIZE register has been received as a single packet of frames (SPI_X_SS[x] held active). TXCHUNDR RAW interrupt status. Reading this returns raw interrupt status. Raw status of transmit channel under-run RXCHOVRF Raw status of receive channel overflow...
Page 569: Table 512 Command
Serial Peripheral Interface Controller 14.4.3.12 SPI Command Register The following table describes the Command register.. Table 512 • COMMAND Reset Number Name Value Description [31:7] Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 570: Cmdsize
Serial Peripheral Interface Controller 14.4.3.13 SPI Packet Size Register The following table provides the details of the Packet Size registers that are used to set the SPI CMD/data frame size. Table 513 • PKTSIZE Reset Number Name Value Description [31:8] Reserved Software should not rely on the value of a reserved bit.
Page 571: Table 516 Stat8
Serial Peripheral Interface Controller 14.4.3.16 SPI Status 8 Register The following table describes the SPI status 8 (STAT8) register. This register allows the important status bits to be read as a single 8-bit value. This reduces the overhead of checking the Status register bits when an 8-bit processor is being used.
Page 572: Features
Inter-Integrated Circuit Peripherals Philips inter-integrated circuit (I2C) is a two wire serial bus interface that provides data transfer between many devices. SmartFusion2 SoC FPGAs contain two identical I C peripherals in the microcontroller subsystem (MSS I2C_0 and MSS I2C_1), that provide a mechanism for serial communication between the SmartFusion2 device and external I C compliant devices.
Page 573: Figure 229 I 2 C Block Diagram
Inter-Integrated Circuit Peripherals 15.2 Functional Description This section provides a detailed description of the I C peripherals. 15.2.1 Architecture Overview The I C peripherals consist mainly of the following components (shown in the following figure). • Input Glitch Filter • Arbitration and Synchronization Logic •...
Page 574: Figure 230 8-Bit Data Transfer Cycle
Inter-Integrated Circuit Peripherals 15.2.1.3 Address Comparator When a master transmits a slave address on the bus, the address comparator checks the 7-bit slave address with its own slave address. If the transmitted slave address does not match, the address comparator compares the first received byte with the general call address (0x00). If the address matches, the Status register is updated.
Page 575: Initialization
1. These clocks are derived from the main MSS clock M3_CLK. Each APB clock can be programmed individually as M3_CLK divided by 1, 2, 4 or 8. Refer to the UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide for more information.
Page 576: Details Of Operation
Inter-Integrated Circuit Peripherals 15.2.4 Details of Operation The I C logic operates in the following modes: • Master Mode • Master-Transmitter mode: The master transmits serial data on SDA and drives the SCL. • Master-Receiver mode: The master receives serial data on SDA and drives the SCL. •...
Page 577: Figure 231 Pmbus And Smbus Devices Interface
Inter-Integrated Circuit Peripherals For an SMBus application, it is advised to choose a PCLK so that the SCL transfers data at near the maximum frequency to ensure that other potential clock-stretching devices on the bus do not slow the clock frequency to below the minimum allowed SMBus clock frequency. Figure 231 •...
Page 578: Design Flow
Inter-Integrated Circuit Peripherals 15.3 How to Use I This section describes how to use I C in an application. 15.3.1 Design Flow The following steps are used to enable the I C in the application by using Libero SoC. Enable I2C_0 and/or I2C_1 instance by using the MSS configurator in the application, as shown in the following figure.
Page 579: Figure 233 Mss I2C Configurator
Inter-Integrated Circuit Peripherals Configure the ports of enabled I2C_0 instance to an IO by using MSS I2C_0 Configurator as shown in the following figure. Click the highlighted Users Guide button to find more information on I configuration details. Figure 233 • MSS I2C Configurator The I2C_0 interface signals in the MSS component are shown in the following figure.
Page 580: Figure 235 I 2 C Driver User's Guide
The firmware driver, mss_i2c (mss_i2c.c and mss_i2c.h) which provides a set of functions for controlling the MSS I2Cs can also be downloaded from the Microsemi firmware catalog. The following figure lists the main APIs for I C. For more information on the APIs, refer to the SmartFusion2_MSS_I2C_Driver_UG, as shown in the preceding figure.
Page 581: Figure 236 I 2 C Sample Project
C usage, the sample projects are available and can be generated, as shown in the following figure. Figure 236 • I C Sample Project Note: The MSS I2C does not support full behavioral simulation models. Refer to SmartFusion2 MSS BFM Simulation User Guide for more information. UG0331 User Guide Revision 15.0...
Page 582: Figure 237 Interfacing External Eeprom To Mss I2C_0 - Block Diagram
The following sections describe I C use models. 15.3.2.1 Use Model 1: Interfacing External EEPROM The following figure shows the interfacing of the external EEPROM to I2C_0 of the SmartFusion2 MSS. Figure 237 • Interfacing External EEPROM to MSS I2C_0 - Block Diagram SmartFusion2...
Page 583 Inter-Integrated Circuit Peripherals 15.3.2.2 Use Model 2: Configuring I C as a Slave The I C peripheral can be configured to Slave mode. In Slave mode, the I2C_0 responds to the commands received by the I C master device. Refer to the Design Flow, page 544 to configure I2C_0 in the application.
Page 584: Table 520 I 2 C Register Map
Inter-Integrated Circuit Peripherals Figure 238 • I C Loopback Block Diagram SCL 0 SCL OUT SCL 1 SCL IN MSS_I2CLOOPBACK bit I2C_0 SDA 0 SDA OUT SDA 1 SDA IN MSS_I2CLOOPBACK bit SCL 0 SCL OUT SCL 1 SCL IN I2C_1 MSS_I2CLOOPBACK bit SDA 0...
Page 585: Table 521 Control Register (Ctrl)
Inter-Integrated Circuit Peripherals 15.4.1 Control Register The following table describes the Control register used for configuring the I C peripherals. Table 521 • Control Register (CTRL) Reset Number Name R/W Value Description Clock rate bit 2; refer to bit 0. ENS1 R/W Enable bit.
Page 586: Table 524 Status Register - Master-Transmitter Mode
Inter-Integrated Circuit Peripherals 15.4.2 Status Register The following table describes the Status register of the I C peripherals. Table 523 • Status Register (STATUS) Reset Number Name Value Description Status register 0XF8 The Status register is read-only. The status values depend on the mode of operation.
Page 587: Table 525 Status Register - Master-Receiver Mode
Inter-Integrated Circuit Peripherals Table 524 • Status Register – Master-Transmitter Mode (continued) Control Register Bits Status Data Register Code Status Action STA STO SI Next Action Taken by Core 0x30 Data byte in Data Data byte Data byte is transmitted; ACK is Register is received.
Page 588: Table 526 Status Register - Slave-Receiver Mode
Inter-Integrated Circuit Peripherals Table 525 • STATUS Register – Master-Receiver Mode (continued) Control Register Bits Status Data Register Code Status Action STA STO SI Next Action Taken by Core 0x50 Data byte has been Read data byte Data byte is received; not ACK(NACK) is received;...
Page 589 Inter-Integrated Circuit Peripherals Table 526 • STATUS Register – Slave-Receiver Mode (continued) Control Register Bits Status Data Register Code Status Action STA STO SI Next Action Taken by Core 0x88 Previously addressed with Read data byte 0 Switched to not-addressed SLV own SLA;...
Page 590: Table 527 Status Register – Slave-Transmitter Mode
Inter-Integrated Circuit Peripherals Table 526 • STATUS Register – Slave-Receiver Mode (continued) Control Register Bits Status Data Register Code Status Action STA STO SI Next Action Taken by Core 0xA0 A STOP condition or No action Switched to not-addressed SLV repeated START condition mode;...
Page 591 Inter-Integrated Circuit Peripherals Table 527 • STATUS Register – Slave-Transmitter Mode (continued) Control Register Bits Status Data Register Code Status Action STA STO SI Next Action Taken by Core 0xC0 Data byte is No action Switched to not-addressed SLV mode; no transmitted;...
Page 592: Data Register
Inter-Integrated Circuit Peripherals 15.4.2.5 Status Register: Miscellaneous States Table 528 • STATUS Register – Miscellaneous States Control Register Bits Status Data Register Code Status Action STA STO SI Next Action Taken by Core 0x38 Arbitration lost No action Bus is released A Start condition is transmitted when the bus gets free.
Page 593: Slave0 Address Register
Inter-Integrated Circuit Peripherals 15.4.4 Slave0 Address Register The I C has dual slave address (Slave0/Slave1) decoding capability. The Slave0 address register is a read/write directly accessible register. The details of this register are provided in the following table. Table 530 • Slave0 Address Register (Slave0 ADR) Numbe Reset Name...
Page 594: Frequency Register
Inter-Integrated Circuit Peripherals Table 531 • SMBus Register (SMBUS) (continued) Reset Number Name Value Description SMBSUS_NI status Status of SMBSUS_NI signal. SMBUS_NI is a Suspend mode signal from fabric to MSS. It is used if the core is slave/device. Upon resuming, the SMBSUS_NI returns High. The system then returns all devices to their operational state.
Page 595: Glitch Register
Inter-Integrated Circuit Peripherals 15.4.7 Glitch Register The Glitch register (GLITCHREG) gives the size of the glitch (in terms of APB interface clock cycles) to filter the glitches on data and clock lines. Table 533 • Glitch Register (GLITCHREG) Reset Number Name Value Description GlitchReg_Num R/W...
Page 596: Figure 239 Gpio Connected On Apb Slave In Mss
MSS GPIO MSS GPIO The microcontroller subsystem (MSS) general purpose input/output (GPIO) block is an advanced peripheral bus (APB) slave that provides access to 32 GPIOs. As shown in the following figure, MSS masters and fabric masters can access the MSS GPIO block through the advanced high-performance bus (AHB) matrix.
Page 597: Figure 240 Gpio, Iomux, And Msio
MSS GPIO 16.2 MSS GPIO Functional Description The following figure shows the internal architecture of the MSS GPIO block. GPIOs and MSS peripherals, such as MMUART, SPI, and I2C, can be routed to MSIO pads or to the field programmable gate array (FPGA) fabric through I/O mutliplexers (MUXes), as shown in the figure.
Page 598: Figure 241 Mss Gpio Block Diagram
MSS GPIO Figure 241 • MSS GPIO Block Diagram MSS GPIO INT[i] Cortex-M3 Microcontroller GPIO_IN Reg Sync Interrupt Interrupt INT[i] Generate Logic (GPIO_IRQ[i]) EN_IN_i (Input Enable) GPIO_i_IN GPIO_OUT Reg GPIO_i_OUT GPIO_i_OE MSIO TYPES_INT_i (Interrupt Types) EN_OUT_i (Output Enable) UG0331 User Guide Revision 15.0...
Page 599: Figure 242 Gpio Configuration Register (Gpio_X_Cfg)
MSS GPIO 16.2.1 MSS GPIO Configuration Registers (GPIO_X_CFG) In the MSS GPIO block, each GPIO has a 32-bit configuration register. The configuration register allows selection of the GPIO in Input, Output, or Bi-directional mode. A GPIO can also be used as an interrupt when it is configured in Bi-directional mode.
Page 600: Mss Gpio Reset Functionality
MSS GPIO Table 536 • MSS GPIO Interrupts Cortex-M3 Processor Interrupt Signal Source Description INTISR[50] GPIO_INT[0] GPIO_0 Interrupt from GPIO_0 INTISR[51] GPIO_INT[1] GPIO_1 Interrupt from GPIO_1 INTISR[52] GPIO_INT[2] GPIO_2 Interrupt from GPIO_2 INTISR[53] GPIO_INT[3] GPIO_3 Interrupt from GPIO_3 INTISR[54] GPIO_INT[4] GPIO_4 Interrupt from GPIO_4 INTISR[55]...
Page 601 MSS GPIO Following are the two reset resources of the MSS GPIO block: • Hard reset: • The MSS_GPIO_RESET_N is a reset signal generated from the FPGA fabric • Power-on reset is a device reset signal • Soft reset from the SYSREG block: There are two soft reset signals generated from the SYSREG block: one for the output registers and another for the input and interrupt registers.
Page 602: Figure 243 Enable Gpio In Mss Configurator
MSS GPIO 16.3 MSS GPIO Usage 16.3.1 Configuring MSS GPIO Using Libero SoC This sub-section describes MSS GPIO configuration in Libero SoC and shows different options available for configuring GPIO. The MSS GPIO is disabled by default in MSS configurator when the Libero SoC project is created.
Page 603: Figure 244 Mss Gpio Configurator
MSS GPIO Step 2 Double-click GPIO or right-click, GPIO and select the configure option to program the GPIOs. 16.3.1.1 GPIO Configurator Options The following fields are shown in the GPIO configurator (see the following figure): • Set/Reset definition: Used to initialize the GPIOs •...
Page 604: Figure 245 Configuring Gpio Byte-Wise Reset
MSS GPIO 16.3.1.2 Initializing the MSS GPIO The highlighted section in the following figure shows the byte-wise initialization of GPIOs in Libero SoC. Figure 245 • Configuring GPIO Byte-Wise Reset 16.3.1.3 Configuring MSS GPIOs as Input, Output, Tristate, and Bi-directional There are four modes of MSS GPIO, which can be configured using Libero SoC: •...
Page 605: Figure 246 Configuring Gpios As Input, Output, Tristate, Or Bi-Directional
MSS GPIO To configure a GPIO to simultaneously connect with fabric, select the Advanced Options and Fabric check boxes in Libero SoC, as shown in the following figure. Figure 246 • Configuring GPIOs as Input, Output, Tristate, or Bi-directional Connectivity Preview GPIOs have access to IO_A or IO_B MSIOs.
Page 606: Figure 247 Connectivity Preview
MSS GPIO The following figure shows a graphical view of the current connections for the highlighted GPIO signal. Figure 247 • Connectivity Preview Step 3 The configured GPIO signals are shown in the following figure. Figure 248 • GPIO Signals Step 4 To generate a component, click the Generate Component shortcut in MSS configurator or select SmartDesign >...
Page 607: Mss Gpio Use Models
SoftConsole Firmware Project. The SoftConsole folder contains the mss_gpio firmware driver. The firmware driver mss_gpio (mss_gpio.h and mss_gpio.c), which provides a set of functions for controlling the MSS GPIOs, can be downloaded from the Microsemi Firmware Catalog.
Page 608: Figure 249 Gpio Loopback Diagram
MSS GPIO 16.3.2.2 Use Model 2: GPIO Loopback Mode GPIO Loopback mode (shown in the following figure) is looping back all the 32 GPIOs by controlling the MSS_LOOPBACK bit of LOOPBACK_CR System register. Enable GPIOs using MSS configurator in Libero SoC. Initialize all 32 GPIOs to a predefined state using the MSS_GPIO_init API in SoftConsole or Libero SoC.
Page 609 MSS GPIO Table 538 • MSS GPIO Register Map (continued) Address Register Reset Register Name Offset Type Value Description GPIO_13_CFG 0x34 Configuration register for GPIO 13 GPIO_14_CFG 0x38 Configuration register for GPIO 14 GPIO_15_CFG 0x3C Configuration register for GPIO 15 GPIO_16_CFG 0x40 Configuration register for GPIO 16...
Page 610: Sysreg Block Registers
MSS GPIO 16.4.1 SYSREG Block Registers 16.4.1.1 Register Map The following table lists all the GPIO registers in the SYSREG block. The SYSREG block is located at address 0x40038000 in the Cortex-M3 processor address space. Table 539 • GPIO SYREG Registers Flash Address Register...
Page 611: Mss Gpio Definitions
MSS GPIO 16.4.3 MSS GPIO Definitions Table 541 • MSS_GPIO_DEF Reset Number Name Value Description [31:4] Reserved Reserved MSS_GPIO_31_24_DEF Used to initialize GPIO bank [31:24] to 0 or 1 after reset. MSS_GPIO_23_16_DEF Used to initialize GPIO bank [23:16] to 0 or 1 after reset. MSS_GPIO_15_8_DEF Used to initialize GPIO bank [15:8] to 0 or 1 after reset.
Page 612: Gpio System Reset Control Register
MSS GPIO 16.4.6 GPIO System Reset Control Register Table 544 • GPIO_SYSRESET_SEL_CR Reset Number Name Value Description [31:4] Reserved Reserved MSS_GPIO_31_24_SYSRESET_SEL 0 0: The GPIO[31:24] is reset by either power-on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric. 1: The GPIO[31:24] is reset by the soft reset signal MSS_GPIO_31_24_SOFT_RESET.
Page 613: Table 546 Iomux Cell 11
MSS GPIO 16.4.7.1 IOMUX CELL 11 I/O pad name: I2C1_SDA_USBA_DATA3_MGPIO0A Table 546 • IOMUX CELL 11 IOMUXCELL Interface I/O Pad Ports I2C_1 USB Controller GPIO[0] FPGA Fabric SDA_1_IN USBA_DATAI[3] GPIOA_IN[0] IN_A F2H_GPIN[11] DATAO[3] GPIO_OUT[0] IN_B F2H_SCP[11] ~SDA_1_OUT ~NDATAOE GPIO_OE[0] OUT_A H2F_A[11] OUT_B H2F_B[11]...
Page 614: Table 549 Iomux Cell 14
MSS GPIO 16.4.7.4 IOMUX CELL 14 I/O pad name: CAN_RXBUS_USBA_DATA1_MGPIO3A Table 549 • IOMUX CELL 14 IOMUXCELL Interface I/O Pad Ports USB Controller GPIO[3] FPGA Fabric CAN_RX_BUS USBA_DATAI[1] GPIOA_IN[3] IN_A F2H_GPIN[14] DATAO[1] GPIO_OUT[3] IN_B F2H_SCP[14] ~NDATAOE GPIO_OE[3] OUT_A H2F_A[14] OUT_B H2F_B[14] 16.4.7.5 IOMUX CELL 15 I/O pad name: CAN_ TX_EBL_USBA_DATA2_MGPIO4A...
Page 615: Table 552 Iomux Cell 17
MSS GPIO 16.4.7.7 IOMUX CELL 17 I/O pad name: SPI0_SDO_USBA_STP_MGPIO6A Table 552 • IOMUX CELL 17 IOMUXCELL Interface I/O Pad Ports SPI_0 USB Controller GPIO[6] FPGA Fabric GPIOA_IN[6] IN_A F2H_GPIN[17] SPISDO_0_OUT GPIO_OUT[6] IN_B F2H_SCP[17] SPIOEN_0 GPIO_OE[6] OUT_A H2F_A[17] OUT_B H2F_B[17] 16.4.7.8 IOMUX CELL 18 I/O pad name: SPI0_SS0_USBA_NXT_MGPIO7A Table 553 •...
Page 616: Table 555 Iomux Cell 20
MSS GPIO 16.4.7.10 IOMUX CELL 20 I/O pad name: SPI0_SS2_USBA_DATA6_MGPIO9A Table 555 • IOMUX CELL 20 IOMUXCELL Interface I/O Pad Ports SPI_0 USB Controller GPIO[9] FPGA Fabric USBA_DATAI[6] GPIOA_IN[9] IN_A F2H_GPIN[20] SPISS_0_OUT[2] DATAO[6] GPIO_OUT[9] IN_B F2H_SCP[20] SPI_0_MASTER ~NDATAOE GPIO_OE[9] OUT_A H2F_A[20] OUT_B H2F_B[20]...
Page 617: Table 559 Iomux Cell 24
MSS GPIO 16.4.7.14 IO MUX CELL 24 I/O pad name: SPI0_SS6_MGPIO21A Table 559 • IOMUX CELL 24 IOMUXCELL Interface I/O Pad Ports SPI_0 USB Controller GPIO[21] FPGA Fabric GPIOA_IN[21] IN_A SPISS_0_OUT[6] GPIO_OUT[21] IN_B SPI_0_MASTER GPIO_OE[21] OUT_A H2F_A[24] OUT_B 16.4.7.15 IOMUX CELL 25 I/O pad name: SPI0_SS7_MGPIO22A Table 560 •...
Page 618: Table 562 Iomux Cell 27
MSS GPIO 16.4.7.17 IOMUX CELL 27 I/O pad name: SPI1_SDO_MGPIO12A Table 562 • IOMUX CELL 27 IOMUXCELL Interface I/O Pad Ports SPI_0 USB Controller GPIO[12] FPGA Fabric GPIOA_IN[12] IN_A F2H_GPIN[27] SPISDO_1_OUT GPIO_OUT[12] IN_B F2H_SCP[27] SPIOEN_0 GPIO_OE[12] OUT_A H2F_A[27] OUT_B H2F_B[27] 16.4.7.18 IOMUX CELL 28 I/O pad name: SPI1_SS0_MGPIO13A Table 563 •...
Page 619: Table 566 Iomux Cell 31
MSS GPIO 16.4.7.21 IOMUX CELL 31 I/O pad name: SPI1_SS3_MGPIO16A Table 566 • IOMUX CELL 31 IOMUXCELL Interface I/O Pad Ports SPI_1 USB Controller GPIO[16] FPGA Fabric GPIOA_IN[16] IN_A F2H_GPIN[31] SPISS_1_OUT[3] GPIO_OUT[16] IN_B F2H_SCP[31] SPI_1_MASTER GPIO_OE[16] OUT_A H2F_A[31] OUT_B H2F_B[31] 16.4.7.22 IOMUX CELL 32 I/O pad name: SPI1_SS4_MGPIO17A Table 567 •...
Page 620: Table 570 Iomux Cell 35
MSS GPIO 16.4.7.25 IOMUX CELL 35 I/O pad name: SPI1_SS7_MGPIO24A Table 570 • IOMUX CELL 35 IOMUXCELL Interface I/O Pad Ports SPI_1 USB Controller GPIO[24] FPGA Fabric GPIOA_IN[24] IN_A SPISS_1_OUT[7] GPIO_OUT[24] IN_B SPI_1_MASTER GPIO_OE[24] OUT_A H2F_A[35] OUT_B 16.4.7.26 IOMUX CELL 36 I/O pad name: MMUART1_RTS_MGPIO11B Table 571 •...
Page 621: Table 574 Iomux Cell 39
MSS GPIO 16.4.7.29 IOMUX CELL 39 I/O pad name: MMUART1_DSR_MGPIO14B Table 574 • IOMUX CELL 39 IOMUXCELL Interface I/O Pad Ports MMUART_1 USB Controller GPIO[14] FPGA Fabric DSR_1_IN GPIOB_IN[14] IN_A GPIO_OUT[14] IN_B GPIO_OE[14] OUT_A H2F_A[39] OUT_B 16.4.7.30 IOMUX CELL 40 I/O pad name: MMUART1_RI_MGPIO15B Table 575 •...
Page 622: Table 578 Iomux Cell 43
MSS GPIO 16.4.7.33 IOMUX CELL 43 I/O pad name: MMUART1_SCK_USBC_DATA4__MGPIO25B Table 578 • IOMUX CELL 43 IOMUXCELL Interface I/O Pad Ports MMUART_1 USB Controller GPIO[25] FPGA Fabric MMUART1_SCK_IN USBC_DATAI[4] GPIOB_IN[25] IN_A F2H_GPIN[43] MMUART1_BAUDOUTN DATAO[4] GPIO_OUT[25] IN_B F2H_SCP[43] MMUART1_E_MST_SCK ~NDATAOE GPIO_OE[25] OUT_A H2F_A[43] OUT_B...
Page 623: Table 582 Iomux Cell 47
MSS GPIO 16.4.7.37 IOMUX CELL 47 I/O pad name: MMUART0_CTS_USBC_DATA7__MGPIO19B Table 582 • IOMUX CELL 47 IOMUXCELL Interface I/O Pad Ports MMUART_0 USB Controller GPIO[19] FPGA Fabric CTS_0_IN USBC_DATAI[7] GPIOB_IN[19] IN_A F2H_GPIN[47] DATAO[7] GPIO_OUT[19] IN_B F2H_SCP[47] ~NDATAOE GPIO_OE[19] OUT_A H2F_A[47] OUT_B H2F_B[47] 16.4.7.38 IOMUX CELL 48...
Page 624: Table 586 Iomux Cell 51
MSS GPIO 16.4.7.41 IOMUX CELL 51 I/O pad name: MMUART0_TXD_ USBC_DIR_MGPIO27B Table 586 • IOMUX CELL 51 IOMUXCELL Interface I/O Pad Ports MMUART_0 USB Controller GPIO[27] FPGA Fabric TXD_0_IN USBC_DIR GPIOB_IN[27] IN_A F2H_GPIN[51] TXD_0_OUT GPIO_OUT[27] IN_B F2H_SCP[51] MMUART0_TE GPIO_OE[27] OUT_A H2F_A[51] OUT_B H2F_B[51]...
Page 625: Table 590 Iomux Cell 55
MSS GPIO 16.4.7.45 IOMUX CELL 55 I/O pad name: I2C0_SCL_ USBC_DATA1_MGPIO31B Table 590 • IOMUX CELL 55 IOMUXCELL Interface I/O Pad Ports I2C_0 USB Controller GPIO[31] FPGA Fabric SCL_0_IN USBC_DATAI[1] GPIOB_IN[31] IN_A F2H_GPIN[55] DATAO[1] GPIO_OUT[31] IN_B F2H_SCP[55] ~SCL_0_OUT ~NDATAOE GPIO_OE[31] OUT_A H2F_A[55] OUT_B...
Page 626: Features
Communication Block Communication Block The communication block (COMM_BLK) provides a bi-directional message passing facility between the Cortex-M3 processor and the system controller, similar to a mailbox communication channel. 17.1 Features The COMM_BLK peripheral includes the following features: • Bi-directional byte-wide message path •...
Page 627: Figure 250 Interfacing Of Comm_Blk With Ahb Bus Matrix
Communication Block The following figure depicts the connectivity of COMM_BLK to the advanced high-performance bus (AHB) matrix. Figure 250 • Interfacing of COMM_BLK with AHB Bus Matrix ARM Cortex-M3 Microcontroller Subsystem (MSS) MDDR Processor Cache System MSS DDR Controller eNVM_0 eNVM_1 eSRAM_0 eSRAM_1...
Page 628: Figure 251 Interfacing Of Comm_Blk With System Controller
Communication Block In the other direction, the interrupt (COMM_BLK_INT) goes to both the Cortex-M3 processor and the FPGA fabric through the fabric interface interrupt controller (FIIC). This communication link is used as a message passing mailbox by firmware running on the Cortex-M3 processor and system controller. The following figure shows how COMM_BLKs are connected to create a communication channel between the Cortex-M3 processor and the system controller.
Page 629: Clocks
• NVM Data Integrity Check Service Microsemi provides CoreSysServices soft IP to access the system services implemented by the System Controller from FPGA fabric. The CoreSysServices soft IP provides a user interface for each of the system services and an advanced high-performance bus (AHB)-Lite master interface on the fabric interface controller (FIC) side.
Page 630: Figure 252 System Services Driver In Firmware Core Configurator
Send command opcode and command parameters MSS_COMBLK_send_cmd_with_ptr Send command opcode and command parameters pointer MSS_COMBLK_send_paged_cmd Send command opcode and a page of data Note: Microsemi recommends using system services driver provided in firmware core configurator for system service application development. UG0331 User Guide Revision 15.0...
Page 631: Table 593 Comm_Blk Register Map
• Zeroization service • Programming services Refer to the "System Services" chapter in the UG0450: SmartFusion2 SoC and IGLOO2 FPGA System Controller User Guide to know how to implement the system services. Table 593 on page 597 through Table 600 on page 600...
Page 632: Table 594 Control
Communication Block 17.5 COMM_BLK Register Interface Details This section describes the COMM_BLK registers in detail. 17.5.1 Control Register Table 594 • CONTROL Reset Number Name Value Description [7:6] RESERVED Reserved LOOPBACK After system reset the COMM_BLK is in Loopback mode. Set LOOPBACK bit to ‘0’...
Page 633: Interrupt Enable Register
Communication Block Table 595 • STATUS (continued) SIIDONE Indicated that the transfer to SII Bus is complete. Write 1 to clear UNDERFLOW R/W Receive Overflow. Indicates that the receive FIFO was read when empty. Write 1 to clear OVERFLOW Transmit Overflow. Indicates that the Transmit FIFO was written when full. Write 1 to clear RCVOKAY RCV FIFO non empty.
Page 634: Word Data Register
Communication Block 17.5.5 Word Data Register This register writes a word (32 bits) to the Transmit FIFO or reads a word from the Receive FIFO. If the Transmit FIFO has less than 4 spaces available at the time of a write, an OVERFLOW will be set in the STATUS register.
Page 635: Figure 254 Microcontroller Subsystem Showing Rtc
RTC System RTC System The SmartFusion2 real-time counter (RTC) system keeps track of seconds, minutes, hours, days, weeks, and years. 18.1 Features It has two modes of operation: • Real-time Calendar: Counts seconds, minutes, hours, days, week, months, and years •...
Page 636: Figure 255 Rtc Block Diagram
RTC System 18.2 Functional Description The following sections provide a detailed description of the RTC system. 18.2.1 Architecture Overview This section describes the RTC architecture and its components which are as follows: • Prescaler • RTC Counter • Alarm Wake-up Comparator Figure 255 •...
Page 637: Table 602 Rtc Interface Signals
RTC System Table 601 • Calendar Counter Description (continued) Hour 0-23 0-31 1-31 (auto adjust by month and year) 0-31 Month 1-12 0-15 Year 0-255 0-255 0 (year 2000) Year 2000 to 2255 Weekday Week 1-52 0-63 18.2.1.3 Alarm Wake-up Comparator The RTC has two modes of operation, selectable through the clock_mode bit (Table 605, page 609).
Page 638: Details Of Operation
The prescaler should be programmed to derive a 1 Hz signal. Therefore, for the 32.767 KHz clock, the prescaler should be programmed to 32768 (actual value is N1, that is, 32767). Microsemi recommends that the lowest clock frequency source available is used because this reduces the power consumption;...
Page 639: Figure 256 Enabling Rtc In The Libero Soc Design Mss Configurator
RTC System 18.3 How to Use RTC This section describes how to use the RTC in an application. 18.3.1 Design Flow The following steps are used to enable the RTC in the application: Enable RTC by using the MSS configurator in the application, as shown in the following figure. Figure 256 •...
Page 640: Figure 257 Rtc Configuration Window
RTC System Clicking RTC displays the RTC configuration window, as shown in the following figure. Figure 257 • RTC Configuration Window • Select the Clock Source that drives the RTC system (RTCCLK) as either External 32 KHz RTC crystal oscillator, or On-chip 1 MHz RC oscillator, or On-chip 25/50 MHz RC oscillator (50 MHz in 1.2 V part) •...
Page 641: Figure 259 Rtc Driver User Guide
RTC, can also be downloaded from the Microsemi firmware catalog. The following table lists the APIs for RTC. For more information on the APIs, refer to the SmartFusion2_MSS_RTC_Driver_UG (shown in the preceding figure).
Page 642: Figure 260 Rtc Examples
On reaching the match value, RTC generates the interrupt. Clear the interrupt. Stop RTC increment using the MSS_RTC_stop( ) function Note: The MSS RTC does not support full behavioral simulation models. Refer to SmartFusion2 MSS BFM Simulation User Guide for more information.
Page 643: Table 604 Allocation Of Bits In Calendar Mode
RTC System 18.4.1 Counter Bit Positions The RTC counters support the following two counting modes: • Binary Mode: In Binary mode a 43-bit counter is provided. • Calendar Mode: The 43 bits are allocated as following: Table 604 • Allocation of Bits in Calendar Mode Counter Counts Size Bits...
Page 644: Table 607 Control
RTC System Table 606 • Register Map for RTC (continued) Prescaler 0x08 The value of the prescaler can be written here. This register — should only be written when the RTC is stopped when the control register bit 0 reads as a '0'. Alarm and Compare 0x0C-0x18 R/W Sets and reads the alarm time.
Page 645: Table 608 Mode
RTC System Table 607 • Control (continued) Bit Number Name Reset Value Description Start When '1' is written, the RTC starts. When it is read, it indicates that the RTC is running. Running It reads back '1' as soon as the start bit is written. 18.4.4 Mode Register —...
Page 646: Table 610 Alarm And Compare
RTC System 18.4.6 Alarm and Compare Registers These registers may be written when the RTC is running, but the Alarm must be disabled; the control register bit 2 reads as a '0'. Table 610 • Alarm and Compare Address Register Reset Offset Name...
Page 647: Table 612 The Rtc_Wakeup_Cr In The Sysreg Block
RTC System Table 611 • Date and Time (continued) Address Register Reset Offset Name Numbers Name Value Description 0x50 Date/Time [5:0] Seconds Direct mode returns the date/time at the point that Direct Byte each of the the reads take place. Allows the 0x54 [5:0] Minutes...
Page 648: Figure 261 Mss Showing Timer Peripherals
System Timer System Timer The SmartFusion2 system timer (hereinafter referred as timer) consists of two programmable 32-bit decrementing counters that generate interrupts to the Cortex-M3 processor and FPGA fabric. The two 32-bit timers are identical. X is used as a placeholder for 1, 2, or 64 in register descriptions. It indicates Timer 1, Timer 2, or Timer 64.
Page 649: Figure 262 Timer Block Diagram
19.2.2.1 Clocks Timer is clocked by PCLK0 on the APB0 bus. PCLK is derived from the fabric alignment clock controller (FACC) output. Refer to the UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide more information. 19.2.2.2 Resets Timer resets to zero on power-up and is held in reset until enabled. Libero SoC software can reset the...
Page 650: Details Of Operation
System Timer 19.2.2.3 Interrupts There are two interrupt signals from the system timer block—TIMER1INT and TIMER2INT. The TIMER1INT signal is mapped to INTISR[14] and the TIMER2INT signal is mapped to INTISR[15] in the Cortex-M3 processor nested vectored interrupt controller (NVIC) controller. Both interrupt enable bits within the NVIC (INTISR[14] and INTISR[15]) correspond to bit locations 14 and 15.
Page 651 System Timer Writing to the TIMxBGLOADVAL register in One-shot mode has no real effect unless you intend to switch to Periodic mode when (or before) the next interrupt occurs. When in One-shot mode, the value written to TIMxBGLOADVAL is loaded into the TIMxLOADVAL register as normal but when the counter reaches zero, it generates a single interrupt and stops.
Page 652: Figure 263 Block Diagram 32-Bit Mode
System Timer Figure 263 • Block Diagram 32-Bit Mode APB Bus TIMxBGLOADVAL TIMxLOADVAL TIMxMODE TIMERxINT PCLK TIMERx TIMxENABLE TIMxVALUE APB Bus Figure 264 • Block Diagram 64-Bit Mode APB Bus TIM64BGLOADVAL TIM64BGLOADVAL TIM64LOADVAL TIM64LOADVAL TIM64MODE TIM64MODE TIMER1INT TIMER1INT PCLK TIMER1 PCLK TIMER1 TIM64ENABLE...
Page 653: Figure 265 Timer Driver User Guide
SoftConsole Firmware Project. The SoftConsole folder contains the mss_timer firmware driver. The firmware driver, mss_timer (mss_timer.h) which provides a set of functions for controlling the Timer, can also be downloaded from the Microsemi firmware catalog. The following table lists the APIs for Timer.
Page 654 System Timer Table 615 • MSS Timer APIs (continued) Category Description and Usage Control functions MSS_TIM1_load_immediate() Loads the value passed by the load_value parameter into the Timer1 down-counter. MSS_TIM1_load_background() Specify the value that will be reloaded into the Timer1 down-counter the next time the counter reaches zero.
Page 655: Figure 266 Generating Sample Project
System Timer For more information on Timer usage, the sample projects are available and can be generated, as shown in the following figure. Figure 266 • Generating Sample Project 19.3.2 Timer Use Models 19.3.2.1 Use Model 1: 32-Bit Mode To generate a 1 ms delay with a 100 MHz clock using 32-bit Timer 1 in Periodic mode: Initialize Timer for Periodic mode using MSS_TIM1_init(MSS_TIMER_PERIODIC_MODE).
Page 656: Table 616 Timer Register Map
System Timer 19.3.2.2 Use Model 2: 64-Bit Mode To generate a 30 second delay with a 100 MHz clock using a 64-bit Timer in One-shot mode: Initialize the Timer for One-shot mode using MSS_TIM64_init(MSS_TIMER_ONE_SHOT_MODE). Use MSS_TIM64_load_immediate(load_value) to load required time period For 30 seconds delay load value calculation: •...
Page 657: Tim64_Mis
System Timer Table 616 • Timer Register Map (continued) Address Reset Register Name Offset Value Description TIM64_MIS 0x50 Masked interrupt status for 64-bit mode TIM64_MODE 0x54 Timer dual 32-bit or 64-bit 19.4.1 Timer x Value Register Table 617 • TIMx_VAL Reset Number Name Value...
Page 658: Timer X Raw Interrupt Status Register
System Timer Timer x Control Register Table 620 • TIMx_CTRL Reset Number Name Value Description 31:3 Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 659: Timer X Masked Interrupt Status Register
System Timer 19.4.5 Timer x Masked Interrupt Status Register Table 622 • TIMx_MIS Reset Number Name Value Description 31:1 Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 660: Timer 64 Load Value Lower Register
System Timer 19.4.9 Timer 64 Load Value Lower Register Table 626 • TIM64_LOADVAL_L Reset Number Name Value Description 31:0 TIM64_LOADVAL_L When this register is written, the value written is loaded immediately into the lower 32 bits of the 64-bit counter along with the value written in register TIM64_LOADVAL_U.
Page 661: Table 629 Tim64_Ctrl
System Timer 19.4.11 Timer 64 Background Load Value Lower Register Table 628 • TIM64_BGLOADVAL_L Reset Number Name Value Description 31:0 TIM64_BGLOADVAL_ R/W 0 Background load value for the lower 32 bits of 64-bit Timer. When this register is written, both the upper and lower words are written into an internal 64-bit TIM64LOADVAL register without updating the counter.
Page 662: Timer 64 Raw Interrupt Status Register
System Timer 19.4.13 Timer 64 Raw Interrupt Status Register Table 630 • TIM64_RIS Reset Number Name Value Description 31:1 Reserved Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
Page 663: Figure 267 Microcontroller Subsystem Showing Watchdog Timer
Watchdog Timer Watchdog Timer The watchdog timer is an advanced peripheral bus (APB) slave that guards against the system crashes by requiring regular service by the Cortex-M3 processor or by a bus master in the field programmable gate array (FPGA) fabric. 20.1 Features The watchdog timer has following features:...
Page 664: Figure 268 Block Diagram For The Watchdog Timer
Watchdog Timer 20.2 Functional Description This following sub-sections provide a detailed description of the Watchdog timer. 20.2.1 Architecture Overview The watchdog timer consists of following components (as shown in the following figure): • APB Interface • 32-Bit Counter • Timeout Detection Figure 268 •...
Page 665: Table 633 Watchdog Timer Interface Signals
Watchdog Timer The memory map address for the watchdog timer is 0x40005000-0x40005FFF. The 32-bit counter in the watchdog timer is clocked with the clock signal from the RC Oscillator (RCOSCCLK) which has a frequency of 50 MHz (if Vdd = 1.2 V) with a 5% tolerance. 20.2.1.3 Timeout Detection A control bit in the WDOGCONTROL register is used to determine whether the watchdog timer generates a reset or an interrupt if a counter timeout occurs.
Page 666: Figure 269 Watchdog Timer Counter
Watchdog Timer The following figure shows how the value of the watchdog timer counter might vary with time. Figure 269 • Watchdog Timer Counter counter value WDOGLOAD Refresh of counter not allowed while counter value is in this region WDOGMVRP Reset interrupt generated due to Refresh of counter...
Page 667: How To Use The Watchdog Timer
Watchdog Timer 20.2.3.2.2 Cortex-M3 Processor in Sleep Mode The Cortex-M3 processor can be put into a low-power state by entering sleep mode. The processor exits sleep mode when an interrupt occurs. The watchdog timer can be configured to generate an interrupt if its counter value moves from the permitted to the forbidden window (at the WDOGMVRP level) when the Cortex-M3 processor is in sleep mode.
Page 668: Figure 270 Enabling Watchdog Timer In The Libero Soc Design Mss Configurator
Watchdog Timer 20.3.1 Design Flow The following steps are used to enable the WatchDog Timer in the application: Enable the watchdog timer by using the MSS configurator in the application, as shown in the following figure. Figure 270 • Enabling Watchdog Timer in the Libero SOC Design MSS Configurator UG0331 User Guide Revision 15.0...
Page 669: Figure 271 Watchdog Timer Configuration Window
Watchdog Timer Clicking Watchdog Timer displays the watchdog timer configuration window, as shown in the following figure. Figure 271 • Watchdog Timer Configuration Window • Timeout behavior: The watchdog timer default setting is reset generation on timeout. When interrupt generation is selected, the WDOGTIMEOUTINT output is asserted on timeout and remains asserted until the interrupt is cleared •...
Page 670: Figure 273 Rtc Driver User Guide
Microsemi firmware catalog. The following table lists the APIs for Watchdog Timer. For more information on the APIs, refer to the SmartFusion2_MSS_Watchdog_Driver_UG.
Page 671: Figure 274 Watchdog Timer Examples
The watchdog timer cannot be disabled through software. Only the interrupts can be disabled. • The MSS Watchdog timer does not support full behavioral simulation models. Refer to SmartFusion2 MSS BFM Simulation User Guide for more information. UG0331 User Guide Revision 15.0...
Page 672: Table 635 Watchdog Timer Register Interface Summary
Watchdog Timer 20.4 Watchdog Timer Register Map The following table summarizes the watchdog timer register interface. Detailed description of the registers is given in Watchdog Timer Configuration Register Bit Definitions, page 638. The base address for the register details resides at 0x40005000 and extends to the address 0x40005FFF in the Cortex-M3 processor memory map.
Page 673: Table 640 Wdogenable
Watchdog Timer Table 638 • WDOGMVRP Bit Number Name Reset Value Description [31:0] WDOGMVRP WDOGMVRP This register contains the maximum value for which refreshing is permitted. If the watchdog timer is refreshed (by writing to the WDOGREFRESH register) while the counter value is greater than the value in the WDOGMVRP, then a reset/interrupt is generated.
Page 674: Table 641 Wdogcontrol
Watchdog Timer Table 641 • WDOGCONTROL Bit Number Name Reset Value Description [31:3] Reserved To provide compatibility to the future products, the value of a reserved bit should be preserved across a read-modify-write operation. MODE WDOGMODE Operation mode for the watchdog timer. 0: reset is generated if counter reaches zero.
Page 675: Table 644 Watchdog Timer Sysreg
Watchdog Timer 20.5 SYSREG Control Registers In addition to the specific watchdog timer registers mentioned in Table 635, page 638, the registers mentioned in the following table also control the behavior of the watchdog timer. These registers are located in the System Register Block and are listed here for clarity. Refer to the SYSREG section of System Register Block, page 670 for a detailed description of each register and bit.
Page 676: Figure 275 Reset Signals Distribution In Smartfusion2 Devices
MSS or individual resets to the MSS sub-blocks and user logic in the FPGA fabric. The Reset Controller drives resets to various modules of the SmartFusion2 devices, such as the Cortex-M3 processor, MDDR subsystem, Watchdog Timer, FPGA fabric, MSS GPIO, clock controller, SYSREG, and peripherals.
Page 677: Figure 276 Conceptual Block Diagram Of Power-On Reset Generation
The following figure shows the conceptual block diagram of power-on reset generation. The POR generator block in System Controller generates a power-on reset signal, PO_RESET_N. Figure 276 • Conceptual Block Diagram of Power-On Reset Generation SmartFusion2 SoC FPGA MSS_RESET_N_M2F FPGA Fabric...
Page 678: Figure 277 Power On Reset Delay Configuration
• Completion of zeroization A dedicated input-only reset pad (DEVRST_N) is present on all the SmartFusion2 devices, which cause assertion to the PO_RESET_N signal. If an external reset circuit is connected to the DEVRST_N pin, it increases the power up to functional time due to the delays that the external reset device does add.
Page 679: Figure 279 Power Up To Functional Time Sequence Diagram
Although, the JTAG I/Os are still enabled, they cannot be used as the TAP controller is in reset. The SYSRESET macro is not required to be instantiated to enable the DEVRST_N pin in the user design. DEVRST_N is a dedicated input-only reset pad available on all the SmartFusion2 devices. 21.1.2 Power-Up to Functional Time Sequence The following figure shows the power up to functional time sequence diagram.
Page 680: Power-Up To Functional Time Data
How to Use the Reset Controller, page 666 for more information. In order to simplify the task of initializing a user design in SmartFusion2 devices, Microsemi provides a CoreResetP soft Reset Controller IP. The CoreResetP handles sequencing of reset signals in SmartFusion2 devices.
Page 681: Figure 280 Vdd Power-Up To Functional Time Design Setup
Reset Controller 21.2.2 VDD Power-Up to Functional Time The core supply voltage VDD is connected to the appropriate source and VDD is monitored by the power-on reset circuitry to check if it reaches the minimum threshold value and initiates the system controller to release the device from reset.
Page 682: Figure 281 Vdd Power-Up To Functional Timing Diagram
Reset Controller The following figure shows the behavior of different signals when VDD is ramped with a power on reset delay of 1 ms from 0 V to its minimum threshold level and MSS is used with VDD = 1.2 V, VDDI = 2.5 V, Tj = 25 °C, and power on reset delay setting = 1 ms.
Page 683 Reset Controller Table 645 • VDD Power-Up to Functional Time (continued) Power-Up to Functional Time (µs) Test Case Start Point End Point Description Case 7 DDRIO input at its 2500 2487 2509 2475 2507 2519 2617 buffer weak pull minimum threshold level to input buffer weak pull...
Page 684: Figure 282 Vdd Power-Up To Functional Time Flow
Reset Controller The following figure shows stages that contribute to VDD power-up to functional time for SmartFusion2. Figure 282 • VDD Power-Up to Functional Time Flow Note: Power-up to functional time depends on power-on reset delay setting, 1 MHz oscillator frequency, and period variability.
Page 685: Figure 283 Devrst_N Power-Up To Functional Timing
For more information on proper usage of the DEVRST_N pin, see the AC393: Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Application Note. The following figure shows the behavior of different signals when DEVRST_N is asserted and MSS is used with VDD = 1.2 V, VDDI = 2.5 V, and Tj = 25 °C.
Page 686 Reset Controller Table 646 • DEVRST_N Power-Up to Functional Time (continued) Power-Up to Functional Time (µs) Test Case Start Point End Point Description Case 7 DEVRST_N DDRIO input DEVRST_N to buffer weak pull input buffer weak DEVRST_N MSIO input DEVRST_N to buffer weak pull input buffer weak DEVRST_N...
Page 687: Figure 284 Devrst_N Power-Up To Functional Time Flow
Reset Controller The following figure shows the stages that contribute to DEVRST_N power-up to functional time for SmartFusion2. Figure 284 • DEVRST_N Power-up to Functional Time Flow Note: All timing numbers in Table 645, page 648 and Table 646, page 651 are for worst case conditions.
Page 688: Figure 285 Functional Block Diagram Of Reset Controller During Power-On Reset
The Reset Controller receives a power-on reset signal, PO_RESET_N, from the System Controller, which is a cold reset signal. Its assertion initializes the SmartFusion2 device to its default reset state. PO_RESET_N signal is fed to the system register block (SYSREG). The PO_RESET_DETECT bit of the...
Page 689: Figure 286 Sysreset_N Generation
Reset Controller The generation of SYSRESET_N is shown in the following figure. Figure 286 • SYSRESET_N Generation SYSRESET_N M3_CLK SYS_RESET_REQ_N LOCKUP_N WD_TIMEOUT_N SC_MSS_RESET_N MSS_RESET_N_F2M The inputs SYS_RESET_REQ_N, LOCKUP_N, WD_TIMEOUT_N, SC_MSS_RESET_N, and MSS_RESET_N_F2M are first synchronized on M3_CLK and then combined. The MSS_RESET_N_F2M signal can be used to reset the MSS, independently of any resets coming from the MSS itself.
Page 690: Figure 288 Reset Controller With Only Block Level Resets
Reset Controller • Instrumentation trace macrocell (ITM) • AHB-AP 21.2.6 Block Resets The Reset Controller generates block level resets for all modules except the AHB bus matrix, cache controller, fabric interface interrupt controller (FIIC), RTC, and SYSREG. These blocks will be reset at power-on reset or system reset.
Page 691: Figure 289 M3_Sys_Reset_N Generation
Reset Controller 21.2.6.1.3 T_RESET_N This is also a reset signal to the Cortex-M3 processor. The T_RESET_N is a synchronized signal of PO_RESET_N on TRACECLK (Trace clock input from the clock controller). It asserts asynchronously and negates synchronously to TRACECLK. 21.2.6.1.4 M3_SYS_RESET_N M3_SYS_RESET_N resets the Cortex-M3 processor core and its components, excluding the debug logic.
Page 692: Figure 291 Mddr_Apb_Reset_N Generation
Reset Controller The generation of MDDR_APB_RESET_N is shown in the following figure. Figure 291 • MDDR_APB_RESET_N Generation SYSRESET_N MDDR_APB_RESET_N MDDR_APB_S_RESET_N MDDR_CONFIG_LOCAL The Reset Controller drives a synchronized reset to the APB logic of the MDDR subsystem. 21.2.6.3 Watchdog Resets 21.2.6.3.1 WDOG_RESET_N The WDOG_BLOCK_RESET_N signal is synchronized on M3_CLK and CLK_RCOSC, then gated with WDOG_ENABLE.
Page 693: Figure 293 Fic_2_Apb_M_Preset_N Generation
Reset Controller The generation of FIC_2_APB_M_PRESET_N is shown in the following figure. Figure 293 • FIC_2_APB_M_PRESET_N Generation M3_CLK 4FFs FIC_2_APB_M_PCLK SYSRESET_N 21.2.6.5 MSS GPIO Bank Resets Generator The MSS GPIOs bank can be selectively reset through SYSREG or from flash bits. The GPOUT register is split into four banks of one byte each and each bank has a reset signal.
Page 694: Figure 294 Mss Gpio_Out Reset Generation
HPDMA, USB OTG, COMM_BLK, FIC_0, FIC_1 (if present), MSS_GPIO (MSS_GPIO_RESET_N reset), and the FPGA fabric (MSS_RESET_N_M2F reset). 21.3 CoreResetP Soft Reset Controller The following Reset sub-systems in SmartFusion2 devices that must be sequenced properly for the overall system to function correctly. • Chip Boot (System Controller) •...
Page 695: Figure 296 Mss_Ready Signal Generation
Reset Controller • The FIC sub-systems resets: Both MSS and FPGA fabric should be out of reset to establish the communication between them. CoreResetP generates MSS_READY signal which indicates that both MSS and FPGA fabric are out of reset and ready for communication. •...
Page 696: Figure 297 Coreresetp Connectivity With Peripheral Resets
Reset Controller 21.3.1.2 Peripheral Initialization CoreResetP generates reset signals to initialize MDDR, FDDR and SERDES_IF peripheral blocks. The following figure shows the CoreResetP connectivity with peripheral resets. For each SERDES_IF blocks, the CoreResetP generates SDIFx_PHY_RESET_N and SDIFx_CORE_RESET_N signals which need to be connected to SERDES_IF macro on PHY_RESET_N and CORE_RESET_N respectively.
Page 697: Figure 298 Coreresetp Connectivity With Serdes_If Block
Note: CoreConfigP soft IP facilitates configuration of peripheral blocks (MDDR, FDDR, and SERDESIF blocks) in a SmartFusion2 devices. CoreConfigP is available in the Libero SoC IP Catalog. Refer to the CoreConfigP Handbook for port lists and their descriptions, design flows, memory maps, and Control and Status register details.
Page 698: Figure 299 Timing For Reset Signals Initiated By The Assertion Of Power_N_Reset_N
Reset Controller 21.3.3 Timing Diagrams The following figures show the timing of reset signals for reset sequences initiated by the assertion of POWER_ON_RESET_N, FIC_2_APB_M_PRESET_N, EXT_RESET_IN_N, and USER_FAB_RESET_IN_N signals. Figure 299 • Timing for Reset Signals Initiated by the Assertion of POWER_N_RESET_N Figure 300 •...
Page 699: Figure 301 Timing For Reset Signals Initiated By The Assertion Of Ext_Reset_In_N
Reset Controller Figure 301 • Timing for Reset Signals Initiated by the Assertion of EXT_RESET_IN_N Figure 302 • Timing for Reset Signals Initiated by the Assertion of USER_FAB_RESET_IN_N UG0331 User Guide Revision 15.0...
Page 700: Figure 303 Ramp Delay Configuration
Reset Controller 21.4 How to Use the Reset Controller 21.4.1 Ramp Delay Configuration The delay can be configured to 50 µs, 1 ms, 10 ms, or 100 ms in the New Project window while creating the Libero SoC project as shown in the following figure. Users can also access and change this setting after the project has been created from the Project Settings window.
Page 701: Figure 305 Configuring Reset
Use the following steps for holding the Cortex-M3 reset from the fabric. Instantiate the SmartFusion2 MSS component in the SmartDesign canvas. Configure the SmartFusion2 MSS peripheral components as needed using the MSS configurator. Configure the Reset Controller, as shown the following figure.
Page 702: Figure 307 Initialization Sub-System With Coreresetp Soft Ip
Reset Controller Follow the rest of the steps with default settings and generate the design. The following figure shows the generated design when opened in SmartDesign. The actual SmartDesign created by System Builder is typically not visible unless you open the gen- erated output as a SmartDesign.
Page 703: Figure 308 Initialization Sub-System For Fic Sub-Systems
Reset Controller Figure 308 • Initialization Sub-system for FIC Sub-systems 21.5 SYSREG Control Registers The description of registers are located in the SYSREG section of the user's guide and are listed in the following table. Refer to the System Register Block, page 670 for a detailed description of each register and bit.
Page 704: Figure 309 Register Write Protect
System Register Block System Register Block The System Register (SYSREG) block is an array of system-level registers that contain user configuration information used to configure the microcontroller subsystem (MSS). The contents of these registers are initially set based on the information entered using the MSS configurator in the Libero software.
Page 705: Figure 310 Field Write Protect
System Register Block 22.0.1.2 Field Write Protect Many System Registers contain fields of multiple bits. A Field Write Protect bit provides write protection for an entire field within a single register as shown in the following figure. Field Write Protect bits follow the same rules as Register Write Protect bits described in Register Write Protect, page 670, but are...
Page 706: Figure 312 Rw-P Type
System Register Block Table 649 • Register Types (continued) Type Function Supports read and write accesses via AHB bus matrix. Refer to Figure 313, page 673. Register contents are not initialized from flash configuration bits at power-up. The reset state is determined by the user HW design following assertion of SYS_RESET_N.
Page 707: Figure 313 Rw Type
System Register Block Figure 313 • RW Type AHB Bus Matrix LOADENABLEFLOP Hardware Default (per-bit) REG_BIT Reset Controller Figure 314 • RO Type AHB Bus Matrix UG0331 User Guide Revision 15.0...
Page 708: Figure 315 Ro-P Type
The Register Lock Bits Configuration tool is used to lock MSS, SERDES, and FDDR configuration registers of SmartFusion2 devices in order to prevent them from being overwritten by masters that have access to these registers. Register lock bits are set in a text (*.txt) file, which is then imported into the SmartFusion2 project.
Page 709: Figure 318 Lock Bit Configuration File
• • FDDR • SERDES_IF_x (where x is 0,1,2,3 to indicate the physical SERDES location) for SmartFusion2 M2S010/025/050/150 devices • SERDES_IF2 for SmartFusion2 M2S060/090 devices (only one SERDES block per device) Set the lock bit value to 1 to indicate that the register can be written to (unlocked) and to 0 to indicate that the register cannot be written to (locked).
Page 710: Table 650 Sysreg
System Register Block 22.1.3 Locking and Unlocking a Register A register can be locked or unlocked by setting the appropriate lock bit value in the lock bit configuration file. .txt Browse to locate the lock bit configuration file. .txt Do one or both of the following: •...
Page 711: Master_Weight1_Cr
System Register Block Table 650 • SYSREG (continued) Flash Addr. Register Write Register Name Offset Type Protect Reset Source Description EDAC_CR 0x38 RW-P Register SYSRESET_ EDAC Configuration Register for eSRAM0, eSRAM1, USB, MAC, and CAN MASTER_WEIGHT0_CR 0x3C RW-P Register SYSRESET_ Master Weight Configuration Register 0 MASTER_WEIGHT1_CR...
Page 712: Mac_Stat_Clronrd_Cr
System Register Block Table 650 • SYSREG (continued) Flash Addr. Register Write Register Name Offset Type Protect Reset Source Description MAC_CR 0x8C RW-P Register SYSRESET_ MAC Configuration Register MSSDDR_PLL_STATUS_LOW 0x90 RW-P Register CC_RESET_ Controls the configuration input of MPLL register MSSDDR_PLL_STATUS_HIG 0x94 RW-P...
Page 713: Ddrb_Hpd_Err_Adr_Sr
System Register Block Table 650 • SYSREG (continued) Flash Addr. Register Write Register Name Offset Type Protect Reset Source Description DDRB_HPD_ERR_ADR_SR 0xE0 SYSRESET_ MSS DDR Bridge High Performance DMA Master Error Address Status Register DDRB_SW_ERR_ADR_SR 0xE4 SYSRESET_ MSS DDR Bridge AHB Bus Error Address Status Register DDRB_BUF_EMPTY_SR 0xE8...
Page 714: M3_Sr
System Register Block Table 650 • SYSREG (continued) Flash Addr. Register Write Register Name Offset Type Protect Reset Source Description MM4_5_DDR_FIC_SECURITY 0x128 RO-U SYSRESET_ Read and write security for /MM4_5_FIC64_SECURITY masters 4, 5, and DDR_FIC to eSRAM0, eSRAM1, eNVM1, eNVM0, and MSS DDR bridge MM3_6_7_8_SECURITY 0x12C RO-U...
Page 715: Fab_Prot_Size
System Register Block Table 650 • SYSREG (continued) Flash Addr. Register Write Register Name Offset Type Protect Reset Source Description USERCONFIG1 0x178 RO-P SYSRESET_ User Configuration Register 1 USERCONFIG2 0x17C RO-P SYSRESET_ User Configuration Register 2 USERCONFIG3 0x180 RO-P SYSRESET_ User Configuration Register 3 FAB_PROT_SIZE 0x184...
Page 716: Table 651 Subset Of System Registers
Application traffic across the FIC_0 interface can cause certain bits in the SYSREG block to change state, if these bits are dynamically modified from their default values during runtime. This impacts all SmartFusion2 005 and 010 devices. The following table lists the subset of system registers and specific bit definitions that are affected. The registers/bits listed in the following table should be configured once on power-up.
Page 717: Esram Configuration Register
System Register Block 22.3.2 eSRAM Configuration Register Table 652 • ESRAM_CR Reset Number Name Value Description [31:2] Reserved SW_CC_ESRAM1FWREMAP 0 Defines the locations of eSRAM_0 and eSRAM_1 if eSRAM remap is enabled (if SW_CC_ESRAMFWREMAP is asserted). If SW_CC_ESRAMFWREMAP is 0, this bit has no meaning. If SW_CC_ESRAMFWREMAP is 1, this bit has the following definition: 0: eSRAM_0 is located at address 0x00000000 in the...
Page 718: Table 654 Esram Maximum Latency Values
System Register Block The following table lists eSRAM maximum latency values, where x is either 0 or 1. Table 654 • eSRAM Maximum Latency Values SW_MAX_LAT_ESRAM<X> Latency 8 (default) 22.3.4 DDR Configuration Register Table 655 • DDR_CR Reset Number Name Value Description [31:1]...
Page 719: Table 656 Envm_Cr
System Register Block Table 656 • ENVM_CR (continued) [12:5] NV_FREQRNG Setting of NV_FREQRNG[8:5] or NV_FREQRNG[12:9] determines the behavior of eNVM BUSY_B with respect to the AHB Bus interface clock. It can be used to accommodate various frequencies of the external interface clock, M3_CLK, or it can be used to advance or delay the data capture due to variation of read access time of the NVM core.
Page 720: Envm Remap Base Address Control Register
System Register Block 22.3.5.1 SW_ENVMREMAPSIZE Bit Combinations Table 657 • SW_ENVMREMAPSIZE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Remap Size Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 16 KB 32 KB 64 KB 128 KB 256 KB...
Page 721: Envm Fpga Fabric Remap Base Address Register
System Register Block Bits [18:N] of this bus indicate the base address of the remapped segment. The value of N depends on the eNVM remap section size, so that the base address is aligned according to an even multiple of the segment size.
Page 722: Table 660 Cc_Cr
System Register Block Table 660 • CC_CR (continued) CC_CACHE_ENB Allows the cache to be disabled. The allowed values: 0: Disabled 1: Enabled 22.3.9 Cache Region Control Register Table 661 • CC_REGION_CR Reset Number Name Value Description [31:4] Reserved CC_CACHE_REGION Defines the cache region size. The bits have the following definitions: Bit 0: First (lower) slot of 128 MB (0–128 MB) Bit 1: Second slot of 128 MB (128–256 MB)
Page 723: Mss Ddr Bridge Buffer Timer Control Register
System Register Block 22.3.12 MSS DDR Bridge Buffer Timer Control Register Table 664 • DDRB_BUF_TIMER_CR Reset Number Name Value Description [31:10] Reserved [9:0] DDRB_TIMER 0x3FF 10-bit timer interface used to configure the timeout register in the write buffer module. Once timer reaches the timeout value, a flush request is generated by the flush controller and if response has been received for previous write request from write arbiter, this request is posted to the write arbiter.
Page 724: Mss Ddr Bridge Configuration Register
System Register Block Table 667 • Non-Bufferable Region (continued) 2 MB = (26 – 1 x 64) KB 4 MB = (27 – 1 x 64) KB 8 MB= (28 – 1 x 64) KB 16 MB = (29 – 1 x 64) KB 32 MB = (210 –...
Page 725: Table 668 Ddrb_Cr
System Register Block Table 668 • DDRB_CR (continued) DDRB_HPD_WEN 0x1 Allows the write combining buffer for high performance DMA master in MSS DDR bridge to be disabled. Allowed values: 0: Disabled 1: Enabled DDRB_DS_REN Allows the read buffer for DSG master in MSS DDR bridge to be disabled. Allowed values: 0: Disabled 1: Enabled...
Page 726: Table 670 Master_Weight0_Cr
System Register Block Table 670 • MASTER_WEIGHT0_CR (continued) [24:20] SW_WEIGHT_FAB_1 Configures the round robin weight for fabric (FIC_1) master. It is configurable from 1 to 32 (32 by default). [19:15] SW_WEIGHT_FAB_0 Configures the round robin weight for fabric (FIC_0) master. It is configurable from 1 to 32 (32 by default).
Page 727: Software Interrupt Register
System Register Block 22.3.19 Software Interrupt Register Table 673 • SOFT_IRQ_CR Reset Number Name Value Description [31:1] Reserved SOFTINTERRUPT 1: FIIC SOFTINTERRUPT is asserted 0: SOFTINTERRUPT signal is cleared 22.3.20 Software Reset Control Register Table 674 • SOFT_RESET_CR Reset Number Name Value Description [31:27]...
Page 728: Table 674 Soft_Reset_Cr
System Register Block Table 674 • SOFT_RESET_CR (continued) Reset Number Name Value Description CAN_SOFTRESET 0: Releases CAN from reset 1: Keeps CAN in reset I2C1_SOFTRESET 0: Releases I2C_1 from reset 1: Keeps I2C_1 in reset I2C0_SOFTRESET 0: Releases I2C_0 from reset 1: Keeps I2C_0 in reset SPI1_SOFTRESET 0: Releases SPI1 from reset...
Page 729: M3 Configuration Register
System Register Block 22.3.21 M3 Configuration Register Table 675 • M3_CR Number Name Reset Value Description [31:29] Reserved M3_MPU_DISABLE When set, disables the memory protection unit (MPU) within the Cortex-M3 processor. [27:26] STCLK_DIVISOR Configures the amount of division to be performed on M3_CLK, in order to generate the STCLK input for the Cortex-M3 processor.
Page 730: Table 676 Fab_If_Cr
System Register Block Table 676 • FAB_IF_CR (continued) FAB1_AHB_BYPASS 0: FIC_1 is configured for synchronous bridging 1: FIC_1 is configured in bypass mode, if clock ratio is 1:1 and if in AHB mode FAB0_AHB_BYPASS 0: FIC_0 is configured for synchronous bridging 1: FIC_0 is configured in bypass mode, if clock ratio is 1:1 and if in AHB mode Note: Do not change these register fields dynamically for 005 and 010 devices, see...
Page 731: Gpio Input Source Select Control Register
System Register Block Table 678 • GPIO_SYSRESET_SEL_CR (continued) MSS_GPIO_23_16_SYSRESET_SEL 0: Selects the combination of either power-on reset or the MSS_GPIO_RESET_N signal from the FPGA fabric to reset the GPIO 1: Causes GPIO[23:16] to be held in reset by the soft reset signal MSS_GPIO_23_16_SOFT_RESET MSS_GPIO_15_8_SYSRESET_SEL 0: Selects the combination of either power-on reset or...
Page 732: Usb I/O Input Select Control Register
System Register Block Table 680 • MDDR_CR (continued) MDDR_CONFIG_LOCAL Configures whether the MSS AHBTOAPB2 bridge can directly access the APB slave within the MDDR subsystem or whether the APB slave is connected to the fabric. Allowed values: 0: AHBTOAPB2 bridge cannot access MDDR APB slave 1: AHBTOAPB2 bridge can access MDDR APB slave Reset signal for this bit is CC_RESET_N.
Page 733: Watchdog Configuration Register
System Register Block 22.3.29 Watchdog Configuration Register Table 683 • WDOG_CR Reset Number Name Value Description [31:2] Reserved WDOGMODE Resets/interrupts the mode selection bit from System Register. This value can be read from the WDOGCONTROL register within the WatchDog module. WDOGENABLE Enables the bit for Watchdog module.
Page 734 System Register Block Table 685 • EDAC_IRQ_ENABLE_CR (continued) Reset Number Name Value Description MDDR_ECC_INT_EN Allows the error EDAC for MDDR status update to be disabled. Allowed values: 0: Disabled 1: Enabled CAN_EDAC_2E_EN Allows the 2-bit error EDAC for CAN status update to be disabled. Allowed values: 0: Disabled 1: Enabled...
Page 735: Usb Configuration Register
System Register Block Table 685 • EDAC_IRQ_ENABLE_CR (continued) Reset Number Name Value Description ESRAM0_EDAC_2E_EN Allows the 2-bit error EDAC for eSRAM0 status update to be disabled. Allowed values: 0: Disabled 1: Enabled ESRAM0_EDAC_1E_EN Allows the 1-bit error EDAC for eSRAM0 status update to be disabled.
Page 736: Rtc Wake Up Configuration Register
System Register Block MSS Interrupt Enable Control Register Table 688 • MSS_IRQ_ENABLE_CR Reset Number Name Value Description [31:20] Reserved [19:10] DDRB_INTERRUPT_EN 0x3FF Used to mask the MSS DDR bridge interrupt to the Cortex-M3 processor [9:7] CC_INTERRUPT_EN Used to mask the cache interrupt to the Cortex-M3 processor [6:0] SW_INTERRUPT_EN 0x7F...
Page 737: Mss Ddr Pll Status Low Configuration Register
+1. For example, if the value is 00000, then the divisor value is 1 (00000 + 1). Both REFCLK and post-divide REFCLK must be within the range specified in the SmartFusion2 datasheet. Note: Do not change these register fields dynamically for 005 and 010 devices, see...
Page 738: Mss Ddr Pll Status High Configuration Register
System Register Block 22.3.36.1 FACC_PLL_RANGE Table 692 • FACC_PLL_RANGE Bits[23:19] PLL Range 0000 Bypass 0111 18–29 MHz 0001 1–1.6 MHz 1000 29–46 MHz 0010 1.6–2.6 MHz 1001 46–75 MHz 0011 2.6–4.2 MHz 1010 75–120 MHz 0100 4.2–6.8 MHz 1011 120–200 MHz 0101 6.8–11 MHz 0110...
Page 739: Mss Ddr Fabric Alignment Clock Controller (Facc) Configuration Register 1
System Register Block Table 693 • MSSDDR_PLL_STATUS_HIGH_CR (continued) Reset Bit Number Name Value Description FACC_PLL_BYPASS Powers down the MPLL core and bypasses it such that PLLOUT tracks REFCLK. Note: Do not change these register fields dynamically for 005 and 010 devices, see System Registers Behavior for M2S005/010 Devices, page 682.
Page 740 System Register Block Table 694 • MSSDDR_FACC1_CR (continued) Reset Bit Number Name Value Description PERSIST_CC Feeds into the MSS Reset Controller. Based on the value of PERSIST_CC, the Reset Controller asserts a reset (CC_RESET_N) to the FACC (which inverts it and passes it on to the PLL as MSSDDR_PLL_RESET), either on every MSS system reset or just on power-up reset.
Page 741: Table 695 Clock Ratio
System Register Block Table 694 • MSSDDR_FACC1_CR (continued) Reset Bit Number Name Value Description [4:2] APB0_DIVISOR Indicates the ratio between CLK_A and APB_0_CLK. The user can write to this field dynamically during run time, even when the source clock is active. The allowed values are described in Table 695, page 707.
Page 742: Table 696 Mssddr_Facc2_Cr
System Register Block Table 696 • MSSDDR_FACC2_CR (continued) Reset Number Name Value Description MSS_1MHZ_EN Enables the signal for the 1 MHz RC oscillator. If the 1 MHz RC oscillator is selected as the MSS Flash*Freeze clock source, this bit must be asserted at all times (even when not in Flash*Freeze mode). 1: Enable 0: Disable MSS_25_50MHZ_EN...
Page 743: Pll Lock Enable Control Register
System Register Block Table 696 • MSSDDR_FACC2_CR (continued) Reset Number Name Value Description [1:0] RTC_CLK_SEL Indicates which of the possible clocks are to be configured as the source of the MSS RTC clock. The allowed values are as follows: 00: RTC_CLK comes from XTLOSC_CLK 01: RTC_CLK comes from RCOSC_1MHZ.
Page 744: Mac Status Clear On Read Control Register
System Register Block 22.3.43 MAC Status Clear on Read Control Register Table 700 • MAC_STAT_CLRONRD_CR Reset Number Name Value Description [31:1] Reserved MAC_STAT_CLRONRD MAC statistics counters that have been set are cleared after they are read. 22.3.44 Reset Source Control Register Table 701 •...
Page 745: Dcode Bus Error Address Status Register
System Register Block 22.3.45 Dcode Bus Error Address Status Register Table 702 • CC_DC_ERR_ADDR_SR Reset Number Name Value Description [31:0] CC_DC_ERR_ADDR Stores the address from the DCode bus on which an error has occurred. 22.3.46 ICode Bus Error Address Status Register Table 703 •...
Page 746: Dcode Miss Control Status Register
System Register Block 22.3.50 DCode Miss Control Status Register Table 707 • CC_DC_MISS_CNTR_SR Reset Number Name Value Description [31:0] CC_DC_MISS_CNT Counts the total number of cache misses that occurs on the cacheable region through the DCode bus. Rolls back after maximum value.
Page 747: Mss Ddr Bridge Ds Master Error Address Status Register
System Register Block 22.3.54 MSS DDR Bridge DS master Error Address Status Register Table 711 • DDRB_DS_ERR_ADR_SR Reset Number Name Value Description [31:0] DDRB_DS_ERR_ADD If a write transfer initiated at the MSS DDR bridge arbiter interface to empty data present in the write buffer of the DS master which receives an error response, the address for which error response is received is placed in this register.
Page 748: Mss Ddr Bridge Buffer Empty Status Register
System Register Block 22.3.57 MSS DDR Bridge Buffer Empty Status Register Table 714 • DDRB_BUF_EMPTY_SR Reset Number Name Value Description [31:7] Reserved DDRB_IDC_RBEMPTY When set to ‘1’, indicates that the read buffer of the IDC master does not have valid data. DDRB_HPD_RBEMPTY When set to ‘1’, indicates that the read buffer of the HPDMA master does not have valid data.
Page 749: Esram0 Edac Count
System Register Block 22.3.59 eSRAM0 EDAC Count Table 716 • ESRAM0_EDAC_CNT Reset Number Name Value Description [31:16] ESRAM0_EDAC_CNT_2E 16-bit counter value in eSRAM0 incremented by eSRAM0 EDAC 2-bit error. The counter will not roll back and will stay at its maximum value. [15:0] ESRAM0_EDAC_CNT_1E I16-bit counter value in eSRAM0 incremented by eSRAM0...
Page 750: Usb Edac Count
System Register Block 22.3.63 USB EDAC Count Table 720 • USB_EDAC_CNT Reset Number Name Value Description [31:16] USB_EDAC_CNT_2E 16-bit counter that counts the number of 2-bit errors for USB. The counter will not roll back and will stay at its maximum value.
Page 751: Mac Edac Receiver Address Register
System Register Block 22.3.67 MAC EDAC Receiver Address Register Table 724 • MAC_EDAC_RX_ADR Reset Number Name Value Description [31:26] Reserved [25:13] MAC_EDAC_RX_2E_AD Stores the address from Ethernet RX memory on which a 2-bit SECDED error has occurred. [12:0] MAC_EDAC_RX_1E_AD Stores the address from Ethernet RX memory on which a 1-bit SECDED error has occurred.
Page 752: Table 728 Mm0_1_2_Security
System Register Block 22.3.71 Security Configuration Register for Masters 0, 1, and 2 Table 728 • MM0_1_2_SECURITY Reset Number Name Value Description [31:10] Reserved MM0_1_2_MS6_ALLOWED_W Write security bits for masters 0, 1, and 2 to slave 6 (MSS DDR bridge). If not set, masters 0, 1, and 2 will not have write access to slave 6.
Page 753: Table 730 Mm3_6_7_8_Security
System Register Block Table 729 • MM4_5_DDR_FIC_SECURITY/MM4_5_FIC64_SECURITY (continued) Reset Number Name Value Description MM4_5_DDR_FIC_MS3_ALLOWED_W 1 Write security bits for masters 4, 5, and DDR_FIC to slave 3 (eNVM1). If not set, masters 4, 5, and DDR_FIC will not have write access to slave 3. MM4_5_DDR_FIC_MS3_ALLOWED_R 1 Read security bits for masters 4, 5, and DDR_FIC to slave 3 (eNVM1).
Page 754: Security Configuration Register For Master 9
System Register Block Table 730 • MM3_6_7_8_SECURITY (continued) MM3_6_7_8_MS2_ALLOWED_R Read security bits for masters 3, 6, 7, and 8 to slave 2 (eNVM0). If not set, masters 3, 6, 7, and 8 will not have read access to slave 2. MM3_6_7_8_MS1_ALLOWED_W Write security bits for masters 3, 6, 7, and 8 to slave 1 (eSRAM1).
Page 755: M3 Status Register
System Register Block 22.3.75 M3 Status Register Table 732 • M3_SR Reset Number Name Value Description [31:8] Reserved CURRPRI Indicates which priority interrupt, or base boost, is being used now. CURRPRI represents the pre-emption priority, and does not indicate secondary priority. 22.3.76 ETM Count Low Register Table 733 •...
Page 756: Device Status Register
System Register Block 22.3.78 Device Status Register Table 735 • DEVICE_SR Reset Number Name Value Description [31:7] Reserved M3_DEBUG_ENABLE Enables the debug access port (DAP) logic within the Cortex- M3 processor. The reset signal for this bit is SYSRESET_N. The read type is RO-U for this bit. This bit has the following meanings: 0: Debug block of Cortex-M3 is disabled and it is not possible to use a debugger to debug user firmware.
Page 757: Table 736 Envm_Protect_User
System Register Block Table 736 • ENVM_PROTECT_USER (continued) Reset Number Name Value Description NVM1_UPPER_FABRIC_ACCESS When set, indicates that the fabric can access the upper protection region of eNVM1. This is set by the user flash row bit. NVM1_UPPER_M3ACCESS When set, indicates that the Cortex-M3 processor can access the upper protection region of eNVM1.
Page 758: Smart Fusion2 Envm Status Register
0: MPLL is not in lock 1: MPLL is in lock Microsemi recommends that LOCK is only used for test and system status information, and is not used for critical system functions without thorough characterization in the host system. The precision of the LOCK discrimination can be adjusted using the LOCKWIN[2:0] controls.
Page 759: Table 739 Mssddr_Pll_Status
System Register Block Table 739 • MSSDDR_PLL_STATUS (continued) Reset Number Name Value Description FAB_PLL_LOCK If CLK_BASE is generated from a PLL in the fabric, this signal must be connected from the LOCK output of that PLL. When the FACC is going through its PLL initialization stage (either under system controller control or MSS master control), this signal is ANDed with the LOCK output of the MPLL.
Page 760: Ddrb Status Register
System Register Block 22.3.85 DDRB Status Register Table 742 • DDRB_STATUS Reset Number Name Value Description [31:0] DDRB_DEBUG_STATUS Status of the internal ports of DDRBRIDGE. The bit definitions are as follows: Debug ports of the MSS DDR bridge: SYR_DDRB_DP[31:30] = DSG write buffer mode status SYR_DDRB_DP[29:28] = AHB bus write buffer mode status SYR_DDRB_DP[27:26] = HPDMA write buffer mode status SYR_DDRB_DP[25:23] = IDC read buffer mode status...
Page 761: Table 747 Userconfig0
System Register Block 22.3.87 MSS DDR Clock Calibration Status Table 744 • MSSDDR_CLK_CALIB_STATUS Reset Number Name Value Description [31:1] Reserved FAB_CALIB_FAIL 0: The currently selected CCC delay values for the M3_CLK and fabric Clock are such that the FPGA fabric clock calibration circuit is running correctly.
Page 762: Table 749 Userconfig2
System Register Block 22.3.92 User Configuration Register 2 Table 749 • USERCONFIG2 Number Name Reset Value Description [31:0] CONFIG_REG2 Stores the user configuration register 2 to be read by the Cortex-M3 processor. 22.3.93 User Configuration Register 3 Table 750 • USERCONFIG3 Number Name Reset Value Description [31:0]...
Page 763: Fabric Protected Base Address Register
System Register Block Table 752 • Region Size (continued) Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Size Reserved 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB Reserved Reserved Reserved 8 Mbytes Reserved Reserved 22.3.95 Fabric Protected Base Address Register Table 753 •...
Page 764: Mss Gpio Definitions
System Register Block 22.3.96 MSS GPIO Definitions Table 754 • MSS_GPIO_DEF Reset Number Name Value Description [31:4] Reserved MSS_GPIO_31_24_DEF Used to initialize GPIO Bank [31:24] to 0 or 1 after reset. MSS_GPIO_23_16_DEF Used to initialize GPIO Bank [23:16] to 0 or 1 after reset. MSS_GPIO_15_8_DEF Used to initialize GPIO Bank [15:8] to 0 or 1 after reset.
Page 765: Mss Internal Status Register
System Register Block 22.3.98 MSS Internal Status Register Table 756 • MSS_INTERNAL_SR Reset Number Name Value Description [31:7] Reserved DDR_FIC_INT Indicates an interrupt from DDR_FIC. MDDR_ECC_INT Indicates when an SECDED interrupt from the MDDR subsystem is asserted. MDDR_IO_CALIB_INT Interrupt is generated when the MDDR calibration is finished. FAB_PLL_LOCKLOST_INT 0 Indicates that a falling edge event occurred on the FAB_PLL_LOCK signal.
Page 766: Table 757 Mss_External_Sr
System Register Block Table 757 • MSS_EXTERNAL_SR (continued) Reset Number Name Value Description DDRB_LCKOUT Asserted when lock timeout counter reaches its maximum value. Lock time out counter (20-bit) is maintained in the MSS DDR bridge, which starts counting when a locked transfer obtains access to the AXI bus. When the counter reaches maximum value, a DDRB_LCKOUT interrupt is generated and stays asserted until cleared by the processor.
Page 767: Watchdog Timeout Event
System Register Block 22.3.100 Watchdog Timeout Event Table 758 • WDOGTIMEOUTEVENT Reset Number Name Value Description [31:1] Reserved WDOGTIMEOUTEVENT WDOGTIMEOUTEVENT is not affected by SYSRESETN. This allows firmware to determine if a system reset occurred due to a watchdog timeout event. This signal is not used as an interrupt to the Cortex-M3 processor.
Page 768: Table 760 Clr_Edac_Counters
System Register Block Table 760 • CLR_EDAC_COUNTERS (continued) Reset Number Name Value Description MAC_EDAC_RX_CNTCLR_1E 0 Pulse generated to clear the 16-bit counter value in Ethernet MAC Rx RAM corresponding to the count value of EDAC 1-bit errors. This in turn clears the lower 16 bits of the MAC_EDAC_RX_CNT register.
Page 769: Table 761 Flush_Cr
System Register Block Table 761 • FLUSH_CR (continued) Reset Number Name Value Description DDRB_INVALID_SW Allows the read buffer for the high performance master in the MSS DDR bridge to be invalidated. The read buffer is emptied once this pulse is detected. 0: No effect 1: Invalidate AHB Bus read buffer DDRB_INVALID_DS...
Page 770: Iomuxcell_Config[N] Configuration Register
System Register Block 22.3.105 IOMUXCELL_CONFIG[n] Configuration Register Table 763 • IOMUXCELL_CONFIG[n] Reset Number Name Value Description [31:10] Reserved MSS_IOMUXSEL5LOWER[N] 0 Used to select the source of the output port of the I/O cell corresponding to this IOMUXCELL. Each bit of this bus is used together with the corresponding bit of MSS_IOMUXSEL5UPPER and MSS_IOMUXSEL5MID to form a 3-bit field.
Page 771: Table 764 Mss_Iomuxsel5 [N][2:0]
System Register Block 22.3.105.1MSS_IOMUXSEL5[N][2:0] Table 764 • MSS_IOMUXSEL5 [N][2:0] Bit 0 Bit 1 Bit 2 Function Output of I/O cell comes from output of interface Serial Comms of IOMUXCELL Output of I/O cell comes from output of interface MSS GPIO of IOMUXCELL Output of I/O cell comes from output of interface USB Controller of IOMUXCELL Output of I/O cell is connected to '0'...
Page 772: Figure 319 The Fiic Connection To Ahb Bus Matrix
Fabric Interface Interrupt Controller Fabric Interface Interrupt Controller The fabric interface interrupt controller (FIIC) gathers interrupt signals from within the microcontroller subsystem (MSS) and makes them available to the FPGA fabric. There are a number of peripherals and other blocks within the MSS that generate interrupt signals. These interrupt signals are connected to the nested vectored interrupt controller (NVIC) of the Cortex-M3 processor, and can be used as potential interrupt sources to a user logic within the FPGA fabric.
Page 773: Figure 320 Block Diagram For Fabric Interface Interrupt Controller
Fabric Interface Interrupt Controller 23.2 Functional Description This section provides the detailed description of the FIIC subsystem. 23.2.1 Architecture Overview The following figure shows the interfacing of the FIIC with NVIC, MSS peripheral interrupts, and FPGA fabric. The FIIC receives 43 level-sensitive active high interrupts from the MSS as inputs. These MSS peripheral interrupts are combined, in a predetermined fashion, into 16 M2F interrupts (MSS_INT_M2F [15:0]) routed to the fabric.
Page 774: Table 766 Interrupt Line Signal Distribution
Once asserted, user logic in the fabric must keep the interrupt asserted until it is cleared by the Cortex-M3 processor firmware. The SmartFusion2 SoC FPGA FIIC does not synchronize fabric sourced peripheral interrupts to the fabric clock or MSS clock.
Page 775: Figure 322 Configure Fiic In The Mss Configurator
FIIC. The FIIC is not configured by default in the MSS configurator when the Libero SoC project is created. The following steps are required to configure in the Libero SoC. Instantiate the SmartFusion2 MSS component into the Libero project and configure (enable/disable) the peripherals as per the application needs, using the MSS configurator.
Page 776: Figure 323 Fiic Configurator
Fabric Interface Interrupt Controller The following figure shows the FIIC Configurator. Figure 323 • FIIC Configurator Select either or both check boxes per the application need. Use Fabric to MSS Interrupt: Use this option to expose the MSS_INT_F2M interrupt port. MSS_INT_F2M signals are then available to be used in the design.
Page 777: Figure 324 Fabric To The Mss Interrupt
Fabric Interface Interrupt Controller 23.3.2 FIIC Use Models This section explains the use models and gives directions for using the FIIC in an application. 23.3.2.1 Use Model 1: Fabric to MSS Interrupt The following figure shows fabric master/slave connectivity with the FIIC. Select Use Fabric to MSS Interrupt in the Interrupt Management (FIIC) configurator in the Libero SoC.
Page 778: Table 768 Interrupt Source Numbers
Fabric Interface Interrupt Controller FabricIrqX_IRQn represents interrupt source numbers, which are connected to the NVIC of the Cortex-M3 processor in the MSS. The following table gives the interrupt source numbers that corresponds to the fabric to MSS interrupt, MSS_INT_F2M, signals. Table 768 •...
Page 779: Figure 325 Mss To Fabric Interrupt
Fabric Interface Interrupt Controller 23.3.2.2 Use Model 2: MSS to the Fabric Interrupt The following figure shows user logic in the fabric connectivity with the FIIC. You need to select Use MSS to Fabric Interrupt in the Interrupt Management (FIIC) configurator in the Libero SoC. The MSS_INT_M2F signals are then available to be used in the design.
Page 780: Table 769 Bit-Band Register Bit Of Interrupt_Enable0 And Interrupt_Enable1
Fabric Interface Interrupt Controller Table 769 • Bit-Band Register Bit of Interrupt_Enable0 and Interrupt_Enable1 (continued) I2C_INT1_ENBL FAB_PLL_LOCK_INT_ENBL MMUART0_INTR_ENBL FAB_PLL_LOCKLOST_INT_ENBL MMUART1_INTR_ENBL FIC64_INT_ENBL MAC_INT_ENBL RESERVED3[24] USB_MC_INT_ENBL PDMAINTERRUPT_ENBL HPD_XFR_CMP_INT_ENBL TIMER1_INTR_ENBL TIMER2_INTR_ENBL CAN_INTR_ENBL RTC_WAKEUP_INTR_ENBL WDOGWAKEUPINT_ENBL MSSDDR_PLL_LOCKLOST_INT_ENB ENVM_INT0_ENBL ENVM_INT1_ENBL I2C_SMBALERT0_ENBL I2C_SMBSUS0_ENBL I2C_SMBALERT1_ENBL I2C_SMBSUS1_ENBL HPD_XFR_ERR_INT_ENBL MSSDDR_PLL_LOCK_INT_ENBL SW_ERRORINTERRUPT_ENBL DDRB_INTR_ENBL ECCINTR_ENBL...
Page 781: Table 770 Bit-Band Register Bit Of Interrupt_Reason0 And Interrupt_Reason1
Fabric Interface Interrupt Controller The following table gives the bit-band register bit of INTERRUPT_REASON0 and INTERRUPT_REASON1 in the INTERRUPT_CTRL structure. Refer to m2sxxx.h contained in the CMSIS folder. Table 770 • Bit-Band Register Bit of INTERRUPT_REASON0 and INTERRUPT_REASON1 . Bit-Band Register Bit INTERRUPT_REASON0 INTERRUPT_REASON1 SPIINT0_STATUS...
Page 782 Fabric Interface Interrupt Controller Example: The following code illustrates the usage of the MSS to the fabric interrupt in conjunction with the Timer1 interrupt. int main() // STEP 1 - Enable Timer1 MSS to Fabric Interrupt (MSS_INT_M2F[10]) INTERRUPT_CTRL_BITBAND->TIMER1_INTR_ENBL = 1; // STEP 2 - Configure Timer1 in PERIODIC MODE MSS_TIM1_init(MSS_TIMER_PERIODIC_MODE );...
Page 783: Table 771 Smartfusion2 Soc Fpga Fiic Register Map
FPGA fabric. The following table summarizes each of the registers covered by this chapter. The base address of the FIIC block is 0x40006000. Table 771 • SmartFusion2 SoC FPGA FIIC Register Map Address Register...
Page 784: Table 772 Interrupt_Enable0
Fabric Interface Interrupt Controller Table 772 • INTERRUPT_ENABLE0 (continued) Reset Number Name Value Description MMUART0_INTR_ENBL MMUART0_INTR interrupt from the MSS MMUART_0 block to fabric. 1: Enable 0: Mask MMUART1_INTR_ENBL MMUART1_INTR interrupt from the MSS MMUART_1 block to fabric. 1: Enable 0: Mask MAC_INT_ENBL MAC_INT interrupt from the MSS Ethernet MAC block to...
Page 785 Fabric Interface Interrupt Controller Table 772 • INTERRUPT_ENABLE0 (continued) Reset Number Name Value Description MSSDDR_PLL_LOCKLOST_INT MSSDDR_PLL_LOCKLOST_INT interrupt from MPLL to _ENBL the fabric. 1: Enable 0: Mask ENVM_INT0_ENBL ENVM_INT0 interrupt from the MSS ENVM0 block to fabric. 1: Enable 0: Mask ENVM_INT1_ENBL ENVM_INT1 interrupt from MSS ENVM1 block to fabric.
Page 786 CACHE_ERRINTR interrupt from the cache controller block to fabric. 1: Enable 0: Mask The CACHE_ERRINTR interrupt is generated in the SYSREG block by ORing of the following interrupts from the SmartFusion2 SoC FPGA CACHE block: CC_HRESPERRINT0 CC_HRESPERRINT1 CC_HRESPERRINT2 CC_HRESPERRINT3 CC_EDCERRINT...
Page 787: Table 773 Interrupt_Enable1
Fabric Interface Interrupt Controller Table 772 • INTERRUPT_ENABLE0 (continued) Reset Number Name Value Description SOFTINTERRUPT_ENBL SOFTINTERRUPT interrupt from the SYSREG block to fabric. 1: Enable 0: Mask SOFTINTERRUPT is set by the Cortex-M3 processor firmware by writing to the soft interrupt SYSREG block bits.
Page 788: Table 774 Interrupt_Reason1
Fabric Interface Interrupt Controller Table 774 • INTERRUPT_REASON1 (continued) MDDR_IO_CALIB_INT_STATUS Set if the interrupt source for MDDR_IO_CALIB_INT is asserted and the MDDR_IO_CALIB_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE1 is High. Reserved Reserved FAB_PLL_LOCK_INT_STATUS Set if the interrupt source for FAB_PLL_LOCK_INT is asserted and the FAB_PLL_LOCK_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE1 is High.
Page 789: Table 775 Interrupt_Reason0
Fabric Interface Interrupt Controller Table 775 • INTERRUPT_REASON0 (continued) Reset Number Name Value Description HPD_XFR_CMP_INT_STATUS Set if the interrupt source for HPD_XFR_CMP_INT is asserted and the HPD_XFR_CMP_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. TIMER1_INTR_STATUS Set if the interrupt source for TIMER1_INTR is asserted and the TIMER1_INTR_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High.
Page 790: Table 776 Interrupt_Mode
Fabric Interface Interrupt Controller Table 775 • INTERRUPT_REASON0 (continued) Reset Number Name Value Description HPD_XFR_ERR_INT_STATUS Set if the interrupt source for HPD_XFR_ERR_INT is asserted and the HPD_XFR_ERR_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High. MSSDDR_PLL_LOCK_INT_STATUS Set if the interrupt source for MSSDDR_PLL_LOCK_INT is asserted and the MSSDDR_PLL_LOCK_INT_ENBL interrupt enable bit in INTERRUPT_ENABLE0 is High.
Page 791: Figure 326 The Fic Connection To The Ahb Bus Matrix
AHB-Lite to AHB-Lite between the AHB bus matrix and the FPGA fabric. The interface type is configurable. There are up to two, 32-bit FICs in SmartFusion2 devices, referred to as FIC_0 and FIC_1. Both FICs provide two bus interfaces between the MSS and the fabric. The first is mastered by the MSS and has slaves in the fabric;...
Page 792: Figure 327 Fabric Interface Controller Block Diagram
Fabric Interface Controller The following table lists the number of FICs available for use in each device. Table 777 • Number of FICs Available for Use in Each Device Device FIC Blocks M2S005 M2S010 M2S025 M2S050 M2S060 M2S090 M2S150 Only FIC_0 is available. 24.1 Functional Description This following sections provide a detailed description of the FIC subsystem.
Page 793: Mss To The Fpga Fabric Interface
Fabric Interface Controller 24.1.1 MSS to the FPGA Fabric Interface The FIC interface can be configured towards the fabric to support AHB-Lite or APB. FIC configuration allows you to implement AHB-Lite or APB slave user logic in the fabric that can expose the memory map of the Cortex-M3 processor and other masters on the AHB bus matrix.
Page 794: Table 778 Master Group Access To Fabric Slaves
Fabric Interface Controller 24.2.2 Master Identity Port to the Fabric The AHB bus matrix provides a 2-bit side band signal to the FPGA fabric (one 2-bit signal per FIC instance). The side band signal indicates to the slave, which is implemented in the FPGA fabric, the identification of the master performing the current transaction.
Page 795: Figure 328 Fabric Interface Controller Top-Level View
Fabric Interface Controller 24.3 FIC Interface Port List There are two interfaces between the microcontroller subsystem (MSS) and the fabric. One interface allows an AHB-Lite master in the MSS to communicate with AHB-Lite or APB slaves in the fabric.The second interface allows AHB-Lite or APB masters, that are implemented in the fabric, to communicate with AHB-Lite slaves in the MSS, as shown in the following figure.
Page 796: Table 780 Fabric Interface Controller Port List
Fabric Interface Controller The following table contains the FIC port list. Table 780 • Fabric Interface Controller Port List Port Name Direction Description FIC_X_MASTER_ID [1:0] Indicates the current master performing the transfer. Refer to Table 778 on page 760. FIC_X_APB_S_PRDATA [31:0] Indicates APB read data to the fabric master.
Page 797: Figure 329 Ahb-Lite Bus Signals From Fic To The Fabric Slave For A Write Transaction In Bypass Mode
Fabric Interface Controller Table 780 • Fabric Interface Controller Port List (continued) Port Name Direction Description FIC_X_AHB_M_HREADY Indicates that a transfer has completed on the bus. The fabric slave can drive this signal Low to extend a transfer. FIC_X_AHB_M_HWDATA [31:0] Indicates AHB-Lite write data to the fabric slave.
Page 798: Figure 331 Ahb-Lite Bus Signals From Fic To The Fabric Slave For A Write Transaction In Synchronous Pipelined Mode
Fabric Interface Controller The following diagram shows the AHB-Lite bus signals from the fabric interface controller to the fabric slave for write transaction in Synchronous Pipelined mode. Figure 331 • AHB-Lite Bus Signals from FIC to the Fabric Slave for a Write Transaction in Synchronous Pipelined Mode FIC_X_AHB_M_HCLK FIC_X_AHB_M_HADDR[31:0]...
Page 799: Figure 333 Ahb-Lite Bus Signals From Fabric Master To Fic For A Write Transaction In Bypass Mode
Fabric Interface Controller The following diagram shows the AHB-Lite bus signals from the fabric master to the fabric interface controller for write transactions in Bypass mode. Generation of pipelined requests depends on the efficiency of the master in the fabric to generate it. Figure 333 •...
Page 800: Figure 335 Ahb-Lite Bus Signals From Fabric Master To Fic For A Write Transaction In Synchronous Pipelined Mode
Fabric Interface Controller The following diagram shows the AHB-Lite bus signals from the fabric master to the fabric interface controller for write transactions in Synchronous Pipelined mode. Generation of pipelined requests depends on the efficiency of the master in the fabric to generate it. Figure 335 •...
Page 801: Figure 337 Mss Configurator
ASIC blocks in the MSS to generate higher frequency clocks that are aligned with CLK_BASE; the positive edges of CLK_BASE and derived clocks occur at the same time. Refer to the UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide for more details on the alignment of fabric clocks and derived clocks in the MSS.
Page 802: Figure 338 Fic Configurator
Fabric Interface Controller 24.7.1.1 Step 1: Configure the MSS FIC Sub-Block As shown in the following figure, the FIC configurator (applies to both FIC_0 and FIC_1) is organized as follows. In the left panel, the following can be configured: • The MSS to the FPGA fabric interface •...
Page 803: Figure 340 Advanced Options Configuration
Fabric Interface Controller FIC_0_CLK, and FIC_1_CLK must be set to 1:1 when bypass mode is selected. This requirement is enforced in the MSS CCC Configurator when bypass is selected. Figure 340 • Advanced Options Configuration Expose Master Identity Port: Use this option to expose a 2-bit side band signal to the FPGA fabric (one 2-bit signal per FIC instance).
Page 804: Figure 343 Master/Ahb-Lite Memory Space Configuration - 256 Mb Per Slot
Fabric Interface Controller • If more than 16 MB and less than 256 MB of address space is required for any peripheral, select the option shown in the following figure. This mode provides sixteen, 256 MB slots that can be used to connect up to sixteen AHB-Lite slaves.
Page 805 Fabric Interface Controller Connect the subsystem together; this can be done in two ways: Automatic Connection: Right-click in the top-level SmartDesign canvas and select the Auto Con- nect option. This connects the FPGA fabric peripherals to the MSS FIC interfaces through the CoreAHBLite bus and CoreAPB3 bus.
Page 806: Figure 345 Fic Master/Ahb-Lite Subsystem
Fabric Interface Controller Figure 345 • FIC Master/AHB-Lite Subsystem UG0331 User Guide Revision 15.0...
Page 807: Figure 346 Master/Apb Address Configuration
Fabric Interface Controller 24.7.1.2.2 Master/APB Instantiate and configure the CoreAPB3 bus as follows: Select the Address Configuration options, as shown in the following figure. This mode provides sixteen, 16 MB slots that can be used to connect up to sixteen APB compliant slaves. If you need slots with more memory, you can combine multiple slaves to build a larger slot.
Page 808: Figure 348 Fic Master/Apb Subsystem
Fabric Interface Controller Figure 348 • FIC Master/APB Subsystem 24.7.2 Configuring the FIC Subsystem Clocks To create the proper clock configuration and connectivity you must: • Configure the MSS CCC FIC clocks. • Instantiate and configure an FPGA fabric CCC core. •...
Page 809: Figure 349 Clocking Scheme For Synchronous Communication Between The Mss And The Fpga Fabric
Fabric Interface Controller The SmartFusion2 architecture imposes the following rules that must be followed for synchronous communication between the MSS and the FPGA fabric FIC subsystems. The following figure illustrates these rules. • Each FPGA fabric FIC subsystem must be driven by a clock whose frequency matches the frequency defined, for that particular subsystem, in the MSS_CCC configurator.
Page 810: Figure 350 Mss Ccc Fic Clock Configuration
(MSS_CCC), as shown in the following figure. Figure 350 • MSS CCC FIC Clock Configuration Note that the CLK_BASE field is non-editable. CLK_BASE frequency, as imposed by the SmartFusion2 architecture, must be the minimum frequency of all FIC clock frequencies and is automatically computed by the MSS CCC configurator.
Page 811: Figure 351 Fabric Clocks Configuration
Typically a global output (GLx) must be associated with each of the FIC clocks must be associated and a frequency specified for each output matching the frequencies defined in the MSS_CCC configurator. Microsemi recommends generating all the global outputs from a fabric PLL to guarantee the phase alignment (as shown in Figure 351, page 777).
Page 812: Figure 352 Configure The Mss Reset Sub-Block
Fabric Interface Controller 24.7.2.6 Step 6: Timing Analysis Requirements Post-layout static timing analysis must be performed to make sure that the design meets the frequency requirements defined in MSS_CCC and the fabric CCC configurator. M3_CLK may need to be changed or clock ratio between M3_CLK and the FIC clocks increased to get a design that passes the static timing analysis.
Page 813: Figure 353 Ahb-Lite Slaves In The Fpga Fabric Connected To The Mss Master
The FIC allows four possible communication scenarios that are described in the following sections. Microsemi provides numerous AHB and APB v 3.0 compliant cores in the Libero SoC IP catalog for easy instantiation into the FPGA fabric. You must instantiate CoreAHBLite and CoreAPB3 soft IP into the fabric to allow further instantiation of soft AHB-Lite and APB masters and slaves.
Page 814: Figure 354 Apb Slaves In The Fpga Fabric Connected To The Mss
APB Slave 0 APB Slave 2 The following application note describes this Use Model with a design example: AC392: SmartFusion2 SoC FPGA SRAM Initialization from eNVM. The design example describes a method of initializing the fabric SRAM blocks after power-up with the initialization data from eNVM block using the Cortex-M3 processor as master.
Page 815: Figure 355 Fpga System With The Mss Slave And The Fabric Master
CoreAHBLite AHB-Lite Master The following application note describes this Use Model with a design example: AC388: SmartFusion2 SoC FPGA Dynamic Configuration of AHB Bus Matrix. The design example consists of two AHB masters in FPGA fabric that write 32-bit data to the AHB bus matrix slave eSRAM1.
Page 816: Figure 356 Fabric Apb Master With Mss As Slave
Tutorial: This tutorial shows you how to interface and handle communication between the user logic in the FPGA fabric and the MSS. It also explains the Libero SoC design software tool flow used for designing applications for the SmartFusion2 SoC FPGA family of devices.
Page 817: Table 782 Fab_If Register In The Sysreg Block
Fabric Interface Controller 24.9 SYSREG Control Registers for FIC_0 and FIC_1 Refer to the "System Register Block" section on page 670 for a detailed description of each register and bit. The following table lists the control registers for FIC_0 and FIC_1 from the SYSREG block. Table 782 •...
Page 818: Figure 357 Apb Configuration Interface And Subsystems Connectivity With Mss Master
AMBA APB3 protocol specification. 25.1 Functional Block Diagram Description This section provides the detailed description of the FIC_2 (APB configuration bus) subsystem. Figure 357 • APB Configuration Interface and Subsystems Connectivity with MSS Master SmartFusion2 SoC FPGA Cortex-M3 Processor LPDDR DDR 2...
Page 819: Table 783 Fddr Apb Slave Configuration Interface Port List
• Refer to the "Serializer/Deserializer" chapter of the UG0447: SmartFusion2 and IGLOO2 FPGA High Speed Serial Interfaces User Guide for SERDES register map details and address space partition. The base address of the MDDR configuration address space resides at 0x40020000 and extends to address 0x400203FF in the memory map of the Cortex-M3 processor on the AHB bus matrix.
Page 820: Table 785 Serderif Apb Slave Configuration Interface Port List
25.1.3 CoreSF2Config Soft IP CoreSF2Config facilitates configuration of peripheral blocks (MDDR, FDDR, and SERDESIF blocks) in a SmartFusion2 device, as shown in Figure 358, page 787. CoreSF2Config has a mirrored master APB port and several mirrored slave APB ports. The mirrored master port should be connected to the FIC_2_APB_MASTER port of the MSS and the mirrored slave ports should be connected to the APB slave ports of the blocks to be configured.
Page 821: Figure 358 Configure Fic_2 In Mss Configurator
FIC_2. The FIC_2 is not configured by default in the MSS configurator when the Libero SoC project is created. The following steps are required. 25.2.1.1 Step 1 Instantiate the SmartFusion2 MSS component into the Libero project and configure (enable/disable) the peripherals using MSS configurator, as required. 25.2.1.2 Step 2 Double-click FIC_2 (Peripheral Initialization) or right-click FIC_2 and select Configure, as shown in the following figure.
Page 822: Figure 359 Fic_2 Configurator
APB Configuration Interface The following figure shows the FIC_2 configurator. Figure 359 • FIC_2 Configurator 25.2.1.3 Step 3 Select either or both check boxes as required. If MSS DDR is selected, the FIC_2 Configurator shows the graphical illustration of the connectivity between the FIC_2 APB master and MSS DDR APB slave through CoreSF2Config, as shown in the following figure.
Page 823: Figure 361 Fic_2 Configuration For Mss Ddr, Fddr, And Serdes
APB Configuration Interface CoreSF2Config must be instantiated in SmartDesign.connections made as illustrated in FIC_2 configurator. The following figure shows the connectivity between APB configuration interfaces of the SERDES and DDR subsystems (both are selected). Figure 361 • FIC_2 Configuration for MSS DDR, FDDR, and SERDES If System Builder is used for creating the design, CoreSF2Config is Instantiated and connections are made automatically.
Page 824: Figure 362 Mss Ddr Design With Apb Configuration Interface
INIT_DONE) that are connected to CoreSF2Reset. CoreSF2Reset handles sequencing of reset signals in SmartFusion2 devices. It is particularly concerned with resets related to peripheral blocks (MDDR, FDDR, and SERDESIF blocks). CoreSF2Reset soft IP is available in the Libero SoC IP catalog. Refer to the CoreSF2Reset Handbook for port lists, port descriptions, and design flow.
Page 825: Figure 363 Top-Level Components With Apb Configuration Interface Signals
APB Configuration Interface 25.2.2.2 Use Model 2: Configuring SERDES • Select Use System Builder while creating a new project from the Design Templates and Creators panel in Libero SoC. • Select SERDESIF_0 in the System builder - Device Features GUI. Follow the rest of the steps with default settings and generate the design.
Page 826: Figure 365 Edac In Write Mode
When the word is read, the checksum bits are utilized to determine whether one or more bits are in error. If the error is a single-bit error, checksum bits determine which bit contains the error. EDAC algorithms implemented in SmartFusion2 SOC devices are designed to detect all two-bit errors and correct all single-bit errors within a single word.
Page 827: Table 787 Minimum Number Of Checksum Bits Required Data
USB internal memory: Universal Serial Bus OTG Controller • Internal RAM of the CAN controller: CAN Controller • eNVM: Embedded Nonvolatile Memory (eNVM) Controllers In the UG0446: SmartFusion2 and IGLOO2 FPGA High Speed DDR Interfaces User Guide, refer to the following chapters: • MDDR: MDDR Subsystem •...
Page 828: Figure 367 Edac In Read Mode (Reading From Memory)
Error Detection and Correction Controllers 26.3 How to Use EDAC EDAC can be configured using the SECDED configurator available in the SmartFusion2 SOC, as shown in the following figure. Using the SECDED configurator, EDAC options for the following memories can be configured: •...
Page 829: Figure 368 Edac In Read Mode (Reading From Memory)
Error Detection and Correction Controllers • Enable MDDR ECC Interrupt: Enable MDDR ECC Interrupt can be used to enable the MSS DDR (MDDR) ECC interrupts. Figure 368 • EDAC in Read Mode (Reading From Memory) The values entered in the configurator will be exported into the programming files for programming the flash bits that control the EDAC functionality.

Microsemi SmartFusion2 User Manual

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Cortex-M3 Processor Overview and Debug Features

Cortex-M3 Processor (Reference Material)

Cache Controller

Embedded NVM (Envm) Controllers

Embedded SRAM (Esram) Controllers

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