Microsemi SmartFusion2 Demo Manual
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Microsemi SmartFusion2 Demo Manual

Soc fpga error detection and correction of esram memory - libero soc v11.8 sp1
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Download this manual See also: Configuration Manual, Demo Manual
DG0388
Demo Guide
SmartFusion2 SoC FPGA Error Detection and
Correction of eSRAM Memory - Libero SoC v11.8 SP1

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Summary of Contents for Microsemi SmartFusion2

  • Page 1 DG0388 Demo Guide SmartFusion2 SoC FPGA Error Detection and Correction of eSRAM Memory - Libero SoC v11.8 SP1...
  • Page 2 Within the USA: +1 (800) 713-4113 with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this...

  • Page 3: Table Of Contents

    Revision 1.0 ............... 1 2 SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory . . . 2 Introduction .
  • Page 4 SmartFusion2 Security Evaluation Kit Board Setup ........
  • Page 5 SmartFusion2 Security Evaluation Kit Jumper Settings ........

  • Page 6: Revision History

    Revision History Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the current publication. Revision 10.0 Updated the document for Libero SoC v11.8 SP1 software release. Revision 9.0 Updated the document for Libero SoC v11.8 software release.

  • Page 7: Smartfusion2 Soc Fpga - Error Detection And Correction Of Esram Memory

    (SECDED). All memories within the microcontroller subsystem (MSS) of the SmartFusion2 are protected by SECDED. The eSRAM memory can be eSRAM_0 or eSRAM_1. The address range of eSRAM_0 is 0x20000000 to 0x20007FFF and the address range of eSRAM_1 is 0x20008000 to 0x2000FFFF.

  • Page 8: Demo Requirements

    Host PC Drivers USB to UART drivers For launching demo GUI Microsoft.NET Framework 4 client 2.2.1 Design Files The demo design files are available for download from the following path in the Microsemi website: http://soc.microsemi.com/download/rsc/?f=m2s_dg0388_liberov11p8_sp1_df Design files include: • Libero •...

  • Page 9: Demo Design Description

    2.3.1 Loop Test Loop Test is executed when the SmartFusion2 receives a loop test command from the GUI. Initially, all the error counters and EDAC related registers are placed in the RESET state. The following steps are executed for each iteration: Enable the EDAC controller.

  • Page 10: Figure 3 Design Flow

    SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory The following figure shows the eSRAM EDAC demo operations. Figure 3 • Design Flow Messages from Reset UART Rx Interrupt Initialize the application Receive UART messages and decode as...

  • Page 11: Running The Demo

    Connect the FlashPro4 programmer to the J5 connector of SmartFusion2 Security Evaluation Kit board. Connect one end of the USB mini-B cable to the J18 connector provided in the SmartFusion2 Security Evaluation Kit board. Connect the other end of the USB cable to the host PC. Ensure that...

  • Page 12: Graphical User Interface

    SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory The following figure shows the board setup for running the demo on the SmartFusion2 Security Evaluation Kit. Figure 5 • SmartFusion2 Security Evaluation Kit Board Setup 2.4.2 Graphical User Interface The following section describes about eSRAM - EDAC demo GUI.

  • Page 13: Running The Design

    SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory Figure 6 • eSRAM – EDAC Demo GUI The GUI supports the following features: Selection of COM port and Baud Rate. Selection of 1-bit error correction tab or 2-bit error detection tab.

  • Page 14: Figure 7 Flashpro Programming Window

    SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory Figure 7 • FlashPro Programming Window Press SW6 switch to reset the board after successful programming. Launch the EDAC_eSRAM Demo GUI executable file available in the design files (\GUI Executable\ EDAC_eSRAM.exe).

  • Page 15: Figure 8 1-Bit Error Correction Tab

    Click Loop Test ON. It runs in loop mode where continuous correction and detection of errors is done. The loop runs for 200 iterations. All actions performed in SmartFusion2 are logged in the Serial Console section of the GUI. The 2-bit error detection loop test prints the error affected eSRAM address offset in Serial Console.

  • Page 16: Conclusion

    SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory Figure 9 • 2-Bit Error Detection Tab Conclusion This demo shows SmartFusion2 SECDED capabilities of the eSRAM. DG0388 Demo Guide Revision 10.0...

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