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IGLOO2 FPGA DSP FIR Filter
Microsemi IGLOO2 FPGA DSP FIR Filter Manuals
Manuals and User Guides for Microsemi IGLOO2 FPGA DSP FIR Filter. We have
6
Microsemi IGLOO2 FPGA DSP FIR Filter manuals available for free PDF download: Application Note, User Manual, Demo Manual, Manual
Microsemi IGLOO2 FPGA DSP FIR Filter Application Note (102 pages)
Board and Layout Design Guidelines for SoC and FPGAs
Brand:
Microsemi
| Category:
Power Tool
| Size: 10 MB
Table of Contents
Table of Contents
3
1 Revision History
9
Revision 14.0
9
Revision 13.0
9
Revision 12.0
9
Revision 11.0
9
Revision 10.0
10
Revision 9.0
10
Revision 8.0
10
Revision 7.0
10
Revision 6.0
10
Revision 5.0
11
Revision 4.0
11
Revision 3.0
11
Revision 2.0
11
Revision 1.0
11
Revision 0
11
2 Board Design Guidelines for Smartfusion2 Soc and IGLOO2 Fpgas
12
Design Considerations
12
Power Supplies
12
Figure 1 Power Supplies
13
Power Supply Decoupling
14
Table 1 Device-Package Combinations Without Serdes_X_Vdd Pin
14
Figure 2 Impedance of Three Capacitors in Parallel
15
Table 2 Power Supply Decoupling Capacitors
15
Power Supply Sequencing
17
I/O Glitch
17
I/O Glitch During Power-Up
17
Table 3 Recommended Capacitors
17
I/O Glitch During Power-Down
19
Table 4 I/O Glitch During Power-Up
19
Table 5 I/O Glitch During Power-Down
19
I/O Glitch in a Blank Device
20
Power Supply Flow
20
Unused Pin Configurations
21
Figure 3 Example Power Supply Topology
21
Figure 4 Recommendations for Unused Pin Configurations
22
Table 6 Recommendation for Bank Supplies for FC1152, FG896, FG676, FCS536, FCV484 Packages
23
Table 7 Recommendation for Bank Supplies for FG484 Package
24
Table 8 Recommendation for Bank Supplies for VF400 and FCS325 Packages
24
Limiting Surge Current During Device Reset
25
Table 9 Recommendation for Bank Supplies for VF256 and TQ144 Packages
25
Table 10 Surge Current on VDD During DEVRST_N Assertion (no Decoupling Capacitors on Board)
26
Table 11 M2S090 and M2S150 Surge Current During DEVRST_N Assertion (with Decoupling Capacitors on Board)
26
Clocks
27
Main Crystal Oscillator
27
Table 12 Surge Current on VDD During Digest Check Using System Services
27
Table 13 Clock Circuit
27
Figure 5 Crystal Oscillator
28
Table 14 Crystal Oscillator Output Frequency Range
28
Auxiliary (RTC) Crystal Oscillator
29
Reset Circuit
29
Figure 6 RC Time Constant
29
Figure 7 RC Oscillator
29
Figure 8 Reset Circuit
30
Figure 9 Without Reset Circuit
30
Figure 10 Fabric Logic Reset
30
Device Programming
31
JTAG Programming
31
Table 15 JTAG Pins
31
SPI Master Programming
32
Figure 11 JTAG Programming
32
Figure 12 SPI Master Mode Programming
33
Table 16 Dedicated Pins
33
SPI Slave Programming
34
Serdes
34
Figure 13 SPI Slave Programming by External Microprocessor
34
Figure 14 SPI Slave Programming by External Programmer
34
AC Coupling
35
Figure 15 Serdes Schematics
35
PCI Express (Pcie)
35
PLL Filter
36
Serdes Reference Clock Requirements
36
LPDDR, DDR2, and DDR3
36
MDDR/FDDR Impedance Calibration
37
Table 17 LPDDR/DDR2/DDR3 Parameters
37
VREF Power
38
VTT Power
38
LPDDR and DDR2 Design
38
Figure 16 VREF Generation
38
Figure 17 LPDDR Interface
39
DDR3 Guidelines
40
Figure 18 DDR2 Interface
40
Figure 19 8-Bit DDR3 Interface
41
Figure 20 16-Bit DDR3 Interface
41
User I/O and Clock Pins
42
Internal Clamp Diode Circuitry
42
Figure 21 Internal Clamp Diode Control Circuitry
42
Table 18 Recommendations for Unused I/O and Clock Pins
42
Obtaining a Two-Rail Design for Non-Serdes Applications
43
Operating Voltage Rails
43
Table 19 Operating Voltage Rails
43
Configuring Pins in Open Drain
44
Brownout Detection (BOD)
44
Figure 22 Configuring Pins in Open Drain
44
Table 20 Truth Table
44
Simultaneous Switching Noise
45
Figure 23 BOD Circuit Implementation
45
3 Layout Guidelines for Smartfusion2- and IGLOO2-Based Board Design
46
Power Supply
46
Core Supply (VDD)
47
Component Placement
47
Figure 24 Placement of Capacitors for VDD Plane
47
Plane Layout
48
Simulations
48
Figure 25 Capacitor Placement under BGA Vias
48
Figure 26 VDD Plane
48
Serdes
49
Component Placement
49
Figure 27 Impedance Profile of VDD Plane with Respect to Frequency
49
Figure 28 Filter Circuit for Serdes PLL Power Supply
50
Figure 29 Component between 1.2 K Resistor and K6 Pin
50
Plane Layout
51
Figure 30 Layout for Serdes_X_Vdd Plane
51
Figure 31 Layout of Serdes_X_Vddaio Plane
51
Simulations
52
Figure 32 Layout of SERDES_1_L01_VDDAPLL and SERDES_1_L01_REFRET
52
Figure 33 Impedance Profile of Serdes_X_Vdd Plane over Frequency Range
53
Figure 34 Impedance Profile of Serdes_X_Vddaio Plane over Frequency Range
53
Ddr
54
Component Placement
54
Plane Layout
54
Figure 35 Layout of VREF5
55
Figure 36 Layout of VDDIO0 Plane
55
Simulations
56
Figure 37 Layout of VDDIO5 Plane
56
Figure 38 Impedance Profile of VDDIO0 Plane over Frequency Range
57
Figure 39 Impedance Profile of VDDIO5 Plane over Frequency Range
57
Pll
58
Component Placement
58
Figure 40 Filter Circuit for PLL
58
Figure 41 Placement of Capacitors for PLL Filter Circuit
58
Plane Layout
59
Simulations
59
Figure 42 Routing for PLL Filter Circuit
59
I/O Power Supply
60
Component Placement
60
Plane Layout
60
Figure 43 PLL0VDDA Plane Impedance
60
Simulations
61
Figure 44 Impedance Profile of VDDIO1 Plane over Frequency Range
61
Figure 45 Impedance Profile of VDDIO2 Plane over Frequency Range
61
Programming Power Supply (VPP or VCCENVM)
62
Component Placement
62
Plane Layout
62
Simulations
62
Figure 46 Impedance Profile of VPP Plane over Frequency Range
62
High-Speed Serial Link (Serdes)
63
Layout Considerations
63
Figure 47 Skew Matching
63
Figure 48 Example of Asymmetric and Symmetric Differential Pairs Structure
63
Via
64
Figure 49 Zig-Zag Routing
64
Figure 50 Ground Planes for Reference
64
Figure 51 Via Illustration
65
Figure 52 Non-Functional Pads of Via
65
DC Blocking Capacitors
66
Connectors
66
Figure 53 Via-To-Via Pitch
66
Figure 54 GND Via or Return Via
66
Figure 55 Capacitor Pad Reference Plane
66
Considerations for Simulation
67
Step 1: Gathering the Required Files
67
Step 2: Creating Simulation Topology
67
Step 3: Configuration of AMI Model
68
Figure 56 Typical Topology for SLA Simulation
68
Figure 57 Block Diagram of the 3-Tap Feed Forward Equalizer
68
Step 4: Results
69
Figure 58 Continuous Time Linear Equalization Response
69
Figure 59 Expected Results from Simulations (Eye Diagram, Eye Contour, and Bath Tub Curve)
70
Figure 60 Eye Mask for Pcie 2.0
70
Table 21 Specifications of the Received Signal for Pcie
70
DDR3 Layout Guidelines
71
Placement
71
Routing
71
Figure 61 DDR3 Memories
71
Table 22 Grouping of DDR3 Signals
71
Simulation Considerations
73
Figure 62 TMATCH Signals (Example Layout)
73
Figure 63 DDR3 Simulation Topology
74
Figure 64 List of Reports Generated by Hyperlynx
75
Figure 65 Setup and Time Margins of DQ0
75
References
76
Figure 66 Setup and Time Margins for DQ and DQS Signals
76
4 Creating Schematic Symbols Using Cadence Orcad Capture CIS for Smartfusion2 and IGLOO2 Designs
77
Creating Schematic Symbols Using Pin Assignment Tables (PAT)
77
Preparing the PAT Layout File for Import into Orcad Capture
77
Figure 67 Example PAT Spreadsheet - Initial View
77
Figure 68 Example PAT Spreadsheet - Editing Stage
78
Figure 69 Example PAT Spreadsheet - Final Stage
79
Generating a Orcad Capture Schematic Symbol
80
Figure 70 New Part Creation Spreadsheet Dialog
80
Figure 71 Example PAT Spreadsheet - Final Stage
81
Figure 72 New Part Creation Spreadsheet Dialog with Data
82
Figure 73 New Part Created in the Library
82
Figure 74 Schematic Symbol - First Section
83
Figure 75 Package View of the Schematic Symbol
83
Creating Schematic Symbols with User Defined Pin Names
84
Exporting Pin Information from the Libero Design
84
Figure 76 Modifying Port Names
84
Figure 77 I/O Constraints
84
Figure 78 I/O Editor
85
Figure 79 Exporting Pin Information from Libero
85
Preparing the Pin List for Import into Orcad Capture CIS
86
Figure 80 Importing Pin Names to the Spreadsheet
86
Figure 81 Importing Pin Names to the Spreadsheet-Step 1
86
Figure 82 Importing Pin Names to the Spreadsheet-Step 2
87
Figure 83 Importing Pin Names to the Spreadsheet-Final Step
87
Figure 84 Spreadsheet with the Pin Names Imported
88
Generating a Capture Schematic Symbol
89
Figure 85 Final Example Spreadsheet to be Imported into Orcad Capture
89
5 Board Design and Layout Checklist
90
Prerequisites
90
Design Checklist
90
Table 23 Design Checklist
90
Layout Checklist
97
Table 24 Layout Checklist
97
6 Appendix: Special Layout Guidelines - Crystal Oscillator
98
Figure 86 Layout of the Crystal Oscillator
98
Figure 87 Schematics of Crystal Oscillator
98
7 Appendix: Stack-Up
99
Figure 88 Stack-Up Used in Development Board
100
8 Appendix: Dielectric Material
101
Figure 89 Fiberglass Weaving
101
9 Appendix: Power Integrity Simulation Topology
102
Figure 90 Power Integrity Simulation Topology
102
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Microsemi IGLOO2 FPGA DSP FIR Filter User Manual (50 pages)
Programming
Brand:
Microsemi
| Category:
Microcontrollers
| Size: 2 MB
Table of Contents
Table of Contents
3
1 Revision History
7
Revision 4.0
7
Revision 3.0
7
Revision 2.0
8
Revision 1.0
8
Revision 0
8
Smartfusion2 List of Changes Table for Reference
8
2 Programming Overview
9
Table 1 Smartfusion2 and IGLOO2 Programming Modes (Except M2S/M2GL050 Device)
9
Table 2 M2S/M2GL050 Programming Modes
12
Programming Interface
13
Table 3 Available Programming Interfaces
13
Programming Bitstream Generation
14
Table 4 State of Programming Interface During Reset
14
Figure 1 Libero Soc Programming Bitstream Generation Flow
15
Programming Bitstream
15
Table 5 Programming Bitstream Size (All Variations T/S/TS)
16
Programming Flow
17
3 JTAG Programming
18
Programming Interface Overview
18
Table 6 JTAG Pin Names and Description
18
Figure 2 JTAG Signals Timing Diagram
19
JTAG Timing Diagram
19
Design Implementation
20
Figure 3 JTAG Programming Mode
20
Programming Using an External Programmer
21
Power Supply Requirements for Programming
21
Figure 4 Programming Microsemi Devices in a JTAG Chain
21
Figure 5 JTAG Programming Using External Programmer
21
Figure 6 JTAG Programming of a Smartfusion2 Device
22
Programming Using an External Microprocessor
23
Figure 7 Programming Using an External Microprocessor
23
4 SPI Slave Programming
24
Programming Interface Overview
24
Design Implementation
24
Table 7 Dedicated SC_SPI Pins
24
Figure 8 SPI Slave Programming by External Microprocessor
25
Figure 9 SPI Slave Programming by External Programmer
25
5 Auto Programming
26
Programming Interface Overview
26
Design Implementation
26
Table 8 MSS/HPMS SPI_0 Signals
26
Figure 10 Smartfusion2/Igloo2 MSS/HPMS SPI_0 Port Configured for Auto Programming (Except 050 Device)
27
Auto Programming of M2S/M2GL050 Device
28
Figure 11 Timing Relationship of Reset and FLASH_GOLDEN_N Pin
28
Figure 12 Auto Programming Scheme for M2S/M2GL050 Devices
28
6 MSS ISP (Smartfusion2 Only)
29
Design Implementation
29
Figure 13 MSS ISP Update Process
30
Table 9 ISP Programming Service Request
30
Table 10 ISP Programming Options
30
Table 11 ISP Programming Modes
30
Table 12 ISP Responses
31
Table 13 ISP Programming Service Status Codes
31
Figure 14 MSS ISP Update Flow
32
7 In-Application Programming
34
Figure 15 IGLOO2 In-Application Programming Interface
34
Design Implementation
35
Authenticate
35
Verify
35
Program
36
Figure 16 Smartfusion2 In-Application Programming
36
Table 14 IAP Service Requests
37
Table 15 IAP Programming Options
37
Table 16 IAP Programming Modes
37
Table 17 IAP Service Responses
37
Table 18 IAP Programming Service Status Codes
37
Table 19 Error Codes
38
Table 20 IAP Bitstream Authorization Error Codes
38
Figure 17 IAP Flow
39
8 Auto Update
40
Figure 18 Auto Update Programming Ports
40
Configuring the Device for Auto Update
41
Figure 19 Enabling Auto Update
41
9 Programming Recovery
42
Programming Recovery Implementation
42
Figure 20 Enabling Programming Recovery
43
Table 21 Programming Recovery Configuration Settings (UCNFG[16:12])
43
SPI Flash Configuration and Image Selection
44
MSS/HPMS SPI_0 Port Configuration
44
Table 22 SPI Directory
44
Table 23 User Lock Row Strobe Bits for Programming Recovery
44
Table 24 SPI Signal Polarity Modes
44
Figure 21 Programming Recovery Configuration for Smartfusion2
45
Table 25 Programming Recovery and Auto Update Truth Table
45
10 Production Programming
46
11 State of Smartfusion2 and IGLOO2 Components During Programming
47
Table 26 ASIC Block and I/O State During Programming
47
Figure 22 I/O States During JTAG Programming
49
Table 27 ASIC Block and I/O State During Programming Recovery/Auto Update
49
Figure 23 Setting I/O States
50
Use of Flash Freeze Mechanism in Device Programming
50
Microsemi IGLOO2 FPGA DSP FIR Filter Demo Manual (36 pages)
Libero SoC v11.7
Brand:
Microsemi
| Category:
Motherboard
| Size: 2 MB
Table of Contents
Table of Contents
2
1 Preface
5
Purpose
5
Intended Audience
5
References
5
2 IGLOO2 FPGA DSP FIR Filter
6
Introduction
6
Figure 1. Top-Level Diagram of DSP FIR Filter Demo
6
Design Requirements
7
Demo Design
7
Introduction
7
Figure 2. Demo Design Files Top-Level Structure
7
Table 1. Design Requirements
7
Demo Design Description
8
Data Handle
8
Filter Control
8
Figure 3. DSP FIR Filter Demo Design Block Diagram
8
Tpsram Ip
9
Coreuart
9
Corefir
9
Corefft
9
Table 2. TPSRAM Configuration for Data Buffers
9
Sysreset
10
Osc
10
CCC
10
Setting up the Demo Design
10
Table 3. IGLOO2 FPGA Evaluation Kit Jumper Settings
10
Figure 4. IGLOO2 Evaluation Kit DSP FIR Filter Demo Setup
11
Figure 5. USB to UART Bridge Drivers
12
Programming the Demo Design
13
Figure 6. Flashpro - New Project
13
Figure 7. Flashpro Project Configuration
14
Programming the Device
14
Setting up the Device
14
Figure 8. Flashpro Project RUN Passed
15
DSP FIR Demo GUI
16
Figure 9. DSP FIR Demo Window
16
Running the Demo Design
17
Figure 10. Serial Port Configuration
17
Figure 11. Filter Generation - 1
18
Figure 12. Filter Generation - 2
19
Figure 13. Filter Response and Filter Coefficient Plot
20
Figure 14. Signal Generation
21
Figure 15. Input Signal and Input Signal FFT Plot
22
Figure 16. DSP FIR Filter Demo - Start
23
Figure 17. Filtered Signal: Time and Frequency Plot
24
Figure 18. Filtered Signal: GUI Options
25
Figure 19. Text Viewer
26
Figure 20. Text Viewer: Filter Coefficient Values
27
Figure 21. Text Viewer: Coefficients Save Options
28
Conclusion
29
Figure 22. FIR Filter Demo: Exit
29
3 Appendix: Smartdesign Implementation
30
Figure 23. DSP FIR Filter Smartdesign
30
Table 4. DSP FIR Filter Demo Smartdesign Blocks and Description
30
4 Appendix: Resource Usage Summary
31
Table 5. DSP FIR Filter Demo Resource Usage Summary
31
Table 6. MACC Blocks Usage Summary
31
Table 7. Ram1Kx18 Blocks Usage Summary
31
5 Appendix: Coefficient Text File Format
32
Figure 24. Coefficient File Example - 9 Taps, Decimal Values
32
6 Revision History
33
7 Product Support
34
Customer Service
34
Customer Technical Support Center
34
Technical Support
34
Website
34
Contacting the Customer Technical Support Center
34
Email
34
My Cases
34
Outside the U.S
35
ITAR Technical Support
35
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Microsemi IGLOO2 FPGA DSP FIR Filter User Manual (64 pages)
FPGA Evaluation Kit
Brand:
Microsemi
| Category:
Microcontrollers
| Size: 1 MB
Table of Contents
Table of Contents
3
1 Introduction
5
Kit Contents
5
IGLOO2 FPGA Evaluation Kit Web Resources
5
Board Description
5
2 Installation and Settings
9
Software Installation
9
Hardware Installation
9
IGLOO2 Power Sources
11
Testing the Hardware
11
3 Key Components Description and Operation
13
Powering up the Board
13
Current Measurement
13
Memory Interface
15
SERDES0 Interface
16
USB Interface
18
Marvell PHY (88E1340S)
18
Programming
20
FTDI Interface
20
I2C Port Header
21
System Reset
22
Clock Oscillator
22
Debugging
23
GPIO Header Pin out
25
4 Pin List
27
5 Board Components Placement
41
6 Demo Design
45
M2GL-EVAL-KIT Board Demo Design
45
7 Manufacturing Test
47
M2GL-EVAL-KIT Board Testing Procedures
47
Switches and LED Tests
58
Debugging the Board
58
List of Changes
60
Product Support
61
ITAR Technical Support
62
Microsemi IGLOO2 FPGA DSP FIR Filter User Manual (27 pages)
FPGA System Services Simulation
Brand:
Microsemi
| Category:
Microcontrollers
| Size: 2 MB
Table of Contents
Table of Contents
2
1 Revision History
4
Revision 1.0
4
Types of Available System Services
6
IGLOO2 System Service Simulation
6
Smartfusion2 System Service Simulation
7
Simulation Examples
8
IGLOO2 Serial Number Service Simulation
8
Smartfusion2 Serial Number Service Simulation
11
IGLOO2 Zeroization Service Simulation
16
Smartfusion2 Zeroization Service Simulation
19
3 Appendix: Types of System Services
22
Simulation Message Services
22
Flash*Freeze
22
Zeroization
22
Data Pointer Services
22
Serial Number
22
Usercode
22
Data Descriptor Services
22
Aes
23
Sha 256
23
Hmac
23
DRBG Generate
23
DRBG Reset
23
DRBG Self Test
24
DRBG Instantiate
24
DRBG Uninstantiate
24
DRBG Reseed
24
Keytree
24
Challenge Response
24
Other Services
25
Digest Check
25
Unrecognized Command Response
25
Unsupported Services
25
System Services Simulation Support File
25
Forcing Error Responses
25
Parameter Setting
26
Microsemi IGLOO2 FPGA DSP FIR Filter Manual (15 pages)
Hard Multiplier Accumulator Configuration
Brand:
Microsemi
| Category:
Power Tool
| Size: 1 MB
Table of Contents
Table of Contents
2
Introduction
3
Key Features
3
1 Smartdesign
5
2 Core Parameters
7
3 Port Description
10
A Product Support
14
Customer Service
14
Customer Technical Support Center
14
Technical Support
14
Website
14
Contacting the Customer Technical Support Center
14
ITAR Technical Support
15
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