Microsemi SmartFusion2 User Manual
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Microsemi SmartFusion2 User Manual

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UG0445
User Guide
SmartFusion2 SoC FPGA and IGLOO2 FPGA Fabric

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Summary of Contents for Microsemi SmartFusion2

  • Page 1 UG0445 User Guide SmartFusion2 SoC FPGA and IGLOO2 FPGA Fabric...
  • Page 2 “as is, where is” and with all faults, and the entire risk associated with such information is entirely Within the USA: +1 (800) 713-4113 with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP Outside the USA: +1 (949) 380-6100 rights, whether with regard to such information itself or anything described by such information.

  • Page 3: Table Of Contents

    Operating Modes ..............44 Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 4 5 V Output Driving Compatibility ..........107 6.14 I/Os in Conjunction with Fabric, MDDR/FDDR, and MSS/HPMS Peripherals ....107 Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 5 Terminology ..............114 Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 6 Figures Figure 1 SmartFusion2/IGLOO2 Fabric Architecture for M2S050/M2GL050 ......4 Figure 2 Functional Block Diagram of Logic Element ......... . . 5 Figure 3 Functional Block Diagram of MSIO .
  • Page 7 Chip Level Resets From Device Reset ..........110 Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 8 SmartFusion2 and IGLOO2 Math Blocks Resource ........
  • Page 9 SmartFusion2 and IGLOO2 I/O Features ........

  • Page 10: Revision History

    Revision 3.0 The following is a summary of the changes in revision 3.0 of this document. • Merged the SmartFusion2 SoC and IGLOO2 FPGA Fabric user guide. • Removed all instances of and references to M2GL100 device from Table 1,...

  • Page 11: Revision 2.0

    105. For more information, see I/Os, page 77. • Updated SerDes I/O Pins, page 111. For more information, see I/Os, page 77. Revision 0.0 Revision 0.0 was the first publication of this document. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 12: Fabric Architecture

    (DSP) capability. These elements are arranged as several rows inside the fabric, interconnected by the clustered routing architecture of the SmartFusion2 and IGLOO2 device. Each element in the fabric has a distinct logical coordinate value assigned to it.

  • Page 13: Fabric Resources

    LSRAM Logic Clusters Interface Clusters Chip South I/O Clusters Layout Fabric Resources The following tables list the fabric resources available on SmartFusion2 and IGLOO2 devices. Fabric Resources for SmartFusion2 Devices Table 1 • Fabric Resource M2S005 M2S010 M2S025 M2S050...

  • Page 14: Architecture Overview

    (4-input LUT + Flip- Flop) LSRAM 18K blocks µSRAM 1K blocks Math blocks PLLs and CCCs Architecture Overview The following sections of this chapter describe the SmartFusion2 and IGLOO2 fabric architecture in detail. • Logic Element • Interface Logic Element •...

  • Page 15: Interface Logic Element

    I/Os. At the input side, the input registers allow capturing the input signals and synchronizing them to the design clock. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 16: Fpga Routing Architecture

    2.3.4 FPGA Routing Architecture The SmartFusion2 and IGLOO2 fabric has a clustered routing architecture. Clustering is a hierarchical grouping of fabric resources that allows a more area-efficient implementation of designs while maintaining optimal performance. It also helps in reducing the run-time of the place-and-route software.

  • Page 17: Figure 4 Logic Cluster Top-Level Layout

    See SmartFusion2 and IGLOO2 SmartTime, I/O Editor and ChipPlanner User Guide for more details on how to use the constraints using Libero SoC software. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 18: Figure 6 Fabric Routing Structure

    Knowledge of the routing architecture and functional modules can be useful in providing effective design constraints to the software, so that it can be guided to do an optimal design implementation on the SmartFusion2 and IGLOO2 fabric. In the SmartFusion2 and IGLOO2 device, the fabric routing is segregated into two parts: • Inter-cluster routing •...

  • Page 19: Fabric Array Coordinate System

    Fabric Architecture Fabric Array Coordinate System Every element in the SmartFusion2 and IGLOO2 fabric has individual logical X-Y coordinates associated with the fabric array coordinate system. These logical coordinates are used by the place-and-route software while implementing the design using the fabric elements. The place-and-route software can be constrained to occupy the design components in specific locations inside the fabric using this coordinate system.

  • Page 20: Figure 8 M2S025/M2Gl025 Fabric Logical Coordinates

    (0,0) (635,0) Figure 9 • M2S010/M2GL010 Fabric Logical Coordinates (0,104) (407,104) (371,92) LSRAM (0,92) Mathblocks (0,80) (407,80) uSRAM (0,68) (407,68) LSRAM (0,47) (407,47) Mathblocks (0,23) (407,23) uSRAM (0,11) (407,11) (0,0) (407,0) Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 21: Table 3 Fabric Array Coordinate Systems

    (36, 11) (0, 143) (0, 266) (0, 47) (0, 119) (0, 242) M2GL150 (0, 59) (0, 182) (0, 278) (0, 95) (0, 218) (36, (0, 71) (0, 194) (0, 290) 302) Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 22: Lsram

    LSRAM Introduction The SmartFusion2 and IGLOO2 fabric has embedded 18 Kbit SRAM blocks used for storing data. These large SRAM blocks (LSRAMs) are arranged in multiple rows within the FPGA fabric and can be accessed through the fabric routing architecture. The number of LSRAM blocks available depends upon the specific SmartFusion2 and IGLOO2 device, as shown in the following table.

  • Page 23: Functional Description

    Port List • Port Descriptions Architecture Overview SmartFusion2 and IGLOO2 LSRAM embedded memory includes the RAM1Kx18 macro. The following illustration shows a simplified block diagram of the LSRAM memory block and Table 5, page 15 provides the port descriptions. The following illustration shows two independent data ports, the pipeline registers for read data delay, and the feed-through multiplexers to enable immediate access to the write data.

  • Page 24: Port List

    Static High Lock access to SII BUSY Output Dynamic High Busy signal from SII Static inputs are defined at design time and can be or are controlled by flash configuration bits. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 25: Port Descriptions

    B_WEN[1:0] = “11” Write [35:0] (Two-port write-Port B) A_WEN[1:0] = “11” In dual-port mode, every port reads when the corresponding write enable (A_WEN/B_WEN) is "00" and corresponding port select (A_BLK/B_BLK) is active. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 26: Table 8 Address Bus Used And Unused Bits

    [17:0] None 512 x 32 A_DIN[16:9] is [31:24] A_DIN[17] A_DIN[7:0] is [23:16] A_DIN[8] B_DIN[16:9] is [15:8] B_DIN[17] B_DIN[7:0] is [7:0] B_DIN[8] 512 x 36 A_DIN[17:0] is [35:18] None B_DIN[17:0] is [17:0] Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 27: Table 10 Data Output Buses Used And Unused Bits

    No operation in memory from Port A. Port A output is forced to logic 0. B_BLK[2:0] Perform read or write operation on Port B. B_BLK[2:0] No operation in memory from Port B. Port B output is forced to logic 0. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 28 This signal acts as a Status signal when the system controller is accessing the particular LSRAM. Logic 1 on this signal indicates system controller access. This signal can be used to monitor the completion of LSRAM access. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 29: Memory Modes

    The read operation requires one clock cycle in Non-pipelined mode. In Pipelined mode, the output data appears in the next cycle. The write operation requires one clock cycle. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 30: Two-Port Mode

    B_DIN PORT A DATA In A DATA In B Port B Port A Signals Signals DATA Out A DATA Out B PORT B Pipeline Pipeline Register B Register A A_DOUT B_DOUT Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 31: Table 13 Data Width Configurations For Lsram In Two-Port Mode

    In two-port mode, if the write data width is x36/x32 and read data width is x36/x32, both the bits of A_WEN and B_WEN have to be tied to logic 1 and should not be dynamically changed. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 32: Operating Modes

    During flow-through read operation, the LSRAM can generate glitches on the data output buses. Therefore, Microsemi recommends using LSRAM with pipeline registers to avoid these read glitches.

  • Page 33: Figure 13 Read Operation Timing Waveforms

    Block select setup time (With pipeline register enabled) BLKSU Block select hold time (With pipeline register enabled) BLKHD Read enable setup time (A_WEN, B_WEN =0) RDESU Read enable hold time (A_WEN, B_WEN =0) RDEHD Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 34: Write Operation

    T in the same clock cycle. CLK2Q • For a simple write, the written data is displayed on the output only when a read operation is performed on the same address. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 35: Figure 15 Write Operation Timing Waveforms

    Write enable setup time (A_WEN, B_WEN =1) WESU Write enable hold time (A_WEN, B_WEN =1) WEHD Data setup time Data setup time Read access time with Feed-through write timing CLK2Q Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 36: Reset Operation

    The data output changes its state only if a read operation or write operation in Bypass mode is performed on the LSRAM. In a simple write operation, the data output stays Low. Write operation: The corrupted data is written into the memory. Therefore, Microsemi recommends to avoid asserting reset during write operation.

  • Page 37: Figure 17 Block Select Timings

    Block select to out disable time (when pipeline registers are disabled) BLK2Q Read access time without pipeline register CLK2Q Figure 16, page 27 shows the timing diagram for asynchronous reset operation performed on LSRAM. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 38: Collision

    LSRAM Dual-Port Mode The following illustration shows the ports of the DPSRAM IP macro available in Libero SoC. See SmartFusion2 Dual-Port Large SRAM Configuration for detailed software configuration information on dual-port LSRAM. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 39: Figure 18 Ports Of The Lsram Configured As Dual-Port Sram - Dpsram Macro In Libero Soc

    These signals represent the Read data register Synchronous reset for Port A B_DOUT_SRST_N and Port B A_DOUT_ARST_N, Input These signals represent the Read data register Asynchronous reset for Port A B_DOUT_ARST_N and Port B Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 40: Figure 19 Ports Of The Lsram Configured As Two-Port Sram - Tpsram Macro In Libero Soc

    This signal represents the data output for read Port A. RD_EN Input This signal represents the Read data register enable. RD_SRST_N Input This signal represents the Read data register Synchronous reset. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 41: Figure 20 Ram1Kx18 Macro

    The following image shows CoreAHBLSRAM IP (LSRAM with AHB slave Interface), available in Libero SoC. See for detailed software configuration information for dual-port CoreAHBLSRAM Handbook LSRAM. Figure 21 • CoreAHBLSRAM IP in Libero SoC Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 42: Figure 22 Coreapblsram Ip In Libero Soc

    Libero SoC IP catalog has a CoreFIFO IP, which can be configured as a soft FIFO for generation of FIFO control logic. Memory configuration can be selected as LSRAM, µSRAM, or external memory as per the design requirements. See for detailed software configuration information. CoreFIFO Handbook Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 43: Lsram Use Model

    The implementation has the following configurations: • Write port: 512 x 36 • Read port: 1024 x 18 • Read and write input clock: Two different clock sources • Pipelined read mode: Disabled Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 44: Figure 23 Two-Port Sram With W36 And R18

    B_DIN[17:0] {“11”} B_WEN[1:0] {‘1’} B_DOUT_EN {‘0’} B_DOUT_ARST_N {‘1’} B_DOUT_SRST_N {‘1’} B_DOUT_CLK {‘1’} A_DOUT_LAT {“011”} A_WIDTH[2:0] {‘0’} A_WMODE {‘1’} A_EN {‘1’} B_DOUT_LAT {“100”} B_WIDTH[2:0] B_WMODE {‘0’} B_EN {‘1’} S_LOCK {‘0’} LSRAM #2 Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 45: Table 23 Two-Port Configurations Requiring Two Lsram Blocks

    Libero SoC. The following table shows the TPSRAM data width configurations that require two LSRAM blocks. Table 23 • Two-Port Configurations Requiring Two LSRAM Blocks Write Data Width Read Data width Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 46: Micro Sram (Μsram)

    Micro SRAM (µSRAM) Introduction The SmartFusion2 SoC and IGLOO2 FPGA fabrics have embedded 1 Kbit micro SRAM (µSRAM) blocks used for storing data. These µSRAMs are arranged in multiple rows within the FPGA fabric can be accessed through the fabric routing architecture. The number of µSRAM blocks available varies among SmartFusion2 and IGLOO2 devices, as shown in the following figure.

  • Page 47: Functional Description

    4.3.1 Architecture Overview SmartFusion2 and IGLOO2 µSRAM embedded memory includes the RAM64X18 macro, available in Libero SoC software. The following illustration shows a simplified block diagram of the µSRAM memory block with two read data ports, one write data port and pipeline registers at read port.

  • Page 48: Port List

    C_ADDR[9:0] Input Dynamic Address input C_BLK[1:0] Input Dynamic Active High Block select C_WIDTH[2:0] Input Static Depth x width mode selection C_DIN[17:0] Output Dynamic Data output C_CLK Input Dynamic Rising Clock input Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 49: Port Description

    Unused Bits (to be Depth x Width Used Bits grounded) 1K x 1 [9:0] None 512 x 2 [9:1] 256 x 4 [9:2] [1:0] 128 x 9 [9:3] [2:0] 128 x 8 Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 50: Table 28 Data Input Buses Used And Unused Bits

    [17:1] 512 x 2 [1:0] [17:2] 256 x 4 [3:0] [17:4] 128 x 8 [7:0] [17:8] 128 x 9 [8:0] [17:9] 64 x 16 [16:9] [17] [7:0] 64 x 18 [17:0] Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 51: Table 30 Port Select Control Signals

    Pipelined mode, the output data appears in the next clock cycle. In Latch mode operation, the output data appears in the same clock cycle. When the registers are configured as transparent, tie these inputs to logic 1. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 52 (SII). The system controller can access the µSRAM for the following reasons: • Testing the memory • Moving data between µSRAM and eNVM or external memories • Moving data between various µSRAMs Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 53: Operating Modes

    Latch inputs should be tied to High. In Latch mode, both the input and output clocks should be in opposite phase. Microsemi recommends configuring the pipeline registers, in either the register or Latch mode during read operation to avoid glitches on the read output data lines.

  • Page 54: Figure 25 Timing Waveforms For Synchronous-Asynchronous Read Operation

    The input register clock and pipeline register clock must be synchronous to each other; hence they should be sourced from the same clock input. • The output data appears on the output bus in the next clock cycle. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 55: Figure 26 Timing Waveforms For Synchronous-Synchronous Read Operation

    This mode is used to moderate the effect of glitches that can appear on the µSRAM's data output bus when used without the pipeline registers (when µSRAM is configured in Synchronous- Asynchronous read mode). Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 56: Figure 27 Timing Waveforms For Synchronous Latched Read Operation

    After the input address is provided, the output data is displayed on the output data bus after a T A2QR delay, as shown in the following figure. • The µSRAM can generate glitches on the data output bus when used without the pipeline register. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 57: Figure 28 Timing Waveforms For Read Operations With Asynchronous Inputs Without Pipeline Registers

    Read pipeline clock minimum pulse width High PLCLKMPWH Read pipeline clock minimum pulse width Low PLCLKMPWL Read address setup time in Synchronous mode ADDRSU Read address hold time in Synchronous mode ADDRHD Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 58: Write Operation

    C_CLK input for a successful write operation. • If all the inputs meet the required timing parameters, the input data is written into µSRAM in one clock cycle. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 59: Reset Operation

    0, which in turn forces the data output to logic 0. When the registers are configured as transparent, tie these inputs to logic 1. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 60: Figure 32 Timing Waveforms For Asynchronous Reset

    0, which in turn forces the data output to logic 0. The following illustration shows the timing waveform for synchronous reset. Figure 33 • Timing Waveforms for Synchronous Reset CLKMPWH CLKMPWL A_ADDR_CLK B_ADDR_CLK SRSTSU SRSTHD A_ADDR_SRST_N B_ADDR_SRST_N CLK2Q A_DOUT B_DOUT Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 61: Collision

    There is no collision prevention or detection implemented in the µSRAM architecture, so the designer must take measures to avoid the last three scenarios in designs. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 62: How To Use Μsram

    µSRAM - IP The following figure shows the ports of the µSRAM IP macro available in Libero SoC. See the SmartFusion2/IGLOO2 Micro SRAM Configuration User Guide for detailed information about software configuration for SRAM. Figure 34 • µSRAM IP Macro in Libero SoC Table 41 •...
  • Page 63 The µSRAM must be configured correctly with the appropriate values provided to the static signals before instantiating it in the design. The following figure shows the µSRAM macro (RAM64x18) available in Libero SoC. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 64: Figure 35 Ram64X18 Macro

    Libero SoC IP catalog has a CoreFIFO IP, which can be configured as a soft FIFO for generation of FIFO control logic. Memory configuration can be selected as LSRAM, µSRAM or external memory as per the design requirements. See CoreFIFO Handbook for detailed software configuration information. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 65: Math Blocks

    (IIR) filters, fast fourier transform (FFT) functions, and encoders that require high data throughput. The SmartFusion2 and IGLOO2 math blocks have a built-in multiplier and adder, which minimizes the external logic required to implement multiplication, multiply-add, and multiply-accumulate (MACC) functions.

  • Page 66: Functional Description

    This section provides the detailed description of the architecture of math block. 5.3.1 Architecture Overview The SmartFusion2 and IGLOO2 devices can have one to three rows of math blocks in the FPGA fabric, as listed in Table 42, page 56. Math blocks can be accessed through the FPGA routing architecture and cascaded in a chain, starting from the left-most block to the right-most block.

  • Page 67: Figure 37 Functional Block Diagram Of The Math Block In Normal Mode

    Math blocks have built-in registers on data inputs (A, B, C), data output (P), and control signals. If required, these registers can be bypassed. All the registers in the math block have clock gating capability to reduce power consumption. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 68: Table 43 Truth Table For Propagating Operand D Of The Adder Or Accumulator

    (most positive) or minimum (most negative) value that can be represented. In SmartFusion2 and IGLOO2 math blocks, this capability is implemented using the adder's output sign bit (MSB [43] bit of the P output) and the overflow signal.

  • Page 69: How To Use Math Blocks

    The math block primitive available in the Libero SoC IP Catalog is called MACC. Figure 45, page 70 shows the MACC primitive with input/output port and the bit width of each port. The port list and definitions are given in the following table. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 70: Figure 39 Math Block Macro

    Unused active high dynamic signals should be connected to ground, unused active low dynamic signals should be connected to high, and unused static signals should be in default state. Figure 39 • Math Block Macro Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 71: Table 44 Math Block Pin Descriptions

    B_ARST_N[1:0] Input Dynamic Asynchronous reset B_ARST_N[1] is for B[17:9] B_ARST_N[0] is for B[8:0] When not registered, connect B_ARST_N [1:0] to logic 1. In Normal mode, ensure B_ARST_N [1] = B_ARST_N [0]. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 72 Static High Latch input to bypass data registers C_BYPASS[1] is for C[43:18] C_BYPASS[0] is for C[17:0] When not registered, connect C_BYPASS[1:0] to logic 1. In Normal mode, ensure C_BYPASS[1] = C_BYPASS[0]. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 73 When logic '1', ARSHFT17 is not registered. ARSHFT17_AD Input Static High Asynchronous load data for the ARSHFT17 input's control register. ARSHFT17_SD_N Input Static Synchronous load data for the ARSHFT17 input's control register. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 74 When logic 1, FDBKSEL is not registered. FDBKSEL_AD Input Static High Asynchronous load data for the FDBKSEL input's control register. FDBKSEL_SD_N Input Static Synchronous load data for the FDBKSEL input's control register. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 75 Otherwise, OVFL_CARRYOUT is the overflow output. CDOUT[43:0] Output Cascade output of result P. CDOUT is the same as P. It is used to drive the CDIN of another math block. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 76: Math Block Use Models

    Note: Asynchronous load input has higher priority than the synchronous load input. 5.4.2 Math Block Use Models This section describes a few use models for SmartFusion2 and IGLOO2 math blocks. 5.4.2.1 Use Model 1: Non-Pipelined Implementation of the 35 x 35 Multiplier 35 x 35 multipliers are useful for applications which require more than 18-bit precision.

  • Page 77: Figure 40 Non-Pipelined 35 X 35 Multiplier

    Use Model 2: Pipelined Implementation of the 35 x 35 Multiplier The SmartFusion2 and IGLOO2 math blocks have built-in registers on all input and output ports. To implement high-speed multipliers, extra registers are added to the input or output side of the math blocks to balance the pipeline latency.

  • Page 78: Figure 42 9-Bit Complex Multiplication Using Dotp Mode

    The math block uses its C input for multi-threading and multi-channeling, but fabric registers are also required for implementation. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 79: Figure 43 Rounding Using C-Input And Carryin

    110.100 0.011 000.000 110.111 000.001 111.000 -2.5 101.100 0.011 000.001 110.000 110 000.001 110.000 Figure 43 • Rounding Using C-Input and CARRYIN A[17:0] B[17:0] P[43:0] C Input Fixed Term CARRYIN Variable Term Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 80: Figure 44 Rounding And Trimming Of The Final Sum

    Round towards zero can be done using sign bit of the product (A × B) from the sign bits of the incoming factors A and B using an EXOR. Figure 45 • Rounding and Trimming of the Final Sum A[17] B[17] C[m-1] C[m-1] C[43:m] P[43:m] Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 81: Coding Style Examples

    @ ( posedge clock ) begin if ( ~reset ) begin in1_reg <= 18'b0; in2_reg <= 18'b0; out1 <= 41'b0; else begin in1_reg <= in1; n2_reg <= in2; out1 <= in1_reg × in2_reg; endmodule Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 82 This example shows an unsigned multiplier with inputs and outputs that are registered with different clocks: clock1 and clock2. In this case, the synthesis tool places only the output registers and the multiplier into the SmartFusion2 or IGLOO2 math block. The input registers are implemented in FPGA logic outside the math block.
  • Page 83 Example 5: Multiplier-Adder In the code below. the output of a multiplier is added with another input. Inputs and outputs are registered and have enables and synchronous resets. The synthesis tool maps the code into one SmartFusion2 or IGLOO2 math block.
  • Page 84 ( ~rst ) begin in1_reg <= 17'b0; in2_reg <= 17'b0; out1 <= 40'b0; else begin in1_reg <= in1; in2_reg <= in2; out1 <= (in1_reg × in2_reg) - in3; endmodule Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 85 The synthesis tool uses four cascaded math blocks to implement this multiplication function. The synthesis tool first infers pipeline registers at the input, output of the SmartFusion2 or IGLOO2 math block and controls pipeline latency by balancing the number of register stages. To balance the stages, the tool adds additional registers at the input or output of the math block as required, implemented in the fabric logic.

  • Page 86: Introduction

    The MSIO, MSIOD, and DDRIO are configured at power-up through the flash bits used to initialize the fabric register blocks. This is automatically done using the Libero SoC software. Functional Description SmartFusion2 and IGLOO2 I/Os are classified into the following three categories depending on their functional usage: •...

  • Page 87: Figure 46 I/O Interconnection

    N on the top and P on the bottom. There is one IOD for each pair of IOAs. To support different differential standards, SmartFusion2 and IGLOO2 use a pair of regular I/O cells: P and N. These two I/O cells of MSIO, MSIOD, and DDRIO can be configured as separate single-ended I/Os or configured as one differential I/O pair.

  • Page 88: Transmit Buffer

    The I/O input can be configured as a schmitt trigger receiver or a single-ended receiver. When schmitt trigger receiver is selected, the input buffer has hysteresis that filters noise at the receiver and prevents double glitching caused by the noisy input edges. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 89: Low-Power Exit

    Delay _VREF The MSIO and MSIOD in SmartFusion2/IGLOO2 devices support DDR mode. In DDR mode, the new data is present on every transition (or clock edge) of the clock signal. DDR mode doubles the data transfer rate as compared to single data rate (SDR) mode where new data is present on one transition (or clock edge) of the clock signal.

  • Page 90: On-Die Termination

    Where does the inductance come from? The device ground is connected to the system ground (PCB ground) through a series of inductors, comprised of package bond wire, package trace, and board inductance as shown in the following figure. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 91: Figure 49 A Sample Switching Output Buffer Showing Parasitic Inductance

    The sensitive I/O affected by SSO is sometimes referred to as the victim I/O or quiet I/O. SSOs may affect the victim I/O if the total number of SSOs on both sides of the victim I/O exceeds the SmartFusion2 / IGLOO2 device SSO recommendation. It is important to note that the SSOs must be referenced to the die pads and not package pins.

  • Page 92: Table 46 Msio Sso Guidelines For M2S010 - Fg484 Device

    LVCMOS15 (SSOs LVCMOS12 (SSOs Causing) Causing) Causing) Causing) Drive Drive Drive Drive Strengt Strengt Strengt Strengt h (mA) Bounce Bounce h (mA) Bounce Bounce h (mA) Bounce Bounce h (mA) Bounce Bounce Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 93: Table 49 Msio, Msiod, And Ddrio Sso Guidelines For M2S025 - Fg484 Device

    LVCMOS12 (SSOs (SSOs Causing) Causing) Causing) Causing) Drive Drive Drive Drive Strengt Strengt Strengt strengt h (mA) Bounce Bounce h (mA) Bounce Bounce h (mA) Bounce Bounce h (mA) Bounce Bounce Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 94: Table 52 Ddrio Sso Guidelines For M2S050 - Fg896 Device

    Drive Drive Drive Standar Strengt Standar Strengt Standar Strengt h (mA) Bounce Bounce h (mA) Bounce Bounce h (mA) Bounce Bounce LVTTL LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 95: Table 55 Msio, Msiod, And Ddrio Sso Guidelines For M2S090 - Fcs325 Device

    Standar Strengt Standar Strengt Standar Strengt h (mA) Bounce Bounce h (mA) Bounce Bounce h (mA) Bounce Bounce LVTTL LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO LVCMO Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 96: Supported I/O Standards

    I/Os Supported I/O Standards SmartFusion2/IGLOO2 devices support the different I/O standards, as listed in the following table. These I/O standards can be configured using Libero SoC. See for more details. Libero SoC User Guide The following table lists all the I/O standards supported for single-ended and differential I/Os: Table 57 •...

  • Page 97: Single-Ended Standards

    6.5.1.2 Low Voltage CMOS (LVCMOS) SmartFusion2 and IGLOO2 devices provide five different kinds of LVCMOS: LVCMOS 3.3 V, LVCMOS 2.5 V, LVCMOS 1.8 V, LVCMOS 1.5 V, and LVCOMS1.2 V. LVCMOS 3.3 V (only in MSIO) is an extension of the LVCMOS standard (JESD8-B compliant) used for general purpose 3.3 V applications. LVCMOS 2.5 V is an extension of the LVCMOS standard (JESD8-5-compliant) used for general purpose 2.5 V...

  • Page 98: Differential Standards

    400 MHz. The other advantages of these standards are low power and fewer EMI concerns. HSTL has four classes, of which SmartFusion2 and IGLOO2 devices support Class I. The reference voltage (V ) is 0.75 V.

  • Page 99: I/O Programmable Features

    The SmartFusion2 and IGLOO2 MSIOD has an internal circuit isolation, and the bus isolation should be taken care of in the design external to the device when using M-LVDS.

  • Page 100: Programmable Slew-Rate Control

    The following figure shows an example slew-rate using the I/O attribute editor. Figure 51 • Programmable Slew-Rate Following is the example script to set slew-rate using io.pdc: set_io signal name -pinname A8 -fixed yes -SLEW MEDIUM_FAST \ -DIRECTION OUTPUT Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 101: Programmable Input Delay

    Up, Down, or None through the I/O attribute editor or the pdc file. The following figure shows an example to set weak pull-up and pull-down using the I/O attribute editor. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 102: Programmable Schmitt Trigger Receiver

    (dB) through the I/O attribute editor or the pdc file. Table 63, page 94 for the I/O standards, which support programmable pre-emphasis option. The following figure shows an example to set pre-emphasis using the I/O attribute editor. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 103: Bus Keeper

    Empha e Slew- (Off/0-63) Swap Rate Schmitt Trigger Input Resistor Pull Standa MSIO MSIOD DDRIO MSIO MSIOD DDRIO MSIO MSIOD DDRIO MSIO MSIOD DDRIO LVTTL LVPEC L (Input only) LVDS3 LVCMO Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 104: Receiver Odt Configuration

    MLVDS Yes Receiver ODT Configuration SmartFusion2 and IGLOO2 user I/Os support ODT features available on I/O, which is configured as input or bidirectional buffers. The ODT termination provides a good signal integrity, saves board space, and reduces external components on PCB.

  • Page 105: Receiver Odt Configuration For Msio And Msiod Banks

    Following is the sample script to set ODT static and ODT impedance values using io.pdc: set_io signal name -iostd SSTL18I -ODT_IMP 75 -ODT_STATIC On -DIRECTION INPUT Signal name is the user I/O name that the designer has to set ODT static and impedance values. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 106: Receiver Odt Configuration For Ddrio Banks

    6.7.2 Receiver ODT Configuration for DDRIO Banks SmartFusion2 and IGLOO2 DDRIOs have an in-built I/O calibration engine for impedance calibration. The I/O calibration engine can be enabled or disabled by using System Builder during MDDR or FDDR configuration. The I/O calibration engine is enabled to achieve the impedance control by calibrating the I/O drivers to an external on-board resistor connected between the DDR_IMP_CALIB and VSS pins.

  • Page 107: Table 65 Odt Configuration Options For Msio, Msiod, And Ddrios

    DDR controller is used in a bank, it takes over ODT_STATIC of its own I/Os only. ODT for other I/Os in the same bank can still be controlled using ODT_STATIC option for that particular I/O. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 108: Table 66 Ddrio Odt Configuration- For I/O Connected To Fabric

    On-board I/O Calibration Resistor for I/O External Memory I/O Standards Engine Local ODT Impedance Calibration Terminations LPDDR LVCMOS 18 On- Not Supported Optional 50, 75, 150 150  ± 1% Optional Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 109: Driver Impedance Configuration

    Optional Required Driver Impedance Configuration SmartFusion2/IGLOO2 I/Os support driver impedance configuration only for the output or bidirectional buffers.The driver impedance internal series termination provides a good signal integrity, saves board space, and reduces external components on the PCB. The Libero SoC tool has output drive settings for driver impedance configuration.

  • Page 110: Driver Impedance Configuration For Msio/Msiods

    I/Os 6.8.1 Driver Impedance Configuration for MSIO/MSIODs SmartFusion2/IGLOO2 device output or bidirectional buffers have a programmable drive-strength control for certain I/O standards to mitigate the effects of high signal attenuation due to the long transmission line. The following table lists the programmable drive strengths and these can be set through the I/O attribute editor: Table 69 •...

  • Page 111: I/O Buffer Structure

    All MSIOs are cold separable as the internal clamp diodes are always disabled, except if MSIOs are configured in the PCI I/O standards, which are not cold separable. For more information, see the AC396: SmartFusion2 and IGLOO2 in Hot Swapping and Cold Sparing Application Note. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 112: Low-Power Signature Mode And Activity Mode

    SmartFusion2 and IGLOO2 devices support Flash*Freeze mode, where several device resources are put into a low-power state using various power management hooks available for each resource. The following two methods can be used for SmartFusion2 and IGLOO2 devices wake-up from Flash*Freeze mode: •...

  • Page 113: Signature Mode

    (Rise Time + Fall (Rise Time + Fall Rext 1 (W) Rext 2 (W) I (mA) (ns) (ns) Time) Time) 2.72 2.32 2.54 2.61 2.62 2.41 2.97 2.96 2.18 3.54 3.51 4.54 5.56 5.41 Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 114: Input Tolerance And Output Driving Compatibility (Only Msio)

    R1 = 220  (±5%), P(r1)min = 0.018  R2 = 390  (±5%), P(r2)min = 0.032  Imax_tx = 5.5 V / (220 × 0.95 + 390 × 0.95 + 10) = 9.17 mA Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 115: Figure 61 5 V-Input Tolerance Solution 1

    These are ideal for voltage translation interfaces between buses, and in applications that require isolation and protection. Well-implemented bus switch designs maximize the bus speed. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 116: Output Driving Compatibility

    5 V Output Driving Compatibility SmartFusion2 and IGLOO2 I/Os must be set to 3.3 V LVTTL mode or 3.3 V LVCMOS mode to reliably drive 5 V TTL receivers. It is also critical that there is no external I/O pull-up resistor to 5 V, since this pulls the I/O pad voltage beyond the 3.6 V absolute maximum value and, consequently, cause damage to...

  • Page 117: Msios/Msiods With Mss Or Hpms Peripherals

    JTAG instruction to be executed and a 128-bit data I/O buffer that transfers any associated data. The TAP controller uses 8-bit instructions consistent with previous Microsemi families. The JTAG pin standards are in accordance with MSIO standards. The JTAG pins can be run at any voltage from 1.5 V to 3.3 V (nominal).

  • Page 118: Table 76 Recommended Tie-Off Values For The Tck And Trst Pins

    In critical applications, a fault in the JTAG circuit allows the device entering an undesired JTAG state. In such cases, Microsemi recommends tying off TRSTB to GND through a resistor placed close to the FPGA pin.

  • Page 119: Dedicated I/O

    Chip-level Resets System Resets Asserting device reset causes a SmartFusion2 or IGLOO2 device to exit Flash*Freeze mode; this is very useful in recovering from a situation where the device enters Flash*Freeze mode without the Flash*Freeze exit mechanism being correctly configured in the I/O cells or in the real-time clock (RTC).

  • Page 120: Serdes I/O

    Datasheet. 6.16.3.2 SerDes I/O Pins Each SerDes interface in SmartFusion2 and IGLOO2 devices has four SerDes I/O data lanes or sixteen SerDes I/Os available for accessing the SerDes interface (SERDESIF block). Each data lane has two pairs of differential signals: one for transmit data (TxDP, TxDN) and the other for receive data (RxDP, RxDN).

  • Page 121: Glossary

    Least significant bit LSRAM Large static random access memory LVDS Bus LVDS LVPECL Low-voltage positive emitter coupled logic LVTTL Low voltage transistor transistor logic MDDR Microcontroller subsystem double data rate MLVDS Multipoint LVDS Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...
  • Page 122 Glossary Most significant bit MSIO Multi-standard I/O MultiView Navigator On-die termination RSDS Reduced swing differential signaling SerDes Serializer/deserializer SSTL Stub series terminated logic µSRAM Micro static random access memory Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

  • Page 123: Terminology

    Logic Cluster A logic cluster is formed by grouping 12 logic elements. Logic Element The basic logic element in the SmartFusion2 SoC and IGLOO2 FPGA fabric, consisting of a 4-input LUT, a D-flip-flop, and a dedicated carry chain. Low-Power Exit Logic for the chip to come out from low-power state.
  • Page 124 A write operation in which the data written does not appear on the SRAM output ports. STMR Self-corrected triple module redundancy Transparent Mode Non-registered/Non-pipelined mode Two-Port Mode SRAM with two ports, one dedicated to read operations and the other dedicated to write operations. Microsemi Proprietary and Confidential UG0445 User Guide Revision 7.0...

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