Microsemi SmartFusion2 Demo Manual

Microsemi SmartFusion2 Demo Manual

Soc fpga coretse_ahb 1000 base-t loopback - libero soc v11.8
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DG0637
Demo Guide
SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T
Loopback - Libero SoC v11.8

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Summary of Contents for Microsemi SmartFusion2

  • Page 1 DG0637 Demo Guide SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback - Libero SoC v11.8...
  • Page 2 Within the USA: +1 (800) 713-4113 with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this...
  • Page 3: Table Of Contents

    Programming the Design ............8 2.4.2 Connecting SmartFusion2 Security Evaluation Board to Host PC ..... 11 2.4.3 Running the Demo Design with Cat Karat and Wireshark on the Hardware .
  • Page 4 SmartFusion2 Security Evaluation Kit Setup ........
  • Page 5 Table 2 SmartFusion2 Security FPGA Evaluation Kit Jumper Settings ......7 DG0637 Demo Guide Revision 3.0...
  • Page 6: Revision History

    Revision History Revision History The revision history describes the changes that were implemented in the document. The changes are listed by revision, starting with the most current publication. Revision 3.0 The following is a summary of the changes in revision 2.0 of this document. •...
  • Page 7: Smartfusion2 Soc Fpga Coretse_Ahb 1000 Base-T Loopback Demo

    Multiple instances of the CoreTSE IP can be used to achieve Ethernet solutions in SmartFusion2 devices. The CoreTSE_AHB IP, along with MSS Ethernet MAC, can be used to support multiple Ethernet interfaces for SmartFusion2 devices. For...
  • Page 8: Demo Design

    SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo Table 1 • Design Requirements (continued) Software Requirements Libero SoC 11.8 FlashPro Programming Software 11.8 SoftConsole v4.0 Cat Karat Packet Generator Software Provided with design files Wireshark Software Provided with design files...
  • Page 9: Design Features

    The following figure shows the demo design block diagram. Figure 2 • SmartFusion2 CoreTSE_AHB 1000 Base-T Loop back Demo Block Diagram In this demo design, CoreTSE_AHB is instantiated in the FPGA fabric and connected to the on-board Ethernet PHY using high-speed serial interface (SERDES_IF).
  • Page 10: Design Description

    AHB interface and forwards it to it on the CoreTSE_AHB transmit (TX) path. CoreTSE_AHB transmits the Ethernet packet to the on-board Ethernet PHY through high-speed SERDES. 2.2.1.4 Ethernet Test Solution There are many ways to evaluate the CoreTSE_AHB 1000 Base-T loopback demo on the SmartFusion2 Security Evaluation board. 2.2.1.4.1 Solution 1 •...
  • Page 11: Simulating The Design

    SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo Simulating the Design A test bench design is created for CoreTSE_AHB loopback demo. The test bench transmits the Ethernet packet to CoreTSE_AHB loopback demo design and receives the loopback Ethernet packet from the CoreTSE_AHB loopback demo design.
  • Page 12: Setting Up The Demo Design

    The following steps describe how to setup the demo. Connect the FlashPro4 Programmer to the J5 connector on the SmartFusion2 FPGA Security Evaluation Board. Connect the jumpers to the SmartFusion2 FPGA Security Evaluation Board as specified in the following table. Table 2 •...
  • Page 13: Programming The Design

    SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo 2.4.1 Programming the Design The following steps describe how to program the demo design. Download the demo design from the following path: http://soc.microsemi.com/download/rsc/?f=m2s_dg0637_liberov11p7sp2_df Switch ON the power supply switch, SW7. Launch the FlashPro software.
  • Page 14: Figure 7 Flashpro Project Configuration

    SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo Click Configure Device. Figure 7 • FlashPro Project Configuration 10. Click Browse, navigate to the location where the SF2_1000BaseT_Demo.stp file is located, and select the file. The default location is: <download_folder>\SF2_1000BaseT_loopback_demo_df\ProgrammingFile\ 11. Select Advanced as the Mode, and select PROGRAM under Action.
  • Page 15: Figure 8 Flashpro Programming Passed

    SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo 12. Click PROGRAM to start programming the device. Wait until the programmer status is changed to RUN PASSED. Figure 8 • FlashPro Programming Passed DG0637 Demo Guide Revision 3.0...
  • Page 16: Connecting Smartfusion2 Security Evaluation Board To Host Pc

    2.4.2 Connecting SmartFusion2 Security Evaluation Board to Host PC The following steps describe how to connect the SmartFusion2 Security Evaluation Board to the host PC: After successful programming, switch OFF the SmartFusion2 Security Evaluation Board. Connect the host PC to the J13 connector on the SmartFusion2 Security Evaluation Kit using the RJ45 cable.
  • Page 17: Figure 10 Wireshark Network Analyzer

    SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo On the host PC, open the Wireshark network analyzer. Select Start as shown in Figure 10, page 12. Figure 10 • Wireshark Network Analyzer On the host PC, open the Cat Karat software, as shown in the following figure.
  • Page 18: Figure 12 Packet Flow Control

    Under Protocol View, select the RAW tab and copy the Ethernet net packet from the source files (<download folder>\ SF2_1000BaseT_loopback_demo_df \Source Files\Raw_packet.txt), as shown Figure 11, page 12. Under Interfaces, select the Ethernet connection to the SmartFusion2 Evaluation board. Select Start Transmit from the menu, as shown in Figure 11, page 12, to transmit the packet.
  • Page 19: Appendix: Running The Demo Design Using Spirent Test Center

    Spirent Test Center The following steps describe how to run the CoreTSE_AHB loopback demo using Spirent test center: Connect the SmartFusion2 Security Evaluation Kit to the slot 1 Ethernet port on the Spirent test equipment using the RJ45 cable. On the host PC, open the Spirent test center configurator.
  • Page 20: Figure 15 Spirent Test Center -Traffic Generator

    Appendix: Running the Demo Design Using Spirent Test Center Select Traffic Generator under Ports, add packet information in stream block editor, and click Start Traffic on all ports, as shown in the following figure. Figure 15 • Spirent Test Center –Traffic Generator Ethernet packets are transmitted and received on port 1 through the RJ45 cable.

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