Simulating The Design; Figure 4 Smartdesign For Simulation - Microsemi SmartFusion2 Demo Manual

SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo
2.3

Simulating the Design

A test bench design is created for CoreTSE_AHB loopback demo. The test bench transmits the Ethernet
packet to CoreTSE_AHB loopback demo design and receives the loopback Ethernet packet from the
CoreTSE_AHB loopback demo design.
The design uses bus functional model (BFM) simulation for initializing the CoreTSE with the required
configuration. The user.bfm file under the
<LiberoProject>/simulation folder contains the BFM commands for writing the packet to LSRAM
or reading the packet from LSRAM.
The Raw Ethernet Packet frame is:
0102030405060708090a0b0c0d0e5555555555555555555555551b1c1d1e1f202122232425262728292
a2b2c2d2e2f303132333435363738393a3b3c3d3e3f40.
The test bench reads the Ethernet packet from the user.bfm file and puts the Ethernet packet on to the
high-speed SERDES_IF of CoreTSE_AHB loopback design.
The loopback packet is received by the test bench and displayed on the ModelSim transcript window.
The following figure shows the Libero SmartDesign to simulate the CoreTSE_AHB loopback demo
design. The simulation test bench has the following Libero components:
• CoreTSE_AHB
• High-speed SERDES_IF
• Test bench with packet transmit and packet receive logic
The Ethernet packet is generated from the file (packetfile.txt) and transmitted by the test bench module
through the high-speed serial interface. The CoreTSE loopback design receives the packet and transmits
it back to the test bench for comparison and display in the ModelSim transcript window.
Note: Simulation is not supported in the current version of CoreTSE_AHB. It will be supported in future
releases of the IP.
Figure 4 • SmartDesign for Simulation
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