Microsemi SmartFusion2 MSS Configuration Manual
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Microsemi SmartFusion2 MSS Configuration Manual

Microsemi SmartFusion2 MSS Configuration Manual

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SmartFusion2 MSS
DDR Controller Configuration
Libero SoC v11.6 and later

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Summary of Contents for Microsemi SmartFusion2 MSS

  • Page 1 SmartFusion2 MSS DDR Controller Configuration Libero SoC v11.6 and later...

  • Page 2: Table Of Contents

    Table of Contents Introduction ..............3 1 MDDR Configurator .

  • Page 3: Introduction

    Introduction The SmartFusion2 MSS has an embedded DDR controller. This DDR controller is intended to control an off-chip DDR memory. The MDDR controller can be accessed from the MSS as well as from the FPGA fabric. In addition, the DDR controller can also be bypassed, providing an additional interface to the FPGA fabric (Soft Controller Mode (SMC)).

  • Page 4: Mddr Configurator

    1 – MDDR Configurator The MDDR Configurator is used to configure the overall datapath and the external DDR Memory Parameters for the MSS DDR controller. Figure 1-1 • MDDR Configurator Overview The General tab sets your Memory and Fabric Interface settings (Figure 1-1).
  • Page 5 Fabric Interface Settings By default, the hard Cortex-M3 processor is set up to access the DDR Controller. You can also allow a fabric Master to access the DDR Controller by enabling the Fabric Interface Setting checkbox. In this case, you can choose one of the following options: •...

  • Page 6: Mddr Controller Configuration

    2 – MDDR Controller Configuration When you use the MSS DDR Controller to access an external DDR Memory, the DDR Controller must be configured at runtime. This is done by writing configuration data to dedicated DDR controller configuration registers. This configuration data is dependent on the characteristics of the external DDR memory and your application.
  • Page 7 Figure 2-1 • MDDR Configuration—Memory Initialization Parameters (LPDDR) • Timing Mode - Select 1T or 2T Timing mode. In 1T (the default mode), the DDR controller can issue a new command on every clock cycle. In 2T timing mode, the DDR controller holds the address and command bus valid for two clock cycles.
  • Page 8 Figure 2-2 • MDDR Configuration—Memory Initialization Parameters (DDR2)
  • Page 9 Figure 2-3 • MDDR Configuration—Memory Initialization Paramet ers (DDR3) Memory Timing This tab allows you to configure the Memory Timing parameters. Refer to the Data Sheet of your LPDDR/ DDR2/DDR3 memory when configuring the Memory Timing parameters. When you change or enter a value, the Register Description pane gives you the register name and register value that is updated.

  • Page 10: Importing Ddr Configuration Files

    Figure 2-4 • MDDR Configuration Memory Timing Tab Importing DDR Configuration Files In addition to entering DDR Memory parameters using the Memory Initialization and Timing tabs, you can import DDR register values from a file. To do so, click the Import Configuration button and navigate to the text file containing DDR register names and values.

  • Page 11: Exporting Ddr Configuration Files

    Note: If you choose to import register values rather than entering them using the GUI, you must specify all necessary register values. Refer to the SmartFusion2 SoC FPGA High Speed DDR Interfaces User’s Guide for details. Exporting DDR Configuration Files You can also export the current register configuration data into a text file.

  • Page 12: Firmware

    <project dir>/simulation directory: • test.bfm - Top-level BFM file that is first "executed" during any simulation that exercises the SmartFusion2 MSS' Cortex-M3 processor. It executes peripheral_init.bfm and user.bfm, in that order. • peripheral_init.bfm - Contains the BFM procedure that emulates the CMSIS::SystemInit() function run on the Cortex-M3 before you enter the main() procedure.

  • Page 13: Mss Ddr Configuration Path

    MSS DDR Configuration Path The Peripheral Initialization solution requires that, in addition to specifying MSS DDR configuration register values, you configure the APB configuration data path in the MSS (FIC_2). The SystemInit() function writes the data to the MDDR configuration registers via the FIC_2 APB interface. Note: If you are using System Builder the configuration path is set and connected automatically.
  • Page 14 For complete details on configuring and connecting the CoreConfigP and CoreResetP cores, refer to the Peripheral Initialization User Guide. Figure 2-8 • FIC_2 Ports...

  • Page 15: Port Description

    3 – Port Description DDR PHY Interface Table 3-1 • DDR PHY Interface Port Name Direction Description Remarks MDDR_CAS_N DRAM CASN MDDR_CKE DRAM CKE MDDR_CLK Clock, P side MDDR_CLK_N Clock, N side MDDR_CS_N DRAM CSN MDDR_ODT DRAM ODT Ignore this signal for LPDDR Interface.
  • Page 16 Table 3-1 • DDR PHY Interface Port Name Direction Description Remarks For LPDDR, connect this  MDDR_DQS_TMATCH_0_OUT FIFO out signal signal to  FDDR_DQS_TMATCH_0_I For LPDDR, connect this  MDDR_DQS_TMATCH_1_IN FIFO in signal (32-bit only) signal to  FDDR_DQS_TMATCH_1_ OUT. For LPDDR, connect this  MDDR_DQS_TMATCH_1_OUT FIFO out signal (32-bit only) signal to  FDDR_DQS_TMATCH_1_I MDDR_DM_RDQS_ECC INOUT Dram ECC Data Mask MDDR_DQS_ECC INOUT Dram ECC Data Strobe Input/...
  • Page 17 Table 3-3 • Fabric Master AXI Bus Interface (continued) Port Name Direction Description DDR_AXI_S_ARREADY Read address ready DDR_AXI_S_RID[3:0] Read ID Tag DDR_AXI_S_RRESP[1:0] Read Response DDR_AXI_S_RDATA[63:0] Read data DDR_AXI_S_RLAST Read Last This signal indicates the last transfer in a read burst DDR_AXI_S_RVALID Read address valid DDR_AXI_S_AWID[3:0]...
  • Page 18 Fabric Master AHB0 Bus Interface Table 3-4 • Fabric Master AHB0 Bus Interface Port Name Direction Description DDR_AHB0_SHREADYOUT AHBL slave ready - When high for a write indicates the MDDR is ready to accept data and when high for a read indicates that data is valid DDR_AHB0_SHRESP AHBL response status - When driven high at the end of a transaction...
  • Page 19 Fabric Master AHB1 Bus Interface Table 3-5 • Fabric Master AHB1 Bus Interface Port Name Direction Description DDR_AHB1_SHREADYOUT AHBL slave ready - When high for a write indicates the MDDR is ready to accept data and when high for a read indicates that data is valid DDR_AHB1_SHRESP AHBL response status - When driven high at the end of a transaction indicates that the transaction has completed with errors.
  • Page 20 Soft Memory Controller Mode AXI Bus Interface Table 3-6 • Soft Memory Controller Mode AXI Bus Interface Port Name Direction Description SMC_AXI_M_WLAST Write last SMC_AXI_M_WVALID Write valid SMC_AXI_M_AWLEN[3:0] Burst length SMC_AXI_M_AWBURST[1:0] OUT Burst type SMC_AXI_M_BREADY Response ready SMC_AXI_M_AWVALID Write Address Valid SMC_AXI_M_AWID[3:0] Write Address ID SMC_AXI_M_WDATA[63:0]...
  • Page 21 Soft Memory Controller Mode AHB0 Bus Interface Table 3-7 • Soft Memory Controller Mode AHB0 Bus Interface Port Name Direction Description SMC_AHB_M_HBURST[1:0] AHBL Burst Length SMC_AHB_M_HTRANS[1:0] AHBL transfer type - Indicates the transfer type of the current transaction. SMC_AHB_M_HMASTLOCK AHBL lock - When asserted the current transfer is part of a locked transaction SMC_AHB_M_HWRITE AHBL write -- When high indicates that the current transaction is a write.

  • Page 22: A Product Support

    Technical Support For Microsemi SoC Products Support, visit http://www.microsemi.com/products/fpga-soc/design-support/ fpga-soc-support. Website You can browse a variety of technical and non-technical information on the Microsemi SoC Products Group home page, at www.microsemi.com/soc. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website.

  • Page 23: Itar Technical Support

    The ©2016 Microsemi Corporation. All rights information provided by Microsemi hereunder is provided "as is, where is" and with all faults, and the entire reserved. Microsemi and the Microsemi risk associated with such information is entirely with the Buyer.

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