SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo
The following figure shows the demo design block diagram.
Figure 2 •
SmartFusion2 CoreTSE_AHB 1000 Base-T Loop back Demo Block Diagram
In this demo design, CoreTSE_AHB is instantiated in the FPGA fabric and connected to the on-board
Ethernet PHY using high-speed serial interface (SERDES_IF).
In the previous figure, the dotted arrow in red shows the transfer of Ethernet packet from the host PC to
the internal LSRAM and the dotted arrow in blue shows the retransmission of packet from LSRAM to the
host.
2.2.1
Design Features
The demo design performs Ethernet loopback using CoreTSE_AHB in TBI 1000 Base-T on hardware
and also in simulation.
Following are the demo design features:
•
Simulation model for CoreTSE_AHB loopback design.
•
CoreTSE_AHB loopback design on SmartFusion2 Security Evaluation Kit.
The following section explains the initialization and configuration of CoreTSE_AHB, SERDES_IF, and the
loopback mechanism.
2.2.1.1
High-Speed Serial Interface Configuration
During the design process, CoreTSE_AHB was configured to present a Ten Bit Interface (TBI) to the
SERDESIF block, which is configured for External Physical Coding SubLayer (EPCS) operation using
lane 3 to create an SGMII link to the external physical-layer (PHY) device.
2.2.1.2
CoreTSE_AHB IP MAC Initialization
At power-up, firmware running on the Cortex-M3 processor will initialize control registers in
CoreTSE_AHB and the external PHY device to place them in 1000 Base-T mode.
2.2.1.3
Ethernet Packet Loopback Mechanism
The following Ethernet loopback mechanism is used in this demo:
2.2.1.3.1
Ethernet Packet Reception
CoreTSE_AHB receives the Ethernet packet from the on-board Ethernet PHY through high-speed
SERDES_IF.
CoreTSE_AHB receive (RX) path is connected to LSRAM through the AHB interface. The Cortex- M3
processor moves the Ethernet packet data to the LSRAM memory using DMA.
DG0637 Demo Guide Revision 3.0
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