Demo Design Description; Loop Test; Manual Test - Microsemi SmartFusion2 Demo Manual

SmartFusion2 SoC FPGA - Error Detection and Correction of eSRAM Memory
2.3

Demo Design Description

Each eSRAM within the MSS is protected by a dedicated EDAC controller. EDAC detects a 1-bit error or
2-bit error when data is read from the memory. If EDAC detects the 1-bit error, the EDAC controller
corrects the same error bit. If EDAC is enabled for all the 1-bit and 2-bit errors, corresponding error
counters in the system registers are incremented and corresponding interrupts and error bus signals to
the FPGA fabric are generated.
In a single event upset (SEU) susceptible environment, random access memory (RAM) is prone to
transient errors caused by heavy ions. This happens in real-time. To demonstrate this, an error is
introduced manually and detection and correction is observed.
This demo design involves implementation of following tasks:
• Enable EDAC
• Write data to eSRAM
• Read data from eSRAM
• Disable EDAC
• Corrupt one or two bits
• Write data to eSRAM
• Enable EDAC
• Read the data
• In the case of a 1-bit error, the EDAC controller corrects the error, updates the corresponding status
registers, and gives the data written in step 2 at the read operation done at step 8.
• In the case of a 2-bit error, a corresponding interrupt is generated and the application must correct
the data or take the appropriate action in the interrupt handler. These two methods are
demonstrated in this demo.
Two tests are implemented in this demo: loop test and manual test and they are applicable to both 1-bit
and 2-bit errors.
2.3.1

Loop Test

Loop Test is executed when the SmartFusion2 receives a loop test command from the GUI. Initially, all
the error counters and EDAC related registers are placed in the RESET state.
The following steps are executed for each iteration:
1. Enable the EDAC controller.
2. Write the data to the specific eSRAM memory location.
3. Disable the EDAC controller.
4. Write the 1-bit or 2-bit error induced data to the same eSRAM memory location.
5. Enable the EDAC controller.
6. Read the data from the same eSRAM memory location.
7. Send the 1-bit or 2-bit error detection and 1-bit error correction data in case of 1-bit error to the GUI.
2.3.2

Manual Test

This method allows manual testing for enabling or disabling EDAC and write or read operation. Using this
method, 1-bit or 2-bit errors can be introduced to any location within the eSRAM. Enable the EDAC and
write data to the specified address using the GUI fields. Disable the EDAC and write 1-bit or 2-bit
corrupted data to the same address location. Enable the EDAC and read the data from the same address
location then the LED on the board toggles to notify the detection and correction of errors. The
corresponding error counter is displayed on the GUI. The GUI Serial Console logs all the actions
performed in SmartFusion2.
DG0388 Demo Guide Revision 10.0 4