Smartfusion2 Soc Fpga Coretse_Ahb 1000 Base-T Loopback Demo; Design Requirements - Microsemi SmartFusion2 Demo Manual

SmartFusion2 SoC FPGA CoreTSE_AHB 1000 Base-T Loopback Demo

2 SmartFusion2 SoC FPGA CoreTSE_AHB
1000 Base-T Loopback Demo
Microsemi Triple-Speed Ethernet MAC, CoreTSE_AHB is a configurable soft intellectual property (IP)
core that complies with the IEEE 802.3 standard.
This demo design provides an Ethernet solution for the SmartFusion
CoreTSE_AHB-based 1000 Base-T loopback design on the SmartFusion2 Security Evaluation Kit.
CoreTSE_AHB enables system designers to implement a broad range of Ethernet designs, from low-
cost 10/100 Ethernet to higher-performance 1 gigabit ports. CoreTSE_AHB suits networking equipments
such as switches, routers, and data acquisition systems. CoreTSE is also available in a version that
works with IGLOO
CoreTSE_AHB has the following interfaces:
• 10/100/1000 Mbps Ethernet MAC with a gigabit media independent interface (GMII) and ten bit
interface (TBI) to support serial gigabit media independent interface (SGMII), 1000BASE-T, and
1000BASE-X
• GMII or TBI physical layer interface connects to Ethernet PHY
• MAC data path interface
• Advanced peripheral bus (APB) slave interface for MAC configuration registers and status counter
access
CoreTSE_AHB can be configured as GMII or TBI for Ethernet network at 10/100/1000 Mbps data
transfer rates (line speeds).
The CoreTSE IP is available in two different versions:
• CoreTSE_AHB: Uses AHB interface for both the transmit and receive paths. This IP works for
SmartFusion2 SoC FPGA.
• CoreTSE (Non-AMBA): Uses direct access to the MAC with a streaming packet interface. This IP
works for IGLOO2 FPGA and SmartFusion2 SoC FPGA.
CoreTSE and CoreTSE_AHB are identical to MSS hard Ethernet MAC in SmartFusion2 with respect to
the supported features, register configuration, and register addresses. Multiple instances of the CoreTSE
IP can be used to achieve Ethernet solutions in SmartFusion2 devices. The CoreTSE_AHB IP, along with
MSS Ethernet MAC, can be used to support multiple Ethernet interfaces for SmartFusion2 devices. For
more information about CoreTSE_AHB, see to the
For more information about Ethernet applications, see the
Application Note.
Note: CoreTSE_AHB requires a license for use in the Libero
email to soc_marketing@microsemi.com.
2.1

Design Requirements

The following table lists the design requirements for running the demo.
Table 1 •
Hardware Requirements
SmartFusion2 Security Evaluation Kit:
Host PC or Laptop (12 GB RAM)
Spirent Test Center (Optional)
®
2 FPGA family.
Design Requirements
• 12 V adapter
• FlashPro4
programmer
DG0637 Demo Guide Revision 3.0
®
2 SoC FPGA and implements a
CoreTSE_AHB Handbook.
AC423: SmartFusion2/IGLOO2 Ethernet
®
SoC design suite. For license request, send an
Description
Rev D or later
Windows 64-bit Operating System
2