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Summary of Contents for Microsemi IGLOO2
- Page 1 AC393 Application Note Board and Layout Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs...
- Page 2 Within the USA: +1 (800) 713-4113 with the Buyer. Microsemi does not grant, explicitly or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such information itself or anything described by such information. Information provided in this...
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Page 3: Table Of Contents
Revision 0 ............... . 3 2 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs ..4 Design Considerations . - Page 4 3 Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design 38 Power Supply ..............38 Core Supply (VDD) .
- Page 5 Creating Schematic Symbols with User Defined Pin Names ....... . . 76 4.2.1 Exporting Pin Information from the Libero Design .
- Page 6 Figures Figure 1 Power Supplies ..............5 Figure 2 Impedance of Three Capacitors in Parallel .
- Page 7 Figure 55 Capacitor Pad Reference Plane ........... 58 Figure 56 Typical Topology for SLA Simulation .
- Page 8 Tables Table 1 Device-Package Combinations Without SERDES_x_VDD Pin ......6 Table 2 Power Supply Decoupling Capacitors ..........7 Table 3 Recommended Capacitors .
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Page 9: Revision History
Table 19, page 35. • AC394: Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design was added as a part of Board Design guidelines itself. Revision 11.0 The following is a summary of changes made in revision 11.0 of this document. -
Page 10: Revision 10.0
Revision History Revision 10.0 The following is a summary of the changes made in revision 10.0 of this document. • Updated Power Supplies, page 4 (SAR 77745 and SAR 79670). • Updated Table 6, page 15 (SAR 78887). • Updated SPI Master Programming, page 24 (SAR 75910). -
Page 11: Revision 5.0
Added the Configuring Pins in Open Drain section. 1.12 Revision 3.0 The following is a summary of the changes made in revision 3.0 of this document. • Updated the content for IGLOO2 devices (SAR 48630). • Updated Power Supply Sequencing, page 9. -
Page 12: Board Design Guidelines For Smartfusion2 Soc And Igloo2 Fpgas
SerDes protocols. This document assumes that the reader has a good understanding of the SmartFusion2/IGLOO2 device, is experienced in digital and analog board design, and knows about the electrical characteristics of systems. -
Page 13: Figure 1 Power Supplies
PLL (0 or 1). The PLL RC values shown in the figure are applicable to all variants of SmartFusion2/IGLOO2 devices. For the device to operate successfully, power supplies must be free from unregulated spikes and the associated grounds must be free from noise. -
Page 14: Power Supply Decoupling
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs • VPPNVM: eNVM supply for the device. This pin must be connected to the VPP supply. • VREFx: Reference voltage for MDDR/FDDR signals, which is powered through the corresponding bank supply (VDDIx). Can be DNC or grounded (VSS) when unused. -
Page 15: Figure 2 Impedance Of Three Capacitors In Parallel
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Ceramic capacitors are preferred for high-frequency noise elimination and tantalum capacitors for low- frequency noise elimination. • For values ranging from 1 nF to 100 µF, use X7R or X5R (dielectric material) type capacitors. - Page 16 See Figure 1, page 5 for power supply schematics design. The following table lists the recommended decoupling capacitors for the SmartFusion2/IGLOO2 devices. For placement and routing details, see Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design, page 38.
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Page 17: Power Supply Sequencing
VDD refers to the supply voltage to the SmartFusion2/IGLOO2 device core and VDDI refers to the supply voltage to the bank I/O buffers and I/O logic. - Page 18 Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 4 • I/O Glitch during Power-up Glitch Observation with Test observed 10 KΩ Pull-Down Case Output Test Condition (Yes or No) Comments Resistor Case 1 Output VPP and DEVRSTB No glitch observed driving are constant at 3.3V;...
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Page 19: I/O Glitch During Power-Down
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Table 4 • I/O Glitch during Power-up (continued) Glitch Observation with Test observed 10 KΩ Pull-Down Case Output Test Condition (Yes or No) Comments Resistor Case 9 Output VPP and DEVRSTB... -
Page 20: I/O Glitch In A Blank Device
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs To minimize I/O glitch during power-down, any one of the following solutions can be used: • The device must enter Flash*Freeze mode before a device reset asserted. • In the power-down sequence, VDDI must be powered-down first and then the DEVRST_N must be asserted. -
Page 21: Unused Pin Configurations
VREFx can be left floating (DNC) even though the corresponding bank supply is still powered. To allow a SmartFusion2/IGLOO2 device to exit from reset, some of the bank supplies (VDDIx) must always be powered, even if associated bank I/O are unused (as shown in... -
Page 22: Figure 4 Recommendations For Unused Pin Configurations
This change does not effect the old board design functionality. For recommendations on unused VDDI supplies, see the following tables. SmartFusion2/IGLOO2 devices have multiple bank supplies. In cases where specific banks are not used, Microsemi recommends connecting them as listed in the following tables. -
Page 23: Table 6 Recommendation For Bank Supplies For Fc1152, Fg896, Fg676, Fcs536, Fcv484 Packages
10 KΩ resistor or a 10 K Ω resistor can be used for each VDDI# bank, it completely depends on the board layout. For the previous design the unused VDDI# pins were DNC, and cannot create functionality issue. Microsemi recommends connecting to Ground to improve the board reliability. -
Page 24: Table 7 Recommendation For Bank Supplies For Fg484 Package
10 KΩ resistor or a 10 K Ω resistor can be used for each VDDI# bank, it completely depends on the board layout. For the previous design the unused VDDI# pins were DNC, and cannot create functionality issue. Microsemi recommends connecting to Ground to improve the board reliability. -
Page 25: Limiting Surge Current During Device Reset
10 KΩ resistor or a 10 K Ω resistor can be used for each VDDI# bank, it completely depends on the board layout. For the previous design the unused VDDI# pins were DNC, and cannot create functionality issue. Microsemi recommends connecting to Ground to improve the board reliability. -
Page 26: Table 10 Surge Current On Vdd During Devrst_N Assertion (No Decoupling Capacitors On Board)
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs SmartFusion2/IGLOO2 device reset can be activated either directly through an external DEVRST_N pin or indirectly through the tamper macro IP. When the device reset is asserted, the system controller immediately puts the FPGA core in inactive state. During this operation, depending on the board design layout and decoupling capacitors used, there may be additional surge current on the VDD power rail. -
Page 27: Clocks
• Main crystal oscillator • Auxiliary (RTC) crystal oscillator All IGLOO2 devices and the M2S050 SmartFusion2 device only have a main crystal oscillator; they do not have an auxiliary (RTC) crystal oscillator. Table 13 • Clock Circuit SmartFusion2 SoC Part... -
Page 28: Figure 5 Crystal Oscillator
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs The following table lists the output frequency range of the main crystal oscillator with different possible sources. Table 14 • Crystal Oscillator Output Frequency Range Source Output Frequency Range Crystal 32 kHz to 20 MHz... -
Page 29: Auxiliary (Rtc) Crystal Oscillator
For detailed information, see the UG0449: SmartFusion2 and IGLOO2 Clocking Resources User Guide. Auxiliary (RTC) crystal oscillator is not available in the IGLOO2 device. Reset Circuit SmartFusion2/IGLOO2 devices have a dedicated asynchronous Schmitt-trigger reset input pin (DEVRST_N) with a maximum slew rate not faster than1 µs. This active-low signal should be asserted only when the device is unresponsive due to some unforeseen circumstances. -
Page 30: Figure 8 Reset Circuit
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs assert this pin during a programming (including eNVM) operation, as it may cause severe consequences including corruption of the device configuration. Asserting this signal tristates all user I/O and resets the system. -
Page 31: Device Programming
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Device Programming The SmartFusion2/IGLOO2 device can be programmed via one of two dedicated interfaces: JTAG or SPI. These two interfaces support the following programming modes: • Auto-programming (master) mode • In-system programming: •... -
Page 32: Spi Master Programming
The embedded system controller contains a dedicated SPI block for programming, which can operate in master or slave mode. In master mode, the SmartFusion2/IGLOO2 device interfaces with the external SPI flash from which programming data is downloaded. In slave mode, the SPI block communicates with a remote device that initiates download of programming data to the device. -
Page 33: Figure 12 Spi Master Mode Programming
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Figure 12 • SPI Master Mode Programming 3.3 V VDDIOy y=bank number where this pin is located 10 K 10 K 3.3 V 3 Pin Jumper 10 K External Flash FLASH_GOLDEN_N... -
Page 34: Spi Slave Programming
Mfr.: Samtec Inc SerDes SmartFusion2/IGLOO2 SerDes I/O reside in dedicated I/O banks. The number of SerDes I/O depends on the device size and pin count. For example, the M2S050T/M2GL050T device has two SerDes blocks (SERDES0 and SERDES1), which reside in bank 6 and bank 9 out of 10 I/O banks. The M2S010T/M2GL010T device has a single SerDes block (SERDES0), which resides in I/O bank 5. -
Page 35: Pci Express (Pcie)
For non-PCIe applications, the SmartFusion2/IGLOO2 device requires the receive inputs to be AC coupled to prevent common-mode mismatches between devices. Suitable values (for example, 0.1 µF... -
Page 36: Serdes Reference Clock Requirements
Figure 1, page 5 for an illustration of a typical power supply connection. • The DC series resistance of this filter should be limited. Microsemi recommends limiting the voltage drop across this device to less than 5% under worst-case conditions. •... -
Page 37: Mddr/Fddr Impedance Calibration
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs The following table lists the differences between LPDDR, DDR2, and DDR3. Table 17 • LPDDR/DDR2/DDR3 Parameters Parameter LPDDR DDR2 DDR3 VDDQ 1.8 V 1.8 V 1.5 V VTT, VREF 0.9 V 0.75 V... -
Page 38: Vref Power
Figure 17, page 31 and Figure 18, page 32 show the connectivity of the SmartFusion2/IGLOO2 LPDDR interface and a 32-bit DDR2 interface respectively. AC393 Application Note Revision 14.0... -
Page 39: Figure 17 Lpddr Interface
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Figure 17 • LPDDR Interface SmartFusion2/IGLOO2 xDDR_DQS [1:0] xDDR_DM_RDQS [1:0] xDDR_DQ [15:0] xDDR_BA [2:0] xDDR_ADDR [14:0] 16 LPDDR SDRAM Control lines CKE, CS, WE, RAS, CAS xDDR_CLK xDDR_CLK_N 16 LPDDR SDRAM... -
Page 40: Ddr3 Guidelines
40 Ω, 60 Ω, and 140 Ω. VTT pull-up is not necessary. Characteristic impedance: Zo is typically 50 Ω, and Zdiff (differential) is 100 Ω. • DDR3 interfacing with SmartFusion2/IGLOO2 devices for 8-bit and 16-bit interfaces is shown in Figure 19, page 33 and Figure 20, page 33. -
Page 41: Figure 19 8-Bit Ddr3 Interface
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs Figure 19 • 8-Bit DDR3 Interface SmartFusion2/ IGLOO2 Clock DDR3 DDR3 DDR3 DDR3 SDRAM SDRAM SDRAM SDRAM Address and Command DQ Group 0 DQ Group 1 DQ Group 2 DQ Group 3... -
Page 42: User I/O And Clock Pins
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs 2.10 User I/O and Clock Pins The following table lists recommendations for unused I/O and clock pins in a SmartFusion2/IGLOO2 device. Table 18 • Recommendations for Unused I/O and Clock Pins... -
Page 43: Obtaining A Two-Rail Design For Non-Serdes Applications
+2.5 V or +3.3 V. 2.11.1 Operating Voltage Rails SmartFusion2/IGLOO2 devices require +1.2 V for the core supply and either +2.5 V or +3.3 V for I/O and analog supplies. The following table lists operating voltage requirements for the devices. Table 19 •... -
Page 44: Configuring Pins In Open Drain
2.13 Brownout Detection (BOD) SmartFusion2/IGLOO2 functionality is guaranteed only if VDD is above the recommended level specified in the datasheet. Brownout occurs when VDD drops below the minimum recommended operating voltage. As a result, it is not possible to ensure proper or predictable device operation. The design might continue to malfunction even after the supply is brought back to the recommended values, as parts of the device might have lost functionality during brownout. -
Page 45: Simultaneous Switching Noise
Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs SmartFusion2/IGLOO2 devices do not have a built-in brownout detection circuitry, but an external brownout detection circuitry can be implemented as shown in the following figure. Figure 23 • BOD Circuit Implementation... -
Page 46: Layout Guidelines For Smartfusion2- And Igloo2-Based Board Design
This chapter provides guidelines for the hardware board layout that incorporates SmartFusion2 SoC FPGA or IGLOO2 FPGA devices. Good board layout practices are required to achieve the expected performance from the printed circuit boards (PCB) and SmartFusion2/IGLOO2 devices. These are essential to achieve high quality and reliable results such as low-noise levels, signal integrity, impedance, and power requirements. -
Page 47: Core Supply (Vdd)
The De-coupling capacitor and the Smart Fusion2\IGOOL2 device can be placed side by side. If placed side by side, route the power with thick traces. Microsemi does not guarantee on noise on power rails. User must run the power simulation. -
Page 48: Plane Layout
Figure 25 • Capacitor Placement under BGA Vias 3.2.2 Plane Layout Microsemi recommends using the VDD plane, as shown in the following figure. Note: The plane can be routed in multiple ways. The goal is to have a dedicated and low-impedance plane. Figure 26 • VDD Plane 3.2.3... -
Page 49: Serdes
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design Figure 27 • Impedance Profile of VDD Plane with Respect to Frequency Z Amplitude (Ω) 0.01 1e-4 2e-4 1e-3 2e-3 0.01 0.02 0.2 0.3 Frequency (GHz) VDD Plane with Decoupling Capacitors VDD Plane without Decoupling Capacitors... -
Page 50: Figure 28 Filter Circuit For Serdes Pll Power Supply
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design 3.3.1.3 SerDes PLL There are two power supply nodes required for SerDes. One is SERDES_x_VDDAPLL and another is SERDES_x_PLL_VDDA. Both of these supplies require separate filter circuits. Filter circuit for SERDES_x_VDDAPLL is shown in the following figure. A typical filter circuit for SERDES_x_PLL_VDDA is shown in the following figure. -
Page 51: Plane Layout
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design 3.3.2 Plane Layout 3.3.2.1 SerDes Core Power (SERDES_x_VDD) Even though SERDES0 and SERDES1 cores share the same power supply, separate planes must be made while connecting to corresponding SerDes blocks, as shown in the following figure. This reduces the noise coupling between SERDES0 and SERDES1 blocks. -
Page 52: Simulations
• The connections of 1.2 kΩ resistor and SERDES_1_L01_REXT of SmartFusion2/IGLOO2 should not be routed as a thick plane. It must be routed as a signal trace in-order to meet minimum capacitance requirement of the SERDES_1_L01_REXT pin. The length of the trace should be as short as possible. -
Page 53: Figure 33 Impedance Profile Of Serdes_X_Vdd Plane Over Frequency Range
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design Figure 33 • Impedance Profile of SERDES_x_VDD Plane Over Frequency Range Z Amplitude (Ω) 1e-4 2e-4 1e-3 2e-3 0.01 0.02 0.2 0.3 Frequency (GHz) SERDES_x_VDD with Decoupling Capacitors SERDES_x_VDD without Decoupling Capacitors 3.3.3.2... -
Page 54: Ddr
Apart from that, it requires VREF voltage for an internal reference. Noise on VREF impacts the read performance of SmartFusion2/IGLOO2 devices. VREF lines should not be routed near the aggressive nets or switching power supplies. For more information about DDR memory layout guidelines, see the Micron DDR3 Memory Layout Guidelines. -
Page 55: Figure 35 Layout Of Vref5
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design The following figure shows the VREF5 used for MDDR. Figure 35 • Layout of VREF5 3.4.2.2 VDDIO The shape of the plane does not have a specific requirement. The width of the plane should be sufficient to carry the required current. -
Page 56: Simulations
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design Figure 37 • Layout of VDDIO5 Plane 3.4.3 Simulations Ω, The target impedance of the DDR VDDIO is calculated as 240 m based on the values (see Power Supply, page 38): •... -
Page 57: Figure 38 Impedance Profile Of Vddio0 Plane Over Frequency Range
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design Figure 38 • Impedance Profile of VDDIO0 Plane Over Frequency Range Z Amplitude (Ω) 0.01 1e-4 2e-4 1e-3 2e-3 0.01 0.02 0.2 0.3 Frequency (GHz) Impedance of VDDIO0 with Decoupling Capacitors Impedance of VDDIO0 without Decoupling Capacitors Figure 39 •... -
Page 58: Pll
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design To achieve a reasonable level of long term jitter, it is vital to deliver an analog grade power supply to the PLL. An R-C or R-L-C filter is used with the C being composed of multiple devices to achieve a wide spectrum of noise absorption. -
Page 59: Plane Layout
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design 3.5.2 Plane Layout • Plane routing for PLL0VDDA and PLL0VSSA is shown in the following figure. These are with respect to the schematic, as shown in Figure 40, page 50. • The capacitor (22 µF) and series resistor should be placed near the device as close as possible to the 0.1 µF cap. -
Page 60: I/O Power Supply
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design Figure 43 • PLL0VDDA Plane Impedance Z Amplitude (Ω) 0.01 1e-4 2e-4 1e-3 2e-3 0.01 0.02 0.2 0.3 Frequency (GHz) PLL0VDDA impedance with Filter Capacitors I/O Power Supply 3.6.1 Component Placement •... -
Page 61: Simulations
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design 3.6.3 Simulations The target impedance of the VDDIO1 plane is calculated as 330 m Ω based on the following values (see Power Supply, page 38): • = 3.3 V, SUPPLY • = 500 mA trans •... -
Page 62: Programming Power Supply (Vpp Or Vccenvm)
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design Programming Power Supply (VPP or VCCENVM) VPP is used as an input for the internal charge pump that generates the required voltage to program flash. VCCENVM is an embedded non-volatile memory (eNVM) supply. -
Page 63: High-Speed Serial Link (Serdes)
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design High-Speed Serial Link (SerDes) 3.8.1 Layout Considerations 3.8.1.1 Differential Traces A well designed differential trace not must have the following qualities: • Mismatch in impedance • Insertion loss and return loss •... -
Page 64: Via
The attenuation due to skin effect is increased proportional to the square root of frequency. The roughness courses this loss proportional to frequency. Microsemi recommends instructing the PCB fabrication house to use smooth copper, if the frequency exceeds 2 Gbps. -
Page 65: Figure 51 Via Illustration
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design Figure 51 • Via Illustration Anti-Pad Dielectric Typ. Barrel Copper Stub Planes Typ. • Number of vias on different traces should be avoided or minimized. SerDes signals should be routed completely on a single layer with the exception of via transitions from component layer to the routing layer (3-via maximum). -
Page 66: Dc Blocking Capacitors
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design Figure 53 • Via-to-Via Pitch Wide Placement GOOD! Vias are narrowly spaced • Symmetrical ground vias (return vias) should be used to reduce discontinuity for Common mode signal component, as shown in the following figure. Common mode of part of the signal requires continuous return path RX to TX and GND. -
Page 67: Considerations For Simulation
The following steps describe how to run the serial channel simulations: 3.9.1 Step 1: Gathering the Required Files 3.9.1.1 IBIS-AMI Models The IBIS-AMI models of SmartFusion2/IGLOO2 and the IBIS-AMI models of IC that will be interfaced with SmartFusion2/IGLOO2 can be downloaded from the Microsemi website: • www.microsemi.com/soc/download/ibis/SmartFusion2.aspx •... -
Page 68: Step 3: Configuration Of Ami Model
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design • PCB: S-parameter model of SmartFusion2 Development Kit SerDes Traces • RX_PRIMARY: S-parameter model of either the connector or the IBIS model of the receiver IC device Once all the model files are imported into the topology, the default configuration in the AMI model should be left to calculate the appropriate coefficients by the tool and then to run the simulations. -
Page 69: Step 4: Results
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design • t2: Post-cursor tap. The range is from -0.5 to -0.01, default value is -0.01. • TapsFromFile: Explicit feed forward equalizer (FFE) coefficients can be set through this file. If a file is used, it overrides the manual tap settings and automatic generation. -
Page 70: Figure 59 Expected Results From Simulations (Eye Diagram, Eye Contour, And Bath Tub Curve)
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design This simulation is on the SmartFusion2 Development Kit using the Sigrity tool and the waveforms are shown in the following figure. The simulation result shows that it meets the PCIe 2.0 requirements Figure 59 •... -
Page 71: Ddr3 Layout Guidelines
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design 3.10 DDR3 Layout Guidelines 3.10.1 Placement It is required to ensure that the placement for the DDR3 memories looks like L (shape), where, memories are at the bottom of the L and controllers are on the top of the L. This gives enough space to route the DQ signals with less number of layers. -
Page 72: Ac393 Application Note Revision 14.0
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design 3.10.2.1 Data Group Signal Routing • The data signals should not be over the split planes. • The reference plane for data signals should be GND plane and should be contiguous between memory and SmartFusion2/IGLOO2. -
Page 73: Simulation Considerations
3.10.3.1 Step 1: Gathering the Required Files 3.10.3.1.1 IBIS Models To download the IBIS models of SmartFusion2/IGLOO2 and the IBIS-AMI models of DDR3 memory which is going to interface with SmartFusion2/IGLOO2, see the following web pages on the Microsemi website: •... -
Page 74: Figure 63 Ddr3 Simulation Topology
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design 3.10.3.1.2 PCB Trace Models The PCB file needs to be converted into a compatible format of simulator software. For example, .HYP file format of PCB is required to simulate in Hyperlynx and SPD file format of PCB is required to simulate in Sigrity. -
Page 75: Figure 64 List Of Reports Generated By Hyperlynx
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design The simulation tool generates the report where all the details are available. For example, Hyperlynx generates the set of excel sheets which contain all setup and hold margin, overshoot, and undershoot information for all corners. It also generates driver and receiver waveforms for all the nets. -
Page 76: References
Layout Guidelines for SmartFusion2- and IGLOO2-Based Board Design Figure 66 • Setup and Time Margins for DQ and DQS Signals Hold Setup Setup Hold Time Margin Time Margin Vref 3.11 References • Power Distribution Network (PDN) by Eric Bogatin •... -
Page 77: Creating Schematic Symbols Using Cadence Orcad Capture Cis For Smartfusion2 And Igloo2 Designs
I/Os. Creating Schematic Symbols using Pin Assignment Tables (PAT) 4.1.1 Preparing the PAT Layout File for Import into OrCAD Capture Download the PAT files from the following path in the Microsemi website under Datasheets section: • www.microsemi.com/products/fpga-soc/soc-fpga/smartfusion2#documents • www.microsemi.com/products/fpga-soc/fpga/igloo2-fpga#documents Open the *Pin_Assignment_Table_Public.xlsx file. -
Page 78: Figure 68 Example Pat Spreadsheet - Editing Stage
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs Figure 68 • Example PAT Spreadsheet - Editing Stage Add the following headings for the columns. See Figure 69, page 71: • Number • Name • Type •... -
Page 79: Figure 69 Example Pat Spreadsheet - Final Stage
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs • Short Dot • Short Dot clock • Short • Zero Length The default shape for most of the FPGA symbol pins is LINE. 10. Leave the Pin Group column blank. -
Page 80: Generating A Orcad Capture Schematic Symbol
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs Recommendations for arranging pins in the Section column: • Arrange individual bank pins in separate sections • Arrange all power supply pins in one section • Arrange all ground pins in one section •... -
Page 81: Figure 71 Example Pat Spreadsheet - Final Stage
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs From the Example PAT Spreadsheet, select and copy all the cells, excluding the column headers as shown in the following figure. Figure 71 • Example PAT Spreadsheet - Final Stage... -
Page 82: Figure 72 New Part Creation Spreadsheet Dialog With Data
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs Select the top left cell of New Part Creation Spreadsheet dialog and paste the copied data. Check if all the columns match between the Example PAT Spreadsheet and New part creation Spreadsheet dialog as shown in the following figure. -
Page 83: Figure 74 Schematic Symbol - First Section
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs Double-click the part that is created to display the first section as shown in the following figure. Figure 74 • Schematic Symbol - First Section You can navigate to all the sections that are created. -
Page 84: Creating Schematic Symbols With User Defined Pin Names
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs Creating Schematic Symbols with User Defined Pin Names 4.2.1 Exporting Pin Information from the Libero Design Launch Libero and open project. For more information about how to use the System Builder wizard in the Libero design, see http://coredocs.s3.amazonaws.com/Actel/Tool/SysBuilder/sf2_system_builder_ug_1.pdf... -
Page 85: Figure 78 I/O Editor
The I/O Editor dialog lists the port names with the updated pin names as shown in the following figure. The pin names that are not modified follow the Microsemi pin naming convention. Note: For the I/O Editor dialog to open, the design must be synthesized and compiled. -
Page 86: Preparing The Pin List For Import Into Orcad Capture Cis
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs The report is stored in the project directory. The path is: <Libero Project Directory>\designer\project\export\<project Name>_top_pinrpt_number.rpt. 4.2.2 Preparing the Pin List for Import into OrCAD Capture CIS Launch Microsoft Excel, and open the *.rpt file that has the exported pin information. Before you open, ensure that All Files (*.*) is the file type as shown in the following figure. -
Page 87: Figure 82 Importing Pin Names To The Spreadsheet-Step 2
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs In the Text Import Wizard - Step 2 dialog, select the following as Delimiters and click Next: • • Space • I as other Figure 82 • Importing Pin Names to the Spreadsheet—Step 2 Click Finish to import the data in separate columns. -
Page 88: Figure 84 Spreadsheet With The Pin Names Imported
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs Retain the columns A, B, F and delete the remaining columns as they are not required for generating schematic symbols. Figure 84 • Spreadsheet with the Pin Names Imported Add the following headings for the columns. -
Page 89: Generating A Capture Schematic Symbol
Creating Schematic Symbols Using Cadence OrCAD Capture CIS for SmartFusion2 and IGLOO2 Designs The default shape for most of the FPGA symbol pins is the LINE. 10. Leave the Pin Group column blank. 11. In the Position column, enter one of the following positions according to the requirement: •... -
Page 90: Board Design And Layout Checklist
Board Design and Layout Checklist This chapter provides a set of checks for designing hardware using Microsemi SmartFusion2 and IGLOO2 FPGAs. The checklists provided in this chapter are a high-level summary to assist the design engineers in the design process. -
Page 91: Ac393 Application Note Revision 14.0
Power Analysis Perform power analysis and check the results against the power budget. (Microsemi Power Calculator can be used to analyze the power consumption. Estimate the dynamic and static power consumption, and ensure that the design does not violate the power budget.) -
Page 92: Ac393 Application Note Revision 14.0
For unused conditions of power supply pins, see the corresponding pin assignment table available on the following pages: SmartFusion2 SoC FPGA Documentation IGLOO2 FGPA Documentation Also see Figure 4, page 14. Brownout Detection (BOD) Circuit Ensure that brownout detection is implemented standalone or included as part of power management circuitry. -
Page 93: Ac393 Application Note Revision 14.0
– Auxiliary (RTC) crystal oscillator (not available in the M2S050T) RC Oscillators (Internal) – 1-MHz RC oscillator – 50-MHz RC oscillator IGLOO2 devices have only main crystal oscillator without auxiliary (RTC) crystal oscillator. For more information about crystal oscillators, see Table 14, page 20. -
Page 94: Ac393 Application Note Revision 14.0
– EPCS: 125 MHz – SERDES TXD: The transmit pair must alone have AC-coupling capacitors near the SmartFusion2/IGLOO2 device. AC-coupling capacitors of 75-200 nF are required for link detection. If the SerDes unit is unused, these pins must remain floating (DNC). -
Page 95: Ac393 Application Note Revision 14.0
This pin is differentially paired with FLASH_GOLDEN_N, which is always input only. For more information, see the following documents: – IGLOO2 Pin Descriptions – SmartFusion2 Pin Descriptions One internal signal can be allocated for probing (for example, towards the oscilloscope feature). The two live probe I/O cells are dual-purpose. They can be used for the live probe functionality or used as user I/Os (MSIO). -
Page 96: Ac393 Application Note Revision 14.0
I/O Pin Assignment Use a spreadsheet to capture the list of design I/Os. Microsemi provides detailed pinout information that can be downloaded from the website and customized to store the pinout information for specific designs. -
Page 97: Layout Checklist
Are enough number of decoupling capacitors used for DDRx core and VTT supply? For more information about DDRx core and VTT supply, see Board Design Guidelines for SmartFusion2 SoC and IGLOO2 FPGAs, page 4. Is one 0.1 µF cap for two VTT termination resistors used for DDRx? -
Page 98: Appendix: Special Layout Guidelines - Crystal Oscillator
Appendix: Special Layout Guidelines - Crystal Oscillator The placement of the crystal needs to be close to the SmartFusion2 or IGLOO2 device. Two capacitors are to be placed symmetrically around the crystal so that the lengths from the crystal pad to capacitor are equal, as shown in the following figure. -
Page 99: Appendix: Stack-Up
Signal integrity depends on how well the traces have controlled impedance, so it is always recommended to have controlled impedance. Microsemi recommends that all critical high-speed signals like DDR and PCIe signals need to have ground reference. All signal layers should be separated from each other by ground or power planes. This minimizes crosstalk and provides balanced and clean transmission lines with properly controlled characteristic impedance between devices and other board components. -
Page 100: Figure 88 Stack-Up Used In Development Board
Appendix: Stack-Up Figure 88 • Stack-up Used in Development Board Lamination Stack-up: Thickness and Tolerance: Base Material Requirements: L#/Type: Description: Cu+: Lamination/PrePreg: Type: Description: Core 0.0040 Q/H .00035 .0040 NP 4000-13EP 1 Mix .00060 2 Pin Pre-Preg (1 x 2113) .0034 NP 4000-13EP .0035... -
Page 101: Appendix: Dielectric Material
Appendix: Dielectric Material Appendix: Dielectric Material The impedance of the traces depends on the geometry of the traces and the dielectric material used. The skew of the signal depends on the dielectric constant and loss of signal strength depends on the loss tangent of the material. -
Page 102: Appendix: Power Integrity Simulation Topology
Appendix: Power Integrity Simulation Topology Appendix: Power Integrity Simulation Topology The following figure shows the topology that is considered for simulating the power plane for power integrity analysis. Figure 90 • Power Integrity Simulation Topology Bulk Caps Voltage Bulk Regulator Caps Module (VRM) Im pedance of the...
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