Memory Architecture - Sun Microsystems Sun Blade 150 Service Manual

C.9

Memory Architecture

The Sun Blade 150 system uses a 168-pin, JEDEC standard, dual-in-line, 3.3V,
unbuffered, synchronous DRAM module. The memory control unit (MCU) is
embedded within the CPU. All address signals, control signals, and clocks are
driven off of the processor and directly drive the memory subsystem on the
motherboard.
The CPU L2 cache megacell reserves a 4 Gbyte region for cacheable main memory.
The memory controller only supports 4 Gbytes of space.
Note – Although the cache and memory controller support up to 4 Gbytes, only
512 MB DIMMS are supported on the Sun Blade 150 system. This limits the
maximum DIMM configuration to 2 Gbytes.
The system has four DIMM slots on the motherboard. Because the memory data bus
width is equal to the DIMMs (64-bit data, plus 8-bit ECC) they can be installed one
at a time and with mixed sizes. The interface between processor and memory sub-
system on the motherboard consists of:
Two sets of multiplexed row-column address bank select address.
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Two sets of bank address
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Four RAS
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Four CAS
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Four WE
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Eight clocks
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Eight CS
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FIGURE C-11
C-18 Sun Blade 150 Service Manual • June 2002
describes the system memory interface.