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3.4.6.5
J5 Connector
•
PICMG 2.16 Link Port 9 to Link Port 19 (10/100/1000Base-T)
Table 3-11:
Connector J5 Pinout
Pin
Row A
22
FL_DA19+
FL_DA19-
21
FL_DB19+
FL_DB19-
20
FL_DA18+
FL_DA18-
19
FL_DB18+
FL_DB18-
18
FL_DA17+
FL_DA17-
17
FL_DB17+
FL_DB17-
16
FL_DA16+
FL_DA16-
15
FL_DB16+
FL_DB16-
14
FL_DA15+
FL_DA15-
13
FL_DB15+
FL_DB15-
12
FL_DA14+
FL_DA14-
11
FL_DB14+
FL_DB14-
10
FL_DA13+
FL_DA13-
9
FL_DB13+
FL_DB13-
8
FL_DA12+
FL_DA12-
7
FL_DB12+
FL_DB12-
6
FL_DA11+
FL_DA11-
5
FL_DB11+
FL_DB11-
4
FL_DA10+
FL_DA10-
3
FL_DB10+
FL_DB10-
2
FL_DA9+
FL_DA9-
1
FL_DB9+
FL_DB9-
3.5
Write Protection Feature
The CP6924 supports hardware driven write protection for all non-volatile memory devices. Depending on the device, the
protection is implemented either by a dedicated write protection signal, by disabling the write enable signal, or by the
whole interface.
Two levels of hardware write protection are supported: standard and enhanced. The protection level is set by a backplane
signal (EWP). It is located on connector J4, pin A9. If left open, the signal is inactive. If pulled to GND, the signal is active.
The following table shows how to configure the write protection. Default setting is 'standard'.
EWP Signal
Inactive (3.3V or open)
Active (GND)
38
Row B
Row C
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
Write Protection Level
Standard
Enhanced
Row D
Row E
FL_DC19+
FL_DC19-
FL_DD19+
FL_DD19-
FL_DC18+
FL_DC18-
FL_DD18+
FL_DD18-
FL_DC17+
FL_DC17-
FL_DD17+
FL_DD17-
FL_DC16+
FL_DC16-
FL_DD16+
FL_DD16-
FL_DC15+
FL_DC15-
FL_DD15+
FL_DD15-
FL_DC14+
FL_DC14-
FL_DD14+
FL_DD14-
FL_DC13+
FL_DC13-
FL_DD13+
FL_DD13-
FL_DC12+
FL_DC12-
FL_DD12+
FL_DD12-
FL_DC11+
FL_DC11-
FL_DD11+
FL_DD11-
FL_DC10+
FL_DC10-
FL_DD10+
FL_DD10-
FL_DC9+
FL_DC9-
FL_DD9+
FL_DD9-
CP6924-1 User Guide
Row F
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
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