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•
10/100/1000Base-T Management Port via Copper PHY BCM54610 connected to FP RJ45
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2x UART connects to CPLD
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Configuration EEPROM
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I2C Interface and SPI Interface to CPLD
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NVRAM write protection
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PPC405EX supports JTAG Boundary Scan
1.1.1.3
IPMI
•
NXP LPC2368 32-Bit Microcontroller
•
PICMG 2.9 / IPMI 1.5 compliant
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Dual Image Support
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2 MByte Flash (Boot Image)
•
64 kByte EEPROM (FRU)
•
Board Voltage and current monitoring
•
Board Temperature monitoring via I²C enabled sensors
•
Switchable pull ups at IPMB0/1 backplane signals
1.1.1.4
Power Supply
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5V and 3.3V only board, no 12V or -12V required
•
IPMB_PWR used for 3.3V PM (generated by LDO)
•
Hot Swap support
•
3V3 V stabilization
•
Point of Load Converters for chip core voltages
1.1.1.5
Miscellaneous
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JTAG Boundary Scan support
•
Board layout is prepared for conduction cooling
•
All parts are extended temperature range parts: -40°C to +85°C or better
1.1.2
General compliances
The Board is compatible to the following standards:
•
PICMG® 2.0 R3.0 CompactPCI® Specification, as amended by ERN 2.0-3.0-002
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PICMG® 2.1 R2.0 CompactPCI® Hot Swap Specification
•
PICMG® 2.9 R1.0 CompactPCI® System Management Specification
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PICMG® 2.16 R1.0 Sep. 5, 2005 Packet Switching Backplane Specification
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Intelligent Platform Management Interface Specification V1.5
•
IEEE 802.3, 2008 section 3
•
IEEE 802.3 2008 section 4 Clause 47 XGMII Extender Sublayer (XGXS) and 10 Gigabit Attachement Unit Interface
(XAUI)
13
CP6924-1 User Guide
www.kontron.com
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