Intel Stratix 10 Configuration User Manual page 46

Table 17. Parameter Settings for New CFI Flash Device
Parameter
CFI flash device name
CFI flash device ID
CFI flash manufacturer ID
CFI flash extended device ID
Flash device is Intel compatible
Typical word programming time
Maximum word programming time
Typical buffer programming time
Maximum buffer programming time
Note: You must specify either the word programming time parameters, buffer
4. Click OK to save the parameter settings.
5. After you add, update, or remove the new CFI flash memory device, click OK.
The Windows registry stores user flash information. Consequently, you must have
system administrator privileges to store the parameters in the Define New CFI Flash
Device window in the Intel Quartus Prime Pro Edition Programmer.
3.1.6.3. Parameters
Table 18. PFL II General Parameters
Options
Operating mode • Flash Programming and FPGA
Configuration
• Flash Programming
• FPGA Configuration
Targeted flash • CFI Parallel Flash
device
Tri-state flash • On
bus
• Off
Table 19. PFL II Flash Interface Setting Parameters
Options
Number of flash • CFI Parallel Flash: 1–16
devices used
Largest flash • CFI Parallel Flash: 8 Mbit–2 Gbit
density
Intel Stratix 10 Configuration User Guide
46
Define the CFI flash name
Specify the CFI flash identifier code
Specify the CFI flash manufacturer identification number
Specify the CFI flash extended device identifier, only applicable for AMD-
compatible CFI flash memory device
Turn on the option if the CFI flash is Intel compatible
Typical word programming time value in µs unit
Maximum word programming time value in µs unit
Typical buffer programming time value in µs unit
Maximum buffer programming time value in µs unit
programming time parameters, or both. Do not leave both programming
time parameters with the default value of zero.
Value
Value
3. Intel Stratix 10 Configuration Schemes
Description
Description
Specifies the operating mode of flash programming and FPGA
configuration control in one IP core or separate these functions
into individual blocks and functionality.
Specifies the flash memory device connected to the PFL II IP
core.
Allows the PFL II IP core to tri-state all pins interfacing with the
flash memory device when the PFL II IP core does not require
access to the flash memory.
Description
Specifies the number of flash memory devices connected to the
PFL II IP core.
Specifies the density of the flash memory device to be
programmed or used for FPGA configuration. If you have more
than one flash memory device connected to the PFL II IP core,
specify the largest flash memory device density.
UG-S10CONFIG | 2018.11.02
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