Texas Instruments SimpleLink CC3200MOD Manual page 39

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4.11.2.5 IEEE 1149.1 JTAG
The Joint Test Action Group (JTAG) port is an IEEE standard that defines a test access port (TAP) and
boundary scan architecture for digital integrated circuits and provides a standardized serial interface to
control the associated test logic. For detailed information on the operation of the JTAG port and TAP
controller, see the IEEE Standard 1149.1,Test Access Port and Boundary- Scan Architecture.
Figure 4-15 shows the JTAG timing diagram.
TCK
TMS
TDI
TDO
Table 4-12 lists the JTAG timing parameters.
PARAMETER PARAMETER
NUMBER
J1
J2
J3
J4
J7 tTMS_SU
J8 tTMS_HO
J9 tTDI_SU
J10 tTDI_HO
J11 tTDO_HO
4.11.2.6 ADC
Table 4-13 lists the ADC electrical specifications.
PARAMETER
Nbits Number of bits
INL Integral nonlinearity
DNL Differential nonlinearity
Input range
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J2
J7 J8
TMS Input Valid
J9 J10
TDI Input Valid
J11
TDO Output Valid
Figure 4-15. JTAG Timing
Table 4-12. JTAG Timing Parameters
PARAMETER NAME
fTCK Clock frequency
tTCK Clock period
tCL Clock low period
tCH Clock high period
TMS setup time
TMS hold time
TDI setup time
TDI hold time
TDO hold time
Table 4-13. ADC Electrical Specifications
DESCRIPTION
Worst-case deviation from
histogram method over full scale
(not including first and last three
LSB levels)
Worst-case deviation of any step
from ideal
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J3
J7 J8
TMS Input Valid
J9 J10
TDI Input Valid
J1
TDO Output Valid
MIN
1
16
1
16
CONDITION AND MIN
ASSUMPTIONS
–2.5
–1
CC3200MOD
SWRS166 – DECEMBER 2014
J4
SWAS031-069
MAX UNIT
15 MHz
1/fTCK ns
tTCK/2 ns
tTCK/2 ns
15
TYP MAX
12
2.5
4
0 1.4
Specifications
UNIT
Bits
LSB
LSB
V
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