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CC3200MOD
SWRS166 – DECEMBER 2014
3.5
Drive Strength and Reset States for Analog-Digital Multiplexed Pins
Table 3-4
describes the use, drive strength, and default state of these pins at first-time power up and reset
(nRESET pulled low).
Table 3-4. Drive Strength and Reset States for Analog-Digital Multiplexed Pins
Board Level Configuration
Pin
and Use
Connected to the enable pin
25
of the RF switch (ANTSEL1).
Other use not recommended.
Connected to the enable pin
26
of the RF switch (ANTSEL2).
Other use not recommended.
44
Generic I/O
42
Generic I/O
Analog signal (1.8 V
47
absolute, 1.46 V full scale)
Analog signal (1.8 V
48
absolute, 1.46 V full scale)
Analog signal (1.8 V
49
absolute, 1.46 V full scale)
Analog signal (1.8 V
50
absolute, 1.46 V full scale)
3.6
Pad State After Application of Power To Chip But Prior To Reset Release
When a stable power is applied to the CC3200 chip for the first time or when supply voltage is restored to
the proper value following a prior period with supply voltage below 1.5 V, the level of the digital pads are
undefined in the period starting from the release of nRESET and until DIG_DCDC powers up. This period
is less than approximately 10 ms. During this period, pads can be internally pulled weakly in either
direction. If a certain set of pins are required to have a definite value during this pre-reset period, an
appropriate pullup or pulldown must be used at the board level. The recommended value of this external
pull is 2.7 KΩ.
22
Terminal Configuration and Functions
Default State at First Power
Up or Forced Reset
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
Analog is isolated. The digital Determined by the I/O state,
I/O cell is also isolated.
ADC is isolated. The digital
I/O cell is also isolated.
ADC is isolated. The digital
I/O cell is also isolated.
ADC is isolated. The digital
I/O cell is also isolated.
ADC is isolated. The digital
I/O cell is also isolated.
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State after Configuration of
Analog Switches (ACTIVE,
LPDS, and HIB Power
Modes)
as are other digital I/Os.
as are other digital I/Os.
as are other digital I/Os.
as are other digital I/Os.
Determined by the I/O state,
as are other digital I/Os.
Determined by the I/O state,
as are other digital I/Os.
Determined by the I/O state,
as are other digital I/Os.
Determined by the I/O state,
as are other digital I/Os.
Copyright © 2014, Texas Instruments Incorporated
www.ti.com
Maximum Effective Drive
Strength (mA)
4
4
4
4
4
4
4
4
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