Texas Instruments SimpleLink CC3200MOD Manual page 35

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4.11.2.1.2 SPI Slave
Figure 4-10 shows the timing diagram for the SPI slave.
CLK
MISO
MOSI
Table 4-5 lists the timing parameters for the SPI slave.
PARAMETER PARAMETER
NUMBER
I1 F
I2 Tclk
I3 tLP
I4 tHT
I5 D
I6 tIS
I7 tIH
I8 tOD
I9 tOH
(1) Timing parameter assumes a maximum load of 20 pF at 3.3 V.
4.11.2.2 McASP
The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio
applications and supports transfer of two stereo channels over two data pins. The McASP consists of
transmit and receive sections that operate synchronously and have programmable clock and frame-sync
polarity. A fractional divider is available for bit-clock generation.
4.11.2.2.1 I2S Transmit Mode
Figure 4-11 shows the timing diagram for the I2S transmit mode.
Copyright © 2014, Texas Instruments Incorporated
I3 I2 I4
Figure 4-10. SPI Slave Timing Diagram
Table 4-5. SPI Slave Timing Parameters
(1)
PARAMETER NAME
Clock frequency @ VBAT = 3.3 V
Clock frequency @ VBAT ≤ 2.1 V
Clock period
Clock low period
Clock high period
Duty cycle
RX data setup time
RX data hold time
TX data output delay
TX data hold time
I2
McACLKX
McAFSX
McAXR0/1
Figure 4-11. I2S Transmit Mode Timing Diagram
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I6 I7
I8
MIN
50
45%
4
4
I1 I3
I4 I4
CC3200MOD
SWRS166 – DECEMBER 2014
I9
SWAS032-017
MAX UNIT
20 MHz
12
25
25
55%
20
24
SWAS032-015
Specifications
ns
ns
ns
ns
ns
ns
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