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Appendix B. FEC (FORWARD
ERROR CORRECTION) OPTIONS
B.1
FEC Overview
The CDD-880 Multi Receiver Router uses, as its FEC (Forward Error Correction) method, a family
of short-block, very low latency, Low Density Parity Check (LDPC) codes called VersaFEC
VersaFEC is ideal for lower data rates that demand the shortest possible latency. It is a patent
pending technology wholly owned and developed by Comtech EF Data and Comtech AHA
Enterprise Products Group (the VersaFEC name is a trademark registered to Comtech AHA).
B.2
VersaFEC (Short-block LDPC)
While LDPC coding represents a significant development in the area of FEC and its performance
is exceptional in terms of coding gain, its higher latency is considered disadvantageous in some
applications.
Comtech EF Data's development of LDPC incorporated research into ways to reduce the block
size of LDPC (and hence its latency) while preserving the coding gain performance very close to
the Shannon bound. The result is development of a set of VersaFEC codes with two distinct
purposes:
1. To provide an expanded choice of combinations of modulation and coding that significantly
reduces latency without compromising coding gain performance.
2. To provide combinations of modulation and coding (MODCODs), which are suitable for not
only Constant Coding and Modulation (CCM) applications, but are also the basis for a patent-
pending Adaptive Coding and Modulation (ACM) system.
VersaFEC offers a sufficient range of code rates and modulation types that optimize link
performance under most conditions. Figure B-1 compares the performance of the VersaFEC codes
with the Shannon bound. Note that the chart uses SNR in place of Eb/No – a convention for
comparing ACM MODCODs. SNR is defined as
Eb/No + 10
(Spectral Efficiency)
log
B–1
®
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