Serial Communication Test Set-Up - TDK-Lambda Genesys User Manual

D. Status Event Register (SEVE?)
The Status Event Register will set a bit if a change in the Power Supply status occurs
and it is enabled. The register is cleared when the "SEVE?" or "CLS" commands are
received. A change in this register will generate SRQ.
BIT Status name
0 (LSB)
Constant Voltage
1
Constant Current
2
No Fault
3
Fault active
4
Auto-Restart enabled
5
Fold enabled
6
Spare
7 (MSB)
Local Mode

8.12. Serial Communication Test Set-Up

Use the following instructions as basic set-up to test the serial communication operation.
8.12.1. Equipment:
8.12.2. PC set-up:
8.12.3. Power Supply Set-Up:
Connect the power supply to the PC using the RS-232 cable.
Set via the front panel: Baud rate: 9600, Address: 06 (default).
Set via the rear panel: RS-232/RS-485 to RS-232 (refer to Section 8.2.3).
Table 8-15: Status Event Register (SEVE?)
Status symbol
CV
CC
NFLT
FLT
0
0
0
LCL
PC with Windows Hyper Terminal, software installed, Genesys
Power supply, RS-232 cable.
2.1 Open Hyper Terminal.........................New Connection
2.2 Enter a name
2.3 Connect to....................................... Direct to Com 1 or Com 2
2.4 Configure port properties:
2.5 Open Properties in the program
2.6 Setting: ASCII Set Up
Select Echo characters locally, select send line ends with line
feed. On some PC systems, pressing the number keypad
"Enter" will distort displayed messages. Use the alphabetic
"Enter" instead.
93
83532002 Rev C
Bit Set condition
Changes in status
occurs and it is
enabled.
The change can set a
bit, but when the
change clears the bit
remains set.
Entire Event Register is cleared
when user sends "SEVE?"
command to read the register.
Always zero
"CLS" and power-up also clear
the Status Event Register.
Always zero
Always zero
Unit is set to Local by
pressing front panel
REM/LOC button
Bits per second......9600
Data bits...............8
Parity...................None
Stop bits...............1
Flow control..........None
File.....................Properties
Bit reset condition
TM