Table 2-27 Additional Operations - ARM ARM946E-S Technical Reference Manual

2.3.16 Register 15, Cache debug index register
ARM DDI 0155A
Reading the test state register returns bits [12:0] in the least significant bits. The 19 most
significant bits are unpredictable. Writing the test state register updates only bits [12:9].
In debug you must be able to execute code without causing linefills to update the
caches, primarily to load new code into memory. This means that
cache, must update the memory and the cache, and that for
prefetches that miss, a linefill is not performed. When set, bits [10:9] prevent the
respective cache from performing a linefill on a cache miss. The memory mapping, as
seen by the ARM9E-S or by the programmer, is unchanged. This improves the
performance of single-stepping when in debug.
When set, bits [12:11] prevent the respective cache from streaming data to the
ARM9E-S while the linefill is performed to the cache. The linefill still occurs, but the
prefetched instruction or load data is returned to the core at the end of a linefill.
Register 15 gives you access to the test features included within the ARM946E-S.
Additional instructions and operations are required to support debug operations within
the cache. Instructions for the additional operations are listed in Table 2-27.
Function
Write CP15 cache debug index
register
Read CP15 cache debug index
register
Instruction TAG write
Instruction TAG read
Data TAG write
Copyright © ARM Limited 2000. All rights reserved.
Table 2-26 Test state register bit assignments (continued)
Bit
10
9
8:0
Data Instruction
Index/
MCR p15, 3, rd, c15, c0, 0
segment
Index/ MRC p15, 3, rd, c15, c0, 0
segment
Data
MCR p15, 3, rd, c15, c1, 0
Data
MRC p15, 3, rd, c15, c1, 0
Data
MCR p15, 3, rd, c15, c2, 0
Programmer's Model
Function
Disable DCache linefill
Disable ICache linefill
Reserved
, if they hit the
STRs
or instruction
LDRs

Table 2-27 Additional operations

2-31