Chapter 30 Cautions For Wait; Cautions For Wait - NEC 78K0 User Manual

30.1 Cautions for Wait

This product has two internal system buses.
One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware.
Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data
may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
When accessing the peripheral hardware that may cause a conflict, therefore, the CPU repeatedly executes
processing, until the correct data is passed.
As a result, the CPU does not start the next instruction processing but waits. If this happens, the number of
execution clocks of an instruction increases by the number of wait clocks (for the number of wait clocks, refer to Table
30-1). This must be noted when real-time processing is performed.

CHAPTER 30 CAUTIONS FOR WAIT

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