NEC 78K0 User Manual page 104

(5) Oscillation stabilization time counter status register (OSTC)
This is the status register of the X1 input clock oscillation stabilization time counter. If the Ring-OSC clock is used
as the CPU clock, the X1 input clock oscillation stabilization time can be checked.
OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset is released (reset by RESET input, POC, LVI, clock monitor, and WDT), the STOP instruction,
MSTOP = 1, and MCC = 1 clear OSTC to 00H.
Figure 5-6. Format of Oscillation Stabilization Time Counter Status Register (OSTC)
Address: FFA3H After reset: 00H
Symbol 7
OSTC 0
MOST11
1
1
1
1
1
Cautions 1. After the above time has elapsed, the bits are set to 1 in order from MOST11 and
Remarks 1. Values in parentheses are reference values for operation with f
104
CHAPTER 5 CLOCK GENERATOR
R
6 5
0 0
MOST13 MOST14
0 0
1 0
1 1
1 1
1 1
remain 1.
2. If the STOP mode is entered and then released while the Ring-OSC clock is being
used as the CPU clock, set the oscillation stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time
set by OSTS
The X1 oscillation stabilization time counter counts up to the oscillation
stabilization time set by OSTS. Note, therefore, that only the status up to the
oscillation stabilization time set by OSTS is set to OSTC after STOP mode is
released.
3. The wait time when STOP mode is released does not include the time after STOP
mode release until clock oscillation starts ("a" below) regardless of whether
STOP mode is released by RESET input or interrupt generation.
STOP mode release
X1 pin voltage
waveform
2. f : X1 input clock oscillation frequency
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User's Manual U16227EJ2V0UD
4 3
MOST11 MOST13 MOST14
MOST15 MOST16 Oscillation stabilization time status
11
0 0 2 /f
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13
0 0 2 /f
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14
0 0 2 /f
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15
1 0 2 /f
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16
1 1 2 /f
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a
2 1 0
MOST15 MOST16
µ
min. (204.8 s min.)
µ
min. (819.2 s min.)
min. (1.64 ms min.)
min. (3.27 ms min.)
min. (6.55 ms min.)
= 10 MHz.
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