NEC 78K0 User Manual page 372

Figure 21-6. Example of Software Processing After Release of Reset (1/2)
• If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage
Checking cause
(set to 50 ms)
Check stabilization
Note 1
Change CPU clock
No
50 ms has passed?
(TMIFH1 = 1?)
Notes 1. If reset is generated again during this period, initialization processing is not started.
2. A flowchart is shown on the next page.
372
CHAPTER 21 LOW-VOLTAGE DETECTOR
; The
Reset
; The cause of reset (power-on-clear, WDT, LVI, or clock monitor)
Note 2
of reset
can be identified by the RESF register.
LVI
; 8-bit timer H1 can operate with the Ring-OSC clock.
Start timer
Source: f
(f
R
; Check the stabilization of oscillation of the X1 input clock by using the
of oscillation
OSTC register.
; Change the CPU clock from the Ring-OSC clock to the X1 input clock.
; TMIFH1 = 1: Interrupt request is generated.
Yes
Initialization
; Initialization of ports
processing
User's Manual U16227EJ2V0UD
Ring-OSC clock is set as the CPU clock when the reset signal is generated
× compare value 200 = 53 ms
7
(480 kHz (MAX.))/2
R
: Ring-OSC clock oscillation frequency)