NEC 78K0 User Manual page 342

(2) STOP mode release
Figure 17-5. Operation Timing When STOP Mode Is Released
STOP mode release
STOP mode
X1 input clock
Ring-OSC clock
X1 input clock is
selected as CPU clock
when STOP instruction
is executed
Ring-OSC clock is
selected as CPU clock
when STOP instruction
is executed
The STOP mode can be released by the following two sources.
(a) Release by unmasked interrupt request
When an unmasked interrupt request is generated, the STOP mode is released.
stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried
out. If interrupt acknowledgment is disabled, the next address instruction is executed.
Figure 17-6. STOP Mode Release by Interrupt Request Generation (1/2)
Standby release signal
Status of CPU
X1 input clock
342
CHAPTER 17 STANDBY FUNCTION
HALT status
(oscillation stabilization time set by OSTS)
Ring-OSC clock
Operation stopped
(17/f )
R
(1) When X1 input clock is used as CPU clock
STOP
instruction
Operating mode
STOP mode
(X1 input clock)
Oscillation stopped
Oscillates
User's Manual U16227EJ2V0UD
X1 input clock
X1 input clock
Clock switched
by software
Wait
(set by OSTS)
Oscillation stabilization wait
(HALT mode status)
Oscillates
Oscillation stabilization time (set by OSTS)
After the oscillation
Operating mode
(X1 input clock)