Appendix D Revision History; Major Revisions In This Edition - NEC 78K0 User Manual

D.1 Major Revisions in This Edition
Page
Throughout Addition of products
µ
PD78F0114(A1), 780111(A2), 780112(A2), 780113(A2), 780114(A2)
Modification of names of the following special function registers (SFRs)
• Ports 0 to 3, 6, 7, 12, and 13 → Port registers 0 to 3, 6, 7, 12, and 13
p.21 Addition of Caution 3 to 1.4 Pin Configuration (Top View)
p.23 Modification of 1.5 K1 Family Lineup
p.29 Modification of outline of timer in and addition of Remark to 1.7 Outline of Functions
p.30 Addition of Table 2-1 Pin I/O Buffer Power Supplies
p.36 Modification of descriptions in 2.2.9 AV
p.38 Modification of the following contents in Table 2-2 Pin I/O Circuit Types
• Modification of recommended connection when P60 to P63 are not used
• Modification of I/O circuit type of P62 and P63
• Addition of Note to AV
• Modification of recommended connection when V
p.56 Modification of Figure 3-14 Data to Be Saved to Stack Memory
p.57 Modification of Figure 3-15 Data to Be Restored from Stack Memory
p.69 Modification of [Description example] in 3.4.4 Short direct addressing
Addition of [Illustration] to 3.4.7 Based addressing, 3.4.8 Based indexed addressing, and 3.4.9 Stack
pp.72 to 74
addressing
p.75 Addition of Table 4-1 Pin I/O Buffer Power Supplies
p.77 Modification of Table 4-3 Port Configuration
p.85 Modification of Figure 4-9 Block Diagram of P20 to P27
p.91 Addition of Remark to Figure 4-15 Block Diagram of P130
p.92 Deletion of input switch control register (ISC) from and addition of port registers (P0 to P3, P6, P7, P12, P13)
to 4.3 Registers Controlling Port Function
p.96 Partial modification of descriptions in 4.4.1 (1) Output mode, 4.4.3 (1) Output mode, and (2) Input mode
p.98 Modification of Figure 5-1 Block Diagram of Clock Generator
p.99 Addition of Note to 5.3 (1) Processor clock control register (PCC)
Addition of Cautions 2 and 3 to Figure 5-6 Format of Oscillation Stabilization Time Counter Status
p.104
Register (OSTC)
pp.106 to 108 Modification of Figure 5-8 Examples of External Circuit of X1 Oscillator, Figure 5-9 Examples of
External Circuit of Subsystem Clock Oscillator, and Figure 5-10 Examples of Incorrect Resonator
Connection
p.113 Modification of Notes 4 and 5 in Figure 5-13 Status Transition Diagram (2)
p.115 Modification of Note 4 and illustration in Figure 5-13 Status Transition Diagram (4)
p.116 Modification of Table 5-3 Relationship Between Operation Clocks in Each Operation Status
p.119 Modification of Note in Figure 5-14 Switching from Ring-OSC Clock to X1 Input Clock (Flowchart)
p.121 Addition of Note to Figure 5-16 Switching from X1 Input Clock to Subsystem Clock (Flowchart)
p.124 Revision of CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00

APPENDIX D REVISION HISTORY

Description
and 2.2.16 V
REF
REF
User's Manual U16227EJ2V0UD
(flash memory versions only)
PP
is not used
PP
(1/3)
481