NEC 78K0 User Manual page 347

Ring-OSC clock
X1 input clock
CPU clock Normal operation
RESET
Internal
reset signal
Port pin
Note The port pins become high impedance, except for P130, which is set to low-level output.
Figure 18-3. Timing of Reset Due to Watchdog Timer Overflow
Ring-OSC clock
X1 input clock
CPU clock
Normal operation
Watchdog timer
overflow
Internal
reset signal
Port pin
Note The port pins become high impedance, except for P130, which is set to low-level output.
Caution A watchdog timer internal reset resets the watchdog timer.
CHAPTER 18 RESET FUNCTION
Figure 18-2. Timing of Reset by RESET Input
Reset period
(Oscillation stop)
Delay
Reset period
(Oscillation stop)
User's Manual U16227EJ2V0UD
Operation stop
Normal operation
(17/f )
(Reset processing, Ring-OSC clock)
R
Delay
Note
Hi-Z
Operation stop
Normal operation
(17/f )
(Reset processing, Ring-OSC clock)
R
Note
Hi-Z
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