NEC 78K0 User Manual page 127

Table 6-2. CR000 Capture Trigger and Valid Edges of TI000 and TI010 Pins
(1) TI000 pin valid edge selected as capture trigger (CRC001 = 1, CRC000 = 1)
CR000 Capture Trigger
Falling edge
Rising edge
No capture operation
(2) TI010 pin valid edge selected as capture trigger (CRC001 = 0, CRC000 = 1)
CR000 Capture Trigger
Falling edge
Rising edge
Both rising and falling edges
Remarks 1. Setting ES001, ES000 = 1, 0 and ES101, ES100 = 1, 0 is prohibited.
2. ES001, ES000:
ES101, ES100:
CRC001, CRC000: Bits 1 and 0 of capture/compare control register 00 (CRC00)
Cautions 1. Set a value other than 0000H in CR000 in the mode in which clear & start occurs on a match
of TM00 and CR000. However, in the free-running mode and in the clear mode using the
valid edge of TI000, if CR000 is cleared to 0000H, an interrupt request (INTTM000) is
generated when the value of CR000 changes from 0000H to 0001H following overflow
(FFFFH).
2. When P01 is used as the valid edge input pin of TI010, it cannot be used as the timer output
(TO00). Moreover, when P01 is used as TO00, it cannot be used as the valid edge input pin
of TI010.
3. When CR000 is used as a capture register, read data is undefined if the register read time
and capture trigger input conflict (the capture data itself is the correct value).
If count stop input and capture trigger input conflict, the captured data is undefined.
4. Do not rewrite CR000 during TM00 operation.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
Rising edge
Falling edge
Both rising and falling edges
Falling edge
Rising edge
Both rising and falling edges
Bits 5 and 4 of prescaler mode register 00 (PRM00)
Bits 7 and 6 of prescaler mode register 00 (PRM00)
User's Manual U16227EJ2V0UD
TI000 Pin Valid Edge
ES001
0
0
1
TI010 Pin Valid Edge
ES101
0
0
1
ES000
1
0
1
ES100
0
1
1
127