NEC 78K0 User Manual page 114

(3) When "Ring-OSC cannot be stopped" is selected by mask option
Status 3
CPU clock: f
XP
f : Oscillating
XP
f : Oscillating
R
Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
2. When shifting from status 2 to status 1, make sure that MCS is 0.
3. The watchdog timer operates using Ring-OSC even in STOP mode if "Ring-OSC cannot be stopped"
is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer
H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer
overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer
overflow after STOP instruction execution.
4. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
114
CHAPTER 5 CLOCK GENERATOR
Figure 5-13. Status Transition Diagram (3/4)
(when subsystem clock is not used)
Interrupt
Interrupt
HALT
instruction
MCM0 = 0
CPU clock: f
f
XP
Note 1 f
MCM0 = 1
R
Interrupt
STOP
STOP
instruction
instruction
STOP
User's Manual U16227EJ2V0UD
HALT
HALT
HALT instruction
instruction
Interrupt
Status 2
MSTOP = 1
R
: Oscillating
: Oscillating
MSTOP = 0
STOP
instruction
Interrupt
Reset release
Note 3
Status 1
Note 2
CPU clock: f
R
f : Oscillation stopped
XP
f : Oscillating
R
Interrupt
Note 4
Reset