NEC 78K0 User Manual page 115

(4) When "Ring-OSC cannot be stopped" is selected by mask option
Status 5
CPU clock: f
XT
f : Oscillation stopped
XP
f : Oscillating
R
MCC = 0
MCC = 1
HALT instruction
Status 4
CPU clock: f
XT
f : Oscillating
XP
f : Oscillating
R
CSS = 0
Note 4
CSS = 1
Status 3
CPU clock: f
f : Oscillating
XP
f : Oscillating
R
Notes 1. Before shifting from status 2 to status 3 after reset and STOP are released, check the X1 input clock
oscillation stabilization time status using the oscillation stabilization time counter status register
(OSTC).
2. When shifting from status 2 to status 1, make sure that MCS is 0.
3. The watchdog timer operates using Ring-OSC even in STOP mode if "Ring-OSC cannot be stopped"
is selected by a mask option. Ring-OSC division can be selected as the count source of 8-bit timer
H1 (TMH1), so clear the watchdog timer using the TMH1 interrupt request before watchdog timer
overflow. If this processing is not performed, an internal reset signal is generated at watchdog timer
overflow after STOP instruction execution.
4. The operation cannot be shifted between subsystem clock operation and Ring-OSC operation.
5. All reset sources (RESET input, POC, LVI, clock monitor, and WDT)
CHAPTER 5 CLOCK GENERATOR
Figure 5-13. Status Transition Diagram (4/4)
(when subsystem clock is used)
Interrupt
Interrupt
HALT instruction
Interrupt
Note 4
HALT
instruction
MCM0 = 0
XP
Note 1
MCM0 = 1
Interrupt
STOP
instruction
User's Manual U16227EJ2V0UD
HALT
HALT
Interrupt instruction
Interrupt
MSTOP = 1
Status 2
CPU clock: f
R
f : Oscillating
XP
MSTOP = 0
f : Oscillating
R
instruction
STOP Interrupt
instruction
Note 3
STOP
HALT instruction
Status 1
Note 2
CPU clock: f
f : Oscillation stopped
XP
f : Oscillating
R
STOP
Interrupt
Reset release
Note 5
Reset
R
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