NEC 78K0 User Manual page 356

(CLME = 1 is set after RESET input and at the end of X1 input clock oscillation stabilization time)
Normal
operation
CPU operation
X1 input clock
Ring-OSC clock
RESET
CLME
Clock monitor status
Monitoring
RESET input clears bit 0 (CLME) of the clock monitor mode register (CLM) to 0 and stops the clock monitor
operation. When CLME is set to 1 by software at the end of the oscillation stabilization time (reset value of OSTS
16
register is 05H (2 /f )) of the X1 input clock, monitoring is started.
XP
(CLME = 1 is set when CPU clock operates on X1 input clock and before entering STOP mode)
Normal
operation
CPU operation
X1 input clock
(CPU clock)
Ring-OSC clock
CLME
Clock monitor status
Monitoring
When bit 0 (CLME) of the clock monitor mode register (CLM) is set to 1 before entering STOP mode, monitoring
automatically starts at the end of the X1 input clock oscillation stabilization time. Monitoring is stopped in STOP mode
and during the oscillation stabilization time.
356
CHAPTER 19 CLOCK MONITOR
Figure 19-3. Timing of Clock Monitor (2/4)
(3) Clock monitor status after RESET input
Clock supply
Reset stopped
17 clocks
(4) Clock monitor status after STOP mode is released
Oscillation stabilization time
STOP
Oscillation Oscillation stabilization time
stopped
(time set by OSTS register)
Monitoring stopped
User's Manual U16227EJ2V0UD
Normal operation (Ring-OSC clock)
Oscillation stabilization time
Monitoring stopped
Set to 1 by software
Monitoring
Normal operation
Monitoring