NEC 78K0 User Manual page 321

(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)
These registers specify the valid edge for INTP0 to INTP5.
EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
RESET input clears these registers to 00H.
Figure 15-5. Format of External Interrupt Rising Edge Enable Register (EGP)
Address: FF48H After reset: 00H
Symbol 7
EGP 0
Address: FF49H After reset: 00H
Symbol 7
EGN 0
EGPn
0
0
1
1
Table 15-3 shows the ports corresponding to EGPn and EGNn.
Detection Enable Register
EGP0
EGP1
EGP2
EGP3
EGP4
EGP5
Caution Select the port mode after clearing EGPn and EGNn to 0 because an edge may be detected when
the external interrupt function is switched to the port function.
Remark n = 0 to 5
CHAPTER 15 INTERRUPT FUNCTIONS
and External Interrupt Falling Edge Enable Register (EGN)
R/W
6 5 4
0 EGP5 EGP4
R/W
6 5 4
0 EGN5 EGN4
EGNn INTPn pin valid edge selection (n = 0 to 5)
0 Edge detection disabled
1 Falling edge
0 Rising edge
1 Both rising and falling edges
Table 15-3. Ports Corresponding to EGPn and EGNn
Edge Detection Port
EGN0 P120
EGN1 P30
EGN2 P31
EGN3 P32
EGN4 P33
EGN5 P16
User's Manual U16227EJ2V0UD
3 2 1
EGP3 EGP2 EGP1
3 2 1
EGN3 EGN2 EGN1
Interrupt Request Signal
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
0
EGP0
0
EGN0
321