Customizing The Test Bench - Xilinx LogiCORE Getting Started Manual

SGMII Example Design / Dynamic Switching Example Design
Demonstration Test Bench
Figure 4-12
PCS/PMA or SGMII Core in SGMII mode.
Figure 4-12: Demonstration Test Bench for the Ethernet 1000BASE-X PCS/PMA or
The demonstration test bench is described in the following files:
VHDL
Verilog
The demonstration test bench is a simple VHDL or Verilog program to exercise the
example design and the core itself. The demonstration test bench performs the following
tasks.
•
•
•
•
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006
illustrates the demonstration test bench for the Ethernet 1000BASE-X
Demonstration Testbench
GMII
Stimulus
GMII
Monitor
project_dir>/<component_name>/simulation/demo_tb.vhd
project_dir>/<component_name>/simulation/demo_tb.v
Input clock signals are generated.
A reset is applied to the example design.
The Ethernet 1000BASE-X PCS/PMA core is configured through the MDIO interface
by injecting an MDIO frame into the example design. This disables Auto-Negotiation
and takes the core out of Isolate state.
The following frames are injected into the GMII transmitter by the GMII stimulus
block at 1 Gbps.
www.xilinx.com
DUT
RocketIO
GMII
Configuration
Stimulus
Control and data structures
SGMII Core in SGMII Mode
PMA
Monitor
(serial to parallel
conversion and
8B10B
decoding)
PMA
Stimulus
(8B10B encoding
and parallel to
serial
conversion)
R
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