Transceiver; Transmitter Elastic Buffer - Xilinx LogiCORE Getting Started Manual

Core Example Design Using RocketIO
The example design HDL top-level connects the GMII of the core to external IOBs and the
PHY side interface of the core directly to a RocketIO instance. This configuration allows the
functionality of the core to be demonstrated using a simulation package as discussed in
this guide. The example design can also be synthesized and, if required, placed on a
suitable board and demonstrated in hardware.

Transceiver

A wrapper file for the Virtex-II Pro RocketIO or Virtex-4 Multi-Gigabit Transceiver is
described in the following files:
VHDL
Verilog
This file instances a Virtex-II Pro RocketIO or Virtex-4 RocketIO and applies Gigabit
Ethernet 1000BASE-X attributes to it. This transceiver wrapper is instantiated from the top-
level HDL file for the example design.
For Virtex-4 FX devices only, a Calibration Block is required. See the
Guide
This is decribed in the following files:
VHDL
Verilog

Transmitter Elastic Buffer

The Transmitter Elastic Buffer is described in the following files:
VHDL
Verilog
When the GMII is used externally (as in this example design), the GMII transmit signals
(inputs to the core from a remote MAC at the other end of the interface) are synchronous to
a clock that is likely to be derived from a different clock source to the core. For this reason,
GMII transmit signals must be transferred into the core main clock domain before they can
be used by the core and RocketIO. This is achieved with the Transmitter Elastic Buffer, an
a synchronous FIFO implemented in distributed RAM. The operation of the elastic buffer
is to attempt to maintain a constant occupancy by inserting or removing any idle
sequences. This causes no corruption to the frames of data.
When the GMII is used as an internal interface, it is expected that the entire interface will
be synchronous to a single clock domain and the Transmitter Elastic Buffer should be
discarded. See the LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII User Guide for
information about connecting the core to an internal GMII or an Ethernet MAC.
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006
project_dir>/<component_name>/example_design/transceiver.vhd
project_dir>/<component_name>/example_design/transceiver.v
for more information.
project_dir/<component_name>/example_design/cal_block_v1_2_1.vhd
project_dir/<component_name>/example_design/cal_block_v1_2_1.v
project_dir>/<component_name>/example_design/tx_elastic_buffer.vhd
project_dir>/<component_name>/example_design/tx_elastic_buffer.v
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