Demonstration Test Bench - Xilinx LogiCORE Getting Started Manual

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Demonstration Test Bench

Figure 4-6
TBI.
The demonstration test bench is described in the following files:
VHDL
Verilog
The demonstration test bench is a simple VHDL or Verilog program to exercise the
example design and the core itself.
Core with MDIO Interface
The demonstration test bench performs the following tasks.
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•
•
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illustrates the demonstration test bench for the Ethernet 1000BASE-X PCS with
Demonstration Testbench
GMII
Stimulus
GMII
Monitor
Figure 4-6: Demonstration Test Bench for the Ethernet 1000BASE-X PCS with TBI
project_dir>/<component_name>/simulation/demo_tb.vhd
project_dir>/<component_name>/simulation/demo_tb.v
Input clock signals are generated.
A reset is applied to the example design.
The Ethernet 1000BASE-X PCS/PMA core is configured through the MDIO interface
by injecting an MDIO frame into the example design. This disables Auto-Negotiation
(if present) and takes the core out of the Isolate state.
www.xilinx.com
Chapter 4: Detailed Example Design
DUT
GMII TBI
Configuration
Stimulus
Control and Data Structures
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
TBI
Monitor
(8B10B
decoding)
TBI
Stimulus
(8B10B
encoding)
UG145 January 18, 2006