Core Example Design Using Rocketio; Top-Level Hdl - Xilinx LogiCORE Getting Started Manual

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Core Example Design Using RocketIO

Top-Level HDL

Figure 4-3
PCS/PMA using RocketIO.
Figure 4-3:
The following files describe the top-level example design for the Ethernet 1000BASE-X
PCS/PMA core using a RocketIO core.
VHDL
Verilog
The example design HDL top level contains the following:
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•
•
•
•
•
32
illustrates the example design for a top-level HDL for the Ethernet 1000BASE-X
FPGA
GMII
IOBs
In
Connect to
Client MAC
IOBs
Out
Top-Level HDL for the Ethernet 1000BASE-X PCS/PMA using RocketIO
project_dir>/<component_name>/example_design/<component_name>_top.vhd
project_dir>/<component_name>/example_design/<component_name>_top.v
An instance of the Ethernet 1000BASE-X PCS/PMA core
An instance of a Virtex-II Pro or Virtex-4 RocketIO transceiver
Clock management logic for the core and the RocketIO transceiver, including DCM
and Global Clock Buffer instances
A transmitter elastic buffer
GMII interface logic, including IOB and DDR registers instances, where required
Input and output buffers for other port signals of the top level
www.xilinx.com
Chapter 4: Detailed Example Design
Tx
Elastic
Buffer
Ethernet
1000BASE-X
PCS/PMA
Core
Clock Management
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
Transceiver
PMA
RocketIO
(Connect to
Optical
Transceiver)
UG145 January 18, 2006