Figure 4-8: Sgmii Adaptation Module - Xilinx LogiCORE Getting Started Manual

Ethernet 1000base-x pcs/pma or sgmii v7.0
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SGMII Adaptation Module
The GMII of the core always operates at 125 MHz. The core makes no differentiation
between the three speeds of operation; it always effectively operates at 1 Gbps. However,
at 100 Mbps, every data byte run through the core should be repeated 10 times to achieve
the required bit rate; at 10 Mbps, each data byte run through the core should be repeated
100 times to achieve the required bit rate. Dealing with this repetition of bytes is the
function of the SGMII adaptation module.
The provided SGMII adaptation module
clocks at a frequency of 125 MHz when operating at a speed of 1 Gbps (with no repetition
of data bytes); 12.5 MHz at a speed of 100 Mbps (each data byte is repeated and run
through the core 10 times); 1.25 MHz at a speed of 10 Mbps (each data byte is repeated and
run through the core 100 times).
This GMII-style interface is not a standard interface (true GMII only operates at a clock
frequency of 125 MHz), but it does allow a straightforward internal connection to an
Ethernet MAC core. For example, the SGMII adaptation module can be used to interface
the Ethernet 1000BASE-X PCS/PMA or SGMII LogiCORE, operating in SGMII mode, to
the Xilinx Tri-Mode Ethernet MAC LogiCORE (see the Xilinx LogiCORE Ethernet
1000BASE-X PCS/PMA or SGMII User Guide for more information).
The top-level HDL for the SGMII adaptation module is described in the following files:
VHDL
42
From Client MAC
GMII
Signals to form
SGMII reference
clock
Speed Control
To Client MAC
GMII
userclk2
(125 MHz
reference clock)

Figure 4-8: SGMII Adaptation Module

www.xilinx.com
Chapter 4: Detailed Example Design
(Figure
4-8) creates a GMII-style interface that
SGMII Adaptation Module
Tx Rate Adapt
gmii_txd_out[7:0]
gmii_txd_in[7:0]
gmii_tx_en_in
gmii_tx_en_out
gmii_tx_er_in
gmii_tx_er_out
sgmii_clk_en_fall
clk125m
Rx Rate Adapt
gmii_rxd_in[7:0]
gmii_rxd_out[7:0]
gmii_rx_dv_out
gmii_rx_dv_in
gmii_rx_er_out
gmii_rx_er_in
sgmii_clk_en_fall
clk125m
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
To GMII
Tx input of core
Clock
Generation
sgmii_clk_en_fall
sgmii_clk_r
sgmii_clk_f
speed_is_10_100
clk125m
From GMII
Rx output of core
UG145 January 18, 2006

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