Demonstration Test Bench; Figure 4-11: Receiver Rate Adaptation Module Data Sampling - Xilinx LogiCORE Getting Started Manual

R
At 100 Mbps, the data is repeated for a 10 clock period duration of clk125m; at 10 Mbps,
the data is repeated for a 100 clock period duration of clk125m. The Receiver Rate
Adaptation Module samples this data on the sgmii_clk_en_fall signal produced
from the Clock Generation circuitry. Since this pulse marks the falling edge of sgmii_clk,
it guarantees that setup and hold time is provided for the attached client MAC.
The Receiver Rate Adaptation module also performs a second function that accounts for
the latency inferred in
detected, and if required, it is realigned across the 8-bit data path of gmii_rxd_out[7:0]
before being presented to the attached client MAC. It is possible that this SFD could have
been skewed across two separate bytes by MACs operating on a 4-bit data path.
48
Figure
Speed is 1 Gbps
clk125 m
'1'
sgmii_clk_en_fall
gmii_rxd_in[7:0]
gmii_rxd_out[7:0]
Speed is 100 Mbps
clk125 m
gmii_rxd_in[7:0]
sgmii_clk_en_fall
gmii_txd_out[7:0]
sgmii_clk

Figure 4-11: Receiver Rate Adaptation Module Data Sampling

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Chapter 4: Detailed Example Design
4-11. The 8-bit Start of Frame Delimiter (SFD) code is
D0 D1 D2
D0 D1 D2
D0 D0 D0 D0 D0 D0 D0 D0 D0 D0
D0
10 clk125 m
cycles
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
D1 D1 D1 D1 D1 D1 D1 D1 D1 D1
D1
UG145 January 18, 2006
D2 D2 D2 D2