Core Example Design With Ten-Bit Interface; Example Design Top-Level Hdl - Xilinx LogiCORE Getting Started Manual

R
Changing Frame Error Status
Errors can be inserted into any of the predefined frames in any position by setting the
"error" field to '1' in any column of that frame. Injected errors are automatically updated in
both stimulus and monitor functions.
Changing the Core Configuration
The configuration of the Ethernet 1000BASE-X PCS/PMA core used in the demonstration
test bench can be altered.
Caution:
run indefinitely. For example, the demonstration test bench will not Auto-Negotiate with the example
design. You determine the configurations that can safely be used with the test bench
When the MDIO interface option is selected, the core can be reconfigured by editing the
injected MDIO frame in the demonstration test bench. See the Xilinx LogiCORE Ethernet
1000BASE-X PCS/PMA or SGMII User Guide for more information on using the MDIO
interface.
When the MDIO interface option is not selected, the core can be reconfigured by modifying
the configuration vector directly. See the Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA
or SGMII User Guide for information on using the configuration vector.

Core Example Design with Ten-Bit Interface

Example Design Top-Level HDL

Figure 4-5
Figure 4-5: Example Design Top-Level HDL for the Ethernet 1000BASE-X PCS with
The example design for the Ethernet 1000BASE-X PCS/PMA core with TBI is described in
the following files:
VHDL
36
Certain configurations of the core will cause the test bench to fail or to cause processes to
illustrates the example design for a top-level HDL with a 10-bit interface (TBI).
Connect to
Client MAC
project_dir>/<component_name>/example_design/<component_name>_top.vhd
www.xilinx.com
Chapter 4: Detailed Example Design
FPGA
GMII
Tx
IOBs
Elastic
In
Buffer
Ethernet
1000BASE-X
PCS/PMA
Core
IOBs
Out
Clock Management
TBI
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
.
TBI
IOBs
Out
TBI
IOBs
In
UG145 January 18, 2006