Verilog Design Entry - Xilinx LogiCORE Getting Started Manual

Directory Structure and File Descriptions

Verilog Design Entry

Figure 4-2
Design Entry Project. <project_dir> is the CORE Generator project directory;
<component_name> is the component name as entered in the Core Customization window.
Note:
Project Directory (<project_dir>)
<component_name>.ngc
The Xilinx netlist for the core. This is instantiated by the VHDL example design.
<component_name>.v
The Verilog simulation model used to support the Verilog functional simulation of the
core. This is UNISIM-based.
<component_name>.veo
This contains a Verilog instantiation template for the core.
<component_name>.xco
A log file that records the settings used to generate a core. An XCO file is generated by the
CORE Generator for each core that it creates in the current project directory. An XCO file
can also be used as an input to the CORE Generator.
<component_name>.xcp
Similar to the XCO file except that it does not specify project specific settings such as target
architecture and output products.
<component_name>_flist.txt
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006
shows the files and directories created by CORE Generator system in a Verilog
The implement and simulation/timing directories are only present with the Full License.
<component_name>.ngc
<component_name>.v
<component_name>.veo
<component_name>.xco
<component_name>.xcp
<component_name>_flist.txt
implement.bat
implement.sh
xst.scr
xst.prj
Generated by the implement scripts
Contains the back-annotated vhdl
netlist files.
demo_tb.v
Figure 4-2: Core Directories and Files
www.xilinx.com
<project_dir>
gig_eth_pcs_pma_v7_0_
release_notes.txt
<component_name> gig_eth_pcs_pma_ds264.pdf
gig_eth_pcs_pma_gsg145.pdf
gig_eth_pcs_pma_ug155.pdf
doc
<component_name>_top.v
example_design
<component_name>_top.ucf
Other Example Design
Verilog files
implement
results
simulation simulate_mti.do
wave_mti.do
functional
simulate_ncsim.sh
wave_ncsim.sv
simulate_mti.do
timing
wave_mti.do
simulate_ncsim.sh
wave_ncsim.sv
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