Transmitter Elastic Buffer - Xilinx LogiCORE Getting Started Manual

Core Example Design with Ten-Bit Interface
Verilog
The HDL example design contains the following:
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The example design HDL top level connects the GMII and the TBI of the core to external
IOBs. This allows the functionality of the core to be demonstrated using a simulation
package as described in this guide.
The example design can also be synthesized and placed on a suitable board and
demonstrated in hardware, if required.

Transmitter Elastic Buffer

The Transmitter Elastic Buffer is described in the following files:
VHDL
Verilog
When the GMII is used externally (as in this example design), the GMII transmit signals,
(inputs to the core from a remote MAC at the other end of the interface) are synchronous to
a clock which is likely to be derived from a different clock source to the core. For this
reason, GMII transmit signals must be transferred into the core main clock domain before
they can be used by the core. This is achieved with the Transmitter Elastic Buffer, an
asynchronous FIFO implemented in distributed RAM. The operation of the elastic buffer is
to attempt to maintain a constant occupancy by inserting or removing Idle sequences as
necessary. This causes no corruption to the frames of data.
When the GMII is used as an internal interface, it is expected that the entire interface will
be synchronous to a single clock domain and the Transmitter Elastic Buffer should be
discarded. See the Xilinx LogiCORE Ethernet 1000BASE-X PCS/PMA or SGMII User Guide
for information about connecting the core to an internal GMII (for example, an Ethernet
MAC).
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006
project_dir>/<component_name>/example_design/<component_name>_top.v
An instance of the Ethernet 1000BASE-X PCS/PMA core
Clock management logic, including DCM and Global Clock Buffer instances, where
required
GMII interface logic, including IOB and DDR registers instances, where required
A transmitter elastic buffer
TBI interface logic, including IOB and DDR registers instances, where required
Input and output buffers for other port signals of the top level
project_dir>/<component_name>/example_design/tx_elastic_buffer.vhd
project_dir>/<component_name>/example_design/tx_elastic_buffer.v
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