Xilinx LogiCORE Getting Started Manual page 25

Directory Structure and File Descriptions
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<project_dir>/implement
Note:
implement.sh
A UNIX shell script that processes the example design through the Xilinx tool flow. See
"Implementation Scripts," page 30
implement.bat
A Windows batch file that process the example design through the Xilinx tool flow. See
"Implementation Scripts," page 30
xst.prj
The XST project file for the example design; it enumerates all of the VHDL files that need
to be synthesized.
xst.scr
The XST script file for the example design.
<project_dir>/implement/results
This directory is produced by the implementation scripts and is used to run through the
example design and the core through the Xilinx implementation tools. Once the implement
script has completed it contains the following files for timing simulation.
routed.vhd
The back-annotated simprim based VHDL model used for timing simulation. This is
SIMPRIM-based.
routed.sdf
The timing information for simulation is contained in this file.
<project_dir>/<component_name>/simulation
The simulation directory and subdirectories that provide the files necessary to test a VHDL
implementation of the example design.
demo_tb.vhd
The VHDL demonstration test bench file for the example design. See the following for
more information.
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<project_dir>/<component_name>/simulation/functional
simulate_mti.do
A ModelSim® macro file that compiles the VHDL sources and then runs the functional
simulation to completion.
Ethernet 1000BASE-X PCS/PMA or SGMII v7.0
UG145 January 18, 2006
"Core Example Design with Ten-Bit Interface," page
"SGMII Example Design / Dynamic Switching Example Design," page
This directory is only present with the Full license.
"Core Example Design Using RocketIO," page
"Core Example Design with Ten-Bit Interface," page
"SGMII Example Design / Dynamic Switching Example Design," page
www.xilinx.com
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for more information.
for more information.
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